// SPDX-License-Identifier: GPL-2.0+ // // OWL S900 SoC clock driver // // Copyright (c) 2014 Actions Semi Inc. // Author: David Liu <[email protected]> // // Copyright (c) 2018 Linaro Ltd. // Author: Manivannan Sadhasivam <[email protected]> #include <linux/clk-provider.h> #include <linux/platform_device.h> #include "owl-common.h" #include "owl-composite.h" #include "owl-divider.h" #include "owl-factor.h" #include "owl-fixed-factor.h" #include "owl-gate.h" #include "owl-mux.h" #include "owl-pll.h" #include "owl-reset.h" #include <dt-bindings/clock/actions,s900-cmu.h> #include <dt-bindings/reset/actions,s900-reset.h> #define CMU_COREPLL … #define CMU_DEVPLL … #define CMU_DDRPLL … #define CMU_NANDPLL … #define CMU_DISPLAYPLL … #define CMU_AUDIOPLL … #define CMU_TVOUTPLL … #define CMU_BUSCLK … #define CMU_SENSORCLK … #define CMU_LCDCLK … #define CMU_DSICLK … #define CMU_CSICLK … #define CMU_DECLK … #define CMU_BISPCLK … #define CMU_IMXCLK … #define CMU_HDECLK … #define CMU_VDECLK … #define CMU_VCECLK … #define CMU_NANDCCLK … #define CMU_SD0CLK … #define CMU_SD1CLK … #define CMU_SD2CLK … #define CMU_UART0CLK … #define CMU_UART1CLK … #define CMU_UART2CLK … #define CMU_PWM0CLK … #define CMU_PWM1CLK … #define CMU_PWM2CLK … #define CMU_PWM3CLK … #define CMU_USBPLL … #define CMU_ASSISTPLL … #define CMU_EDPCLK … #define CMU_GPU3DCLK … #define CMU_CORECTL … #define CMU_DEVCLKEN0 … #define CMU_DEVCLKEN1 … #define CMU_DEVRST0 … #define CMU_DEVRST1 … #define CMU_UART3CLK … #define CMU_UART4CLK … #define CMU_UART5CLK … #define CMU_UART6CLK … #define CMU_TLSCLK … #define CMU_SD3CLK … #define CMU_PWM4CLK … #define CMU_PWM5CLK … static struct clk_pll_table clk_audio_pll_table[] = …; static struct clk_pll_table clk_edp_pll_table[] = …; /* pll clocks */ static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED); static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED); static const char *cpu_clk_mux_p[] = …; static const char *dev_clk_p[] = …; static const char *noc_clk_mux_p[] = …; static const char *dmm_clk_mux_p[] = …; static const char *bisp_clk_mux_p[] = …; static const char *csi_clk_mux_p[] = …; static const char *de_clk_mux_p[] = …; static const char *gpu_clk_mux_p[] = …; static const char *hde_clk_mux_p[] = …; static const char *imx_clk_mux_p[] = …; static const char *lcd_clk_mux_p[] = …; static const char *nand_clk_mux_p[] = …; static const char *sd_clk_mux_p[] = …; static const char *sensor_clk_mux_p[] = …; static const char *uart_clk_mux_p[] = …; static const char *vce_clk_mux_p[] = …; static const char *i2s_clk_mux_p[] = …; static const char *edp_clk_mux_p[] = …; /* mux clocks */ static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT); static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT); static struct clk_div_table nand_div_table[] = …; static struct clk_div_table apb_div_table[] = …; static struct clk_div_table eth_mac_div_table[] = …; static struct clk_div_table rmii_ref_div_table[] = …; static struct clk_div_table usb3_mac_div_table[] = …; static struct clk_div_table i2s_div_table[] = …; static struct clk_div_table hdmia_div_table[] = …; /* divider clocks */ static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0); static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0); static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0); static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0); static struct clk_factor_table sd_factor_table[] = …; static struct clk_factor_table dmm_factor_table[] = …; static struct clk_factor_table noc_factor_table[] = …; static struct clk_factor_table bisp_factor_table[] = …; /* factor clocks */ static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0); static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0); /* gate clocks */ static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0); static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0); static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0); static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED); static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED); static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0); static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0); static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0); static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0); static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0); static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0); static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0); static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0); static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0); static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0); static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0); static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0); static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED); /* composite clocks */ static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, OWL_MUX_HW(CMU_BISPCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), 0); static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p, OWL_MUX_HW(CMU_CSICLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0), OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL), 0); static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p, OWL_MUX_HW(CMU_CSICLK, 20, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0), OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL), 0); static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p, OWL_MUX_HW(CMU_DECLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), 0); static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK, 10, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0), OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table), CLK_IGNORE_UNUSED); static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p, OWL_MUX_HW(CMU_EDPCLK, 19, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0), OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table), 0); static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table), 0); static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p, OWL_MUX_HW(CMU_GPU3DCLK, 4, 2), OWL_GATE_HW(CMU_GPU3DCLK, 15, 0), OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table), 0); static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p, OWL_MUX_HW(CMU_GPU3DCLK, 20, 2), OWL_GATE_HW(CMU_GPU3DCLK, 14, 0), OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table), 0); static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p, OWL_MUX_HW(CMU_GPU3DCLK, 28, 2), OWL_GATE_HW(CMU_GPU3DCLK, 13, 0), OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table), 0); static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_HDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0), OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table), 0); static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table), 0); static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0), 1, 5, 0); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table), 0); static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table), 0); static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p, OWL_MUX_HW(CMU_IMXCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0), OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table), 0); static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p, OWL_MUX_HW(CMU_LCDCLK, 12, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0), OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL), 0); static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p, OWL_MUX_HW(CMU_NANDCCLK, 8, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table), CLK_SET_RATE_PARENT); static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p, OWL_MUX_HW(CMU_NANDCCLK, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table), CLK_SET_RATE_PARENT); static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL), 0); static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0), OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL), 0); /* * pwm2 may be for backlight, do not gate it * even it is "unused", because it may be * enabled at boot stage, and in kernel, driver * has no effective method to know the real status, * so, the best way is keeping it as what it was. */ static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0), OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL), 0); static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0), OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL), 0); static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0), OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL), 0); static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0), OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD1CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0), OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD2CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0), OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD3CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0), OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL), 0); static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0), OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL), 0); static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk", "hosc", OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0), OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL), 0); static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART1CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0), OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), 0); static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), 0); static struct owl_clk_common *s900_clks[] = …; static struct clk_hw_onecell_data s900_hw_clks = …; static const struct owl_reset_map s900_resets[] = …; static struct owl_clk_desc s900_clk_desc = …; static int s900_clk_probe(struct platform_device *pdev) { … } static const struct of_device_id s900_clk_of_match[] = …; static struct platform_driver s900_clk_driver = …; static int __init s900_clk_init(void) { … } core_initcall(s900_clk_init);
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