/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __SDHCI_PCI_H #define __SDHCI_PCI_H /* * PCI device IDs, sub IDs */ #define PCI_DEVICE_ID_O2_SDS0 … #define PCI_DEVICE_ID_O2_SDS1 … #define PCI_DEVICE_ID_O2_FUJIN2 … #define PCI_DEVICE_ID_O2_SEABIRD0 … #define PCI_DEVICE_ID_O2_SEABIRD1 … #define PCI_DEVICE_ID_O2_GG8_9860 … #define PCI_DEVICE_ID_O2_GG8_9861 … #define PCI_DEVICE_ID_O2_GG8_9862 … #define PCI_DEVICE_ID_O2_GG8_9863 … #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 … #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 … #define PCI_DEVICE_ID_INTEL_BYT_EMMC … #define PCI_DEVICE_ID_INTEL_BYT_SDIO … #define PCI_DEVICE_ID_INTEL_BYT_SD … #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 … #define PCI_DEVICE_ID_INTEL_BSW_EMMC … #define PCI_DEVICE_ID_INTEL_BSW_SDIO … #define PCI_DEVICE_ID_INTEL_BSW_SD … #define PCI_DEVICE_ID_INTEL_MRFLD_MMC … #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 … #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 … #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 … #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 … #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 … #define PCI_DEVICE_ID_INTEL_QRK_SD … #define PCI_DEVICE_ID_INTEL_SPT_EMMC … #define PCI_DEVICE_ID_INTEL_SPT_SDIO … #define PCI_DEVICE_ID_INTEL_SPT_SD … #define PCI_DEVICE_ID_INTEL_DNV_EMMC … #define PCI_DEVICE_ID_INTEL_CDF_EMMC … #define PCI_DEVICE_ID_INTEL_BXT_SD … #define PCI_DEVICE_ID_INTEL_BXT_EMMC … #define PCI_DEVICE_ID_INTEL_BXT_SDIO … #define PCI_DEVICE_ID_INTEL_BXTM_SD … #define PCI_DEVICE_ID_INTEL_BXTM_EMMC … #define PCI_DEVICE_ID_INTEL_BXTM_SDIO … #define PCI_DEVICE_ID_INTEL_APL_SD … #define PCI_DEVICE_ID_INTEL_APL_EMMC … #define PCI_DEVICE_ID_INTEL_APL_SDIO … #define PCI_DEVICE_ID_INTEL_GLK_SD … #define PCI_DEVICE_ID_INTEL_GLK_EMMC … #define PCI_DEVICE_ID_INTEL_GLK_SDIO … #define PCI_DEVICE_ID_INTEL_CNP_EMMC … #define PCI_DEVICE_ID_INTEL_CNP_SD … #define PCI_DEVICE_ID_INTEL_CNPH_SD … #define PCI_DEVICE_ID_INTEL_ICP_EMMC … #define PCI_DEVICE_ID_INTEL_ICP_SD … #define PCI_DEVICE_ID_INTEL_EHL_EMMC … #define PCI_DEVICE_ID_INTEL_EHL_SD … #define PCI_DEVICE_ID_INTEL_CML_EMMC … #define PCI_DEVICE_ID_INTEL_CML_SD … #define PCI_DEVICE_ID_INTEL_CMLH_SD … #define PCI_DEVICE_ID_INTEL_JSL_EMMC … #define PCI_DEVICE_ID_INTEL_JSL_SD … #define PCI_DEVICE_ID_INTEL_LKF_EMMC … #define PCI_DEVICE_ID_INTEL_LKF_SD … #define PCI_DEVICE_ID_INTEL_ADL_EMMC … #define PCI_DEVICE_ID_SYSKONNECT_8000 … #define PCI_DEVICE_ID_VIA_95D0 … #define PCI_DEVICE_ID_REALTEK_5250 … #define PCI_SUBDEVICE_ID_NI_7884 … #define PCI_SUBDEVICE_ID_NI_78E3 … #define PCI_VENDOR_ID_ARASAN … #define PCI_DEVICE_ID_ARASAN_PHY_EMMC … #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC … #define PCI_DEVICE_ID_GLI_9755 … #define PCI_DEVICE_ID_GLI_9750 … #define PCI_DEVICE_ID_GLI_9763E … #define PCI_DEVICE_ID_GLI_9767 … /* * PCI device class and mask */ #define SYSTEM_SDHCI … #define PCI_CLASS_MASK … /* * Macros for PCI device-description */ #define _PCI_VEND(vend) … #define _PCI_DEV(vend, dev) … #define _PCI_SUBDEV(subvend, subdev) … #define SDHCI_PCI_DEVICE(vend, dev, cfg) … #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) … #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) … /* * PCI registers */ #define PCI_SDHCI_IFPIO … #define PCI_SDHCI_IFDMA … #define PCI_SDHCI_IFVENDOR … #define PCI_SLOT_INFO … #define PCI_SLOT_INFO_SLOTS(x) … #define PCI_SLOT_INFO_FIRST_BAR_MASK … #define MAX_SLOTS … struct sdhci_pci_chip; struct sdhci_pci_slot; struct sdhci_pci_fixes { … }; struct sdhci_pci_slot { … }; struct sdhci_pci_chip { … }; static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) { … } #ifdef CONFIG_PM_SLEEP int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); #endif int sdhci_pci_enable_dma(struct sdhci_host *host); extern const struct sdhci_pci_fixes sdhci_arasan; extern const struct sdhci_pci_fixes sdhci_snps; extern const struct sdhci_pci_fixes sdhci_o2; extern const struct sdhci_pci_fixes sdhci_gl9750; extern const struct sdhci_pci_fixes sdhci_gl9755; extern const struct sdhci_pci_fixes sdhci_gl9763e; extern const struct sdhci_pci_fixes sdhci_gl9767; #endif /* __SDHCI_PCI_H */
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