/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver * * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. */ #ifndef _DW_MMC_EXYNOS_H_ #define _DW_MMC_EXYNOS_H_ #define SDMMC_CLKSEL … #define SDMMC_CLKSEL64 … /* Extended Register's Offset */ #define SDMMC_HS400_DQS_EN … #define SDMMC_HS400_ASYNC_FIFO_CTRL … #define SDMMC_HS400_DLINE_CTRL … /* CLKSEL register defines */ #define SDMMC_CLKSEL_CCLK_SAMPLE(x) … #define SDMMC_CLKSEL_CCLK_DRIVE(x) … #define SDMMC_CLKSEL_CCLK_DIVIDER(x) … #define SDMMC_CLKSEL_GET_DRV_WD3(x) … #define SDMMC_CLKSEL_GET_DIV(x) … #define SDMMC_CLKSEL_UP_SAMPLE(x, y) … #define SDMMC_CLKSEL_TIMING(x, y, z) … #define SDMMC_CLKSEL_TIMING_MASK … #define SDMMC_CLKSEL_WAKEUP_INT … /* RCLK_EN register defines */ #define DATA_STROBE_EN … #define AXI_NON_BLOCKING_WR … /* DLINE_CTRL register defines */ #define DQS_CTRL_RD_DELAY(x, y) … #define DQS_CTRL_GET_RD_DELAY(x) … /* Protector Register */ #define SDMMC_EMMCP_BASE … #define SDMMC_MPSECURITY … #define SDMMC_MPSBEGIN0 … #define SDMMC_MPSEND0 … #define SDMMC_MPSCTRL0 … /* SMU control defines */ #define SDMMC_MPSCTRL_SECURE_READ_BIT … #define SDMMC_MPSCTRL_SECURE_WRITE_BIT … #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT … #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT … #define SDMMC_MPSCTRL_USE_FUSE_KEY … #define SDMMC_MPSCTRL_ECB_MODE … #define SDMMC_MPSCTRL_ENCRYPTION … #define SDMMC_MPSCTRL_VALID … /* Maximum number of Ending sector */ #define SDMMC_ENDING_SEC_NR_MAX … /* Fixed clock divider */ #define EXYNOS4210_FIXED_CIU_CLK_DIV … #define EXYNOS4412_FIXED_CIU_CLK_DIV … #define HS400_FIXED_CIU_CLK_DIV … /* Minimal required clock frequency for cclkin, unit: HZ */ #define EXYNOS_CCLKIN_MIN … #endif /* _DW_MMC_EXYNOS_H_ */
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