// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for sunxi SD/MMC host controllers * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. * (C) Copyright 2007-2011 Aaron Maoye <[email protected]> * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> * (C) Copyright 2013-2014 David Lanzendörfer <[email protected]> * (C) Copyright 2013-2014 Hans de Goede <[email protected]> * (C) Copyright 2017 Sootech SA */ #include <linux/clk.h> #include <linux/clk/sunxi-ng.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mmc/card.h> #include <linux/mmc/core.h> #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include <linux/mmc/sd.h> #include <linux/mmc/sdio.h> #include <linux/mmc/slot-gpio.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/scatterlist.h> #include <linux/slab.h> #include <linux/spinlock.h> /* register offset definitions */ #define SDXC_REG_GCTRL … #define SDXC_REG_CLKCR … #define SDXC_REG_TMOUT … #define SDXC_REG_WIDTH … #define SDXC_REG_BLKSZ … #define SDXC_REG_BCNTR … #define SDXC_REG_CMDR … #define SDXC_REG_CARG … #define SDXC_REG_RESP0 … #define SDXC_REG_RESP1 … #define SDXC_REG_RESP2 … #define SDXC_REG_RESP3 … #define SDXC_REG_IMASK … #define SDXC_REG_MISTA … #define SDXC_REG_RINTR … #define SDXC_REG_STAS … #define SDXC_REG_FTRGL … #define SDXC_REG_FUNS … #define SDXC_REG_CBCR … #define SDXC_REG_BBCR … #define SDXC_REG_DBGC … #define SDXC_REG_HWRST … #define SDXC_REG_DMAC … #define SDXC_REG_DLBA … #define SDXC_REG_IDST … #define SDXC_REG_IDIE … #define SDXC_REG_CHDA … #define SDXC_REG_CBDA … /* New registers introduced in A64 */ #define SDXC_REG_A12A … #define SDXC_REG_SD_NTSR … #define SDXC_REG_DRV_DL … #define SDXC_REG_SAMP_DL_REG … #define SDXC_REG_DS_DL_REG … #define mmc_readl(host, reg) … #define mmc_writel(host, reg, value) … /* global control register bits */ #define SDXC_SOFT_RESET … #define SDXC_FIFO_RESET … #define SDXC_DMA_RESET … #define SDXC_INTERRUPT_ENABLE_BIT … #define SDXC_DMA_ENABLE_BIT … #define SDXC_DEBOUNCE_ENABLE_BIT … #define SDXC_POSEDGE_LATCH_DATA … #define SDXC_DDR_MODE … #define SDXC_MEMORY_ACCESS_DONE … #define SDXC_ACCESS_DONE_DIRECT … #define SDXC_ACCESS_BY_AHB … #define SDXC_ACCESS_BY_DMA … #define SDXC_HARDWARE_RESET … /* clock control bits */ #define SDXC_MASK_DATA0 … #define SDXC_CARD_CLOCK_ON … #define SDXC_LOW_POWER_ON … /* bus width */ #define SDXC_WIDTH1 … #define SDXC_WIDTH4 … #define SDXC_WIDTH8 … /* smc command bits */ #define SDXC_RESP_EXPIRE … #define SDXC_LONG_RESPONSE … #define SDXC_CHECK_RESPONSE_CRC … #define SDXC_DATA_EXPIRE … #define SDXC_WRITE … #define SDXC_SEQUENCE_MODE … #define SDXC_SEND_AUTO_STOP … #define SDXC_WAIT_PRE_OVER … #define SDXC_STOP_ABORT_CMD … #define SDXC_SEND_INIT_SEQUENCE … #define SDXC_UPCLK_ONLY … #define SDXC_READ_CEATA_DEV … #define SDXC_CCS_EXPIRE … #define SDXC_ENABLE_BIT_BOOT … #define SDXC_ALT_BOOT_OPTIONS … #define SDXC_BOOT_ACK_EXPIRE … #define SDXC_BOOT_ABORT … #define SDXC_VOLTAGE_SWITCH … #define SDXC_USE_HOLD_REGISTER … #define SDXC_START … /* interrupt bits */ #define SDXC_RESP_ERROR … #define SDXC_COMMAND_DONE … #define SDXC_DATA_OVER … #define SDXC_TX_DATA_REQUEST … #define SDXC_RX_DATA_REQUEST … #define SDXC_RESP_CRC_ERROR … #define SDXC_DATA_CRC_ERROR … #define SDXC_RESP_TIMEOUT … #define SDXC_DATA_TIMEOUT … #define SDXC_VOLTAGE_CHANGE_DONE … #define SDXC_FIFO_RUN_ERROR … #define SDXC_HARD_WARE_LOCKED … #define SDXC_START_BIT_ERROR … #define SDXC_AUTO_COMMAND_DONE … #define SDXC_END_BIT_ERROR … #define SDXC_SDIO_INTERRUPT … #define SDXC_CARD_INSERT … #define SDXC_CARD_REMOVE … #define SDXC_INTERRUPT_ERROR_BIT … #define SDXC_INTERRUPT_DONE_BIT … /* status */ #define SDXC_RXWL_FLAG … #define SDXC_TXWL_FLAG … #define SDXC_FIFO_EMPTY … #define SDXC_FIFO_FULL … #define SDXC_CARD_PRESENT … #define SDXC_CARD_DATA_BUSY … #define SDXC_DATA_FSM_BUSY … #define SDXC_DMA_REQUEST … #define SDXC_FIFO_SIZE … /* Function select */ #define SDXC_CEATA_ON … #define SDXC_SEND_IRQ_RESPONSE … #define SDXC_SDIO_READ_WAIT … #define SDXC_ABORT_READ_DATA … #define SDXC_SEND_CCSD … #define SDXC_SEND_AUTO_STOPCCSD … #define SDXC_CEATA_DEV_IRQ_ENABLE … /* IDMA controller bus mod bit field */ #define SDXC_IDMAC_SOFT_RESET … #define SDXC_IDMAC_FIX_BURST … #define SDXC_IDMAC_IDMA_ON … #define SDXC_IDMAC_REFETCH_DES … /* IDMA status bit field */ #define SDXC_IDMAC_TRANSMIT_INTERRUPT … #define SDXC_IDMAC_RECEIVE_INTERRUPT … #define SDXC_IDMAC_FATAL_BUS_ERROR … #define SDXC_IDMAC_DESTINATION_INVALID … #define SDXC_IDMAC_CARD_ERROR_SUM … #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM … #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM … #define SDXC_IDMAC_HOST_ABORT_INTERRUPT … #define SDXC_IDMAC_IDLE … #define SDXC_IDMAC_SUSPEND … #define SDXC_IDMAC_DESC_READ … #define SDXC_IDMAC_DESC_CHECK … #define SDXC_IDMAC_READ_REQUEST_WAIT … #define SDXC_IDMAC_WRITE_REQUEST_WAIT … #define SDXC_IDMAC_READ … #define SDXC_IDMAC_WRITE … #define SDXC_IDMAC_DESC_CLOSE … /* * If the idma-des-size-bits of property is ie 13, bufsize bits are: * Bits 0-12: buf1 size * Bits 13-25: buf2 size * Bits 26-31: not used * Since we only ever set buf1 size, we can simply store it directly. */ #define SDXC_IDMAC_DES0_DIC … #define SDXC_IDMAC_DES0_LD … #define SDXC_IDMAC_DES0_FD … #define SDXC_IDMAC_DES0_CH … #define SDXC_IDMAC_DES0_ER … #define SDXC_IDMAC_DES0_CES … #define SDXC_IDMAC_DES0_OWN … #define SDXC_CLK_400K … #define SDXC_CLK_25M … #define SDXC_CLK_50M … #define SDXC_CLK_50M_DDR … #define SDXC_CLK_50M_DDR_8BIT … #define SDXC_2X_TIMING_MODE … #define SDXC_CAL_START … #define SDXC_CAL_DONE … #define SDXC_CAL_DL_SHIFT … #define SDXC_CAL_DL_SW_EN … #define SDXC_CAL_DL_SW_SHIFT … #define SDXC_CAL_DL_MASK … #define SDXC_CAL_TIMEOUT … struct sunxi_mmc_clk_delay { … }; struct sunxi_idma_des { … }; struct sunxi_mmc_cfg { … }; struct sunxi_mmc_host { … }; static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) { … } static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) { … } static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, struct mmc_data *data) { … } static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, struct mmc_data *data) { … } static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, struct mmc_data *data) { … } static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, struct mmc_request *req) { … } static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) { … } /* Called in interrupt context! */ static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) { … } static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) { … } static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) { … } static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) { … } static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) { … } static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, struct mmc_ios *ios, u32 rate) { … } static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, struct mmc_ios *ios) { … } static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, unsigned char width) { … } static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) { … } static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, struct mmc_ios *ios) { … } static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { … } static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) { … } static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) { … } static void sunxi_mmc_hw_reset(struct mmc_host *mmc) { … } static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) { … } static int sunxi_mmc_card_busy(struct mmc_host *mmc) { … } static const struct mmc_host_ops sunxi_mmc_ops = …; static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = …; static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = …; static const struct sunxi_mmc_cfg sun4i_a10_cfg = …; static const struct sunxi_mmc_cfg sun5i_a13_cfg = …; static const struct sunxi_mmc_cfg sun7i_a20_cfg = …; static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = …; static const struct sunxi_mmc_cfg sun9i_a80_cfg = …; static const struct sunxi_mmc_cfg sun20i_d1_cfg = …; static const struct sunxi_mmc_cfg sun50i_a64_cfg = …; static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = …; static const struct sunxi_mmc_cfg sun50i_a100_cfg = …; static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = …; static const struct of_device_id sunxi_mmc_of_match[] = …; MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); static int sunxi_mmc_enable(struct sunxi_mmc_host *host) { … } static void sunxi_mmc_disable(struct sunxi_mmc_host *host) { … } static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, struct platform_device *pdev) { … } static int sunxi_mmc_probe(struct platform_device *pdev) { … } static void sunxi_mmc_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM static int sunxi_mmc_runtime_resume(struct device *dev) { … } static int sunxi_mmc_runtime_suspend(struct device *dev) { … } #endif static const struct dev_pm_ops sunxi_mmc_pm_ops = …; static struct platform_driver sunxi_mmc_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_ALIAS(…) …;
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