/* SPDX-License-Identifier: GPL-2.0-only */ /* * Freescale eSDHC controller driver generics for OF and pltfm. * * Copyright (c) 2007 Freescale Semiconductor, Inc. * Copyright (c) 2009 MontaVista Software, Inc. * Copyright (c) 2010 Pengutronix e.K. * Copyright 2020 NXP * Author: Wolfram Sang <[email protected]> */ #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H #define _DRIVERS_MMC_SDHCI_ESDHC_H /* * Ops and quirks for the Freescale eSDHC controller. */ #define ESDHC_DEFAULT_QUIRKS … /* pltfm-specific */ #define ESDHC_HOST_CONTROL_LE … /* * eSDHC register definition */ /* Present State Register */ #define ESDHC_PRSSTAT … #define ESDHC_CLOCK_GATE_OFF … #define ESDHC_CLOCK_STABLE … /* Protocol Control Register */ #define ESDHC_PROCTL … #define ESDHC_VOLT_SEL … #define ESDHC_CTRL_4BITBUS … #define ESDHC_CTRL_8BITBUS … #define ESDHC_CTRL_BUSWIDTH_MASK … #define ESDHC_HOST_CONTROL_RES … /* System Control Register */ #define ESDHC_SYSTEM_CONTROL … #define ESDHC_CLOCK_MASK … #define ESDHC_PREDIV_SHIFT … #define ESDHC_DIVIDER_SHIFT … #define ESDHC_CLOCK_SDCLKEN … #define ESDHC_CLOCK_PEREN … #define ESDHC_CLOCK_HCKEN … #define ESDHC_CLOCK_IPGEN … /* System Control 2 Register */ #define ESDHC_SYSTEM_CONTROL_2 … #define ESDHC_SMPCLKSEL … #define ESDHC_EXTN … /* Host Controller Capabilities Register 2 */ #define ESDHC_CAPABILITIES_1 … /* Tuning Block Control Register */ #define ESDHC_TBCTL … #define ESDHC_HS400_WNDW_ADJUST … #define ESDHC_HS400_MODE … #define ESDHC_TB_EN … #define ESDHC_TB_MODE_MASK … #define ESDHC_TB_MODE_SW … #define ESDHC_TB_MODE_3 … #define ESDHC_TBSTAT … #define ESDHC_TBPTR … #define ESDHC_WNDW_STRT_PTR_SHIFT … #define ESDHC_WNDW_STRT_PTR_MASK … #define ESDHC_WNDW_END_PTR_MASK … /* SD Clock Control Register */ #define ESDHC_SDCLKCTL … #define ESDHC_LPBK_CLK_SEL … #define ESDHC_CMD_CLK_CTL … /* SD Timing Control Register */ #define ESDHC_SDTIMNGCTL … #define ESDHC_FLW_CTL_BG … /* DLL Config 0 Register */ #define ESDHC_DLLCFG0 … #define ESDHC_DLL_ENABLE … #define ESDHC_DLL_RESET … #define ESDHC_DLL_FREQ_SEL … /* DLL Config 1 Register */ #define ESDHC_DLLCFG1 … #define ESDHC_DLL_PD_PULSE_STRETCH_SEL … /* DLL Status 0 Register */ #define ESDHC_DLLSTAT0 … #define ESDHC_DLL_STS_SLV_LOCK … /* Control Register for DMA transfer */ #define ESDHC_DMA_SYSCTL … #define ESDHC_PERIPHERAL_CLK_SEL … #define ESDHC_FLUSH_ASYNC_FIFO … #define ESDHC_DMA_SNOOP … #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
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