// SPDX-License-Identifier: GPL-2.0-only /* * Support for SDHCI on STMicroelectronics SoCs * * Copyright (C) 2014 STMicroelectronics Ltd * Author: Giuseppe Cavallaro <[email protected]> * Contributors: Peter Griffin <[email protected]> * * Based on sdhci-cns3xxx.c */ #include <linux/io.h> #include <linux/of.h> #include <linux/module.h> #include <linux/err.h> #include <linux/mmc/host.h> #include <linux/reset.h> #include "sdhci-pltfm.h" struct st_mmc_platform_data { … }; /* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */ #define ST_MMC_CCONFIG_REG_1 … #define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT … #define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ … #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT … #define ST_MMC_CCONFIG_ASYNC_WAKEUP … #define ST_MMC_CCONFIG_1_DEFAULT … #define ST_MMC_CCONFIG_REG_2 … #define ST_MMC_CCONFIG_HIGH_SPEED … #define ST_MMC_CCONFIG_ADMA2 … #define ST_MMC_CCONFIG_8BIT … #define ST_MMC_CCONFIG_MAX_BLK_LEN … #define MAX_BLK_LEN_1024 … #define MAX_BLK_LEN_2048 … #define BASE_CLK_FREQ_200 … #define BASE_CLK_FREQ_100 … #define BASE_CLK_FREQ_50 … #define ST_MMC_CCONFIG_2_DEFAULT … #define ST_MMC_CCONFIG_REG_3 … #define ST_MMC_CCONFIG_EMMC_SLOT_TYPE … #define ST_MMC_CCONFIG_64BIT … #define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT … #define ST_MMC_CCONFIG_1P8_VOLT … #define ST_MMC_CCONFIG_3P0_VOLT … #define ST_MMC_CCONFIG_3P3_VOLT … #define ST_MMC_CCONFIG_SUSP_RES_SUPPORT … #define ST_MMC_CCONFIG_SDMA … #define ST_MMC_CCONFIG_3_DEFAULT … #define ST_MMC_CCONFIG_REG_4 … #define ST_MMC_CCONFIG_D_DRIVER … #define ST_MMC_CCONFIG_C_DRIVER … #define ST_MMC_CCONFIG_A_DRIVER … #define ST_MMC_CCONFIG_DDR50 … #define ST_MMC_CCONFIG_SDR104 … #define ST_MMC_CCONFIG_SDR50 … #define ST_MMC_CCONFIG_4_DEFAULT … #define ST_MMC_CCONFIG_REG_5 … #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 … #define RETUNING_TIMER_CNT_MAX … #define ST_MMC_CCONFIG_5_DEFAULT … /* I/O configuration for Arasan IP */ #define ST_MMC_GP_OUTPUT … #define ST_MMC_GP_OUTPUT_CD … #define ST_MMC_STATUS_R … #define ST_TOP_MMC_DLY_FIX_OFF(x) … /* TOP config registers to manage static and dynamic delay */ #define ST_TOP_MMC_TX_CLK_DLY … #define ST_TOP_MMC_RX_CLK_DLY … /* MMC delay control register */ #define ST_TOP_MMC_DLY_CTRL … #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD … #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL … #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE … #define ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE … #define ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY … #define ST_TOP_MMC_START_DLL_LOCK … /* register to provide the phase-shift value for DLL */ #define ST_TOP_MMC_TX_DLL_STEP_DLY … #define ST_TOP_MMC_RX_DLL_STEP_DLY … #define ST_TOP_MMC_RX_CMD_STEP_DLY … /* phase shift delay on the tx clk 2.188ns */ #define ST_TOP_MMC_TX_DLL_STEP_DLY_VALID … #define ST_TOP_MMC_DLY_MAX … #define ST_TOP_MMC_DYN_DLY_CONF … /* * For clock speeds greater than 90MHz, we need to check that the * DLL procedure has finished before switching to ultra-speed modes. */ #define CLK_TO_CHECK_DLL_LOCK … static inline void st_mmcss_set_static_delay(void __iomem *ioaddr) { … } /** * st_mmcss_cconfig: configure the Arasan HC inside the flashSS. * @np: dt device node. * @host: sdhci host * Description: this function is to configure the Arasan host controller. * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5 * or eMMC4.3. This has to be done before registering the sdhci host. */ static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host) { … } static inline void st_mmcss_set_dll(void __iomem *ioaddr) { … } static int st_mmcss_lock_dll(void __iomem *ioaddr) { … } static int sdhci_st_set_dll_for_clock(struct sdhci_host *host) { … } static void sdhci_st_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) { … } static u32 sdhci_st_readl(struct sdhci_host *host, int reg) { … } static const struct sdhci_ops sdhci_st_ops = …; static const struct sdhci_pltfm_data sdhci_st_pdata = …; static int sdhci_st_probe(struct platform_device *pdev) { … } static void sdhci_st_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int sdhci_st_suspend(struct device *dev) { … } static int sdhci_st_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(sdhci_st_pmops, sdhci_st_suspend, sdhci_st_resume); static const struct of_device_id st_sdhci_match[] = …; MODULE_DEVICE_TABLE(of, st_sdhci_match); static struct platform_driver sdhci_st_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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