// SPDX-License-Identifier: GPL-2.0-only /* * SDHCI Controller driver for TI's OMAP SoCs * * Copyright (C) 2017 Texas Instruments * Author: Kishon Vijay Abraham I <[email protected]> */ #include <linux/delay.h> #include <linux/mmc/mmc.h> #include <linux/mmc/slot-gpio.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/pm_wakeirq.h> #include <linux/regulator/consumer.h> #include <linux/pinctrl/consumer.h> #include <linux/sys_soc.h> #include <linux/thermal.h> #include "sdhci-pltfm.h" /* * Note that the register offsets used here are from omap_regs * base which is 0x100 for omap4 and later, and 0 for omap3 and * earlier. */ #define SDHCI_OMAP_SYSCONFIG … #define SDHCI_OMAP_CON … #define CON_DW8 … #define CON_DMA_MASTER … #define CON_DDR … #define CON_CLKEXTFREE … #define CON_PADEN … #define CON_CTPL … #define CON_INIT … #define CON_OD … #define SDHCI_OMAP_DLL … #define DLL_SWT … #define DLL_FORCE_SR_C_SHIFT … #define DLL_FORCE_SR_C_MASK … #define DLL_FORCE_VALUE … #define DLL_CALIB … #define SDHCI_OMAP_CMD … #define SDHCI_OMAP_PSTATE … #define PSTATE_DLEV_DAT0 … #define PSTATE_DATI … #define SDHCI_OMAP_HCTL … #define HCTL_SDBP … #define HCTL_SDVS_SHIFT … #define HCTL_SDVS_MASK … #define HCTL_SDVS_33 … #define HCTL_SDVS_30 … #define HCTL_SDVS_18 … #define SDHCI_OMAP_SYSCTL … #define SYSCTL_CEN … #define SYSCTL_CLKD_SHIFT … #define SYSCTL_CLKD_MASK … #define SDHCI_OMAP_STAT … #define SDHCI_OMAP_IE … #define INT_CC_EN … #define SDHCI_OMAP_ISE … #define SDHCI_OMAP_AC12 … #define AC12_V1V8_SIGEN … #define AC12_SCLK_SEL … #define SDHCI_OMAP_CAPA … #define CAPA_VS33 … #define CAPA_VS30 … #define CAPA_VS18 … #define SDHCI_OMAP_CAPA2 … #define CAPA2_TSDR50 … #define SDHCI_OMAP_TIMEOUT … #define SYSCTL_CLKD_MAX … #define IOV_1V8 … #define IOV_3V0 … #define IOV_3V3 … #define MAX_PHASE_DELAY … /* sdhci-omap controller flags */ #define SDHCI_OMAP_REQUIRE_IODELAY … #define SDHCI_OMAP_SPECIAL_RESET … struct sdhci_omap_data { … }; struct sdhci_omap_host { … }; static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host); static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, unsigned int offset) { … } static inline void sdhci_omap_writel(struct sdhci_omap_host *host, unsigned int offset, u32 data) { … } static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, bool power_on, unsigned int iov) { … } static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, unsigned int iov_pbias) { … } static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, unsigned char signal_voltage) { … } static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable) { … } static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host, int count) { … } static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host) { … } static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) { … } static int sdhci_omap_card_busy(struct mmc_host *mmc) { … } static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) { … } static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) { … } static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, u8 power_mode) { … } static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host, unsigned int mode) { … } static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { … } static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host, unsigned int clock) { … } static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host) { … } static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host) { … } static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock) { … } static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { … } /* * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance * is connected to L3 interconnect and is bus master capable. Note that * the MMCHS_HL_HWINFO register is in the module registers before the * omap registers and sdhci registers. The offset can vary for omap * registers depending on the SoC. Do not use sdhci_omap_readl() here. */ static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset) { … } static int sdhci_omap_enable_dma(struct sdhci_host *host) { … } static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host) { … } static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width) { … } static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode) { … } static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { … } #define MMC_TIMEOUT_US … static void sdhci_omap_reset(struct sdhci_host *host, u8 mask) { … } #define CMD_ERR_MASK … #define CMD_MASK … static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask) { … } static void sdhci_omap_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) { … } static const struct sdhci_ops sdhci_omap_ops = …; static unsigned int sdhci_omap_regulator_get_caps(struct device *dev, const char *name) { … } static int sdhci_omap_set_capabilities(struct sdhci_host *host) { … } static const struct sdhci_pltfm_data sdhci_omap_pdata = …; static const struct sdhci_omap_data omap2430_data = …; static const struct sdhci_omap_data omap3_data = …; static const struct sdhci_omap_data omap4_data = …; static const struct sdhci_omap_data omap5_data = …; static const struct sdhci_omap_data k2g_data = …; static const struct sdhci_omap_data am335_data = …; static const struct sdhci_omap_data am437_data = …; static const struct sdhci_omap_data dra7_data = …; static const struct of_device_id omap_sdhci_match[] = …; MODULE_DEVICE_TABLE(of, omap_sdhci_match); static struct pinctrl_state *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode, u32 *caps, u32 capmask) { … } static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host) { … } static const struct soc_device_attribute sdhci_omap_soc_devices[] = …; static int sdhci_omap_probe(struct platform_device *pdev) { … } static void sdhci_omap_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM static void __maybe_unused sdhci_omap_context_save(struct sdhci_omap_host *omap_host) { … } /* Order matters here, HCTL must be restored in two phases */ static void __maybe_unused sdhci_omap_context_restore(struct sdhci_omap_host *omap_host) { … } static int __maybe_unused sdhci_omap_runtime_suspend(struct device *dev) { … } static int __maybe_unused sdhci_omap_runtime_resume(struct device *dev) { … } #endif static const struct dev_pm_ops sdhci_omap_dev_pm_ops = …; static struct platform_driver sdhci_omap_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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