// SPDX-License-Identifier: GPL-2.0-only /* * PHY support for Xenon SDHC * * Copyright (C) 2016 Marvell, All Rights Reserved. * * Author: Hu Ziji <[email protected]> * Date: 2016-8-24 */ #include <linux/slab.h> #include <linux/delay.h> #include <linux/ktime.h> #include <linux/iopoll.h> #include <linux/of_address.h> #include "sdhci-pltfm.h" #include "sdhci-xenon.h" /* Register base for eMMC PHY 5.0 Version */ #define XENON_EMMC_5_0_PHY_REG_BASE … /* Register base for eMMC PHY 5.1 Version */ #define XENON_EMMC_PHY_REG_BASE … #define XENON_EMMC_PHY_TIMING_ADJUST … #define XENON_EMMC_5_0_PHY_TIMING_ADJUST … #define XENON_TIMING_ADJUST_SLOW_MODE … #define XENON_TIMING_ADJUST_SDIO_MODE … #define XENON_SAMPL_INV_QSP_PHASE_SELECT … #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT … #define XENON_PHY_INITIALIZAION … #define XENON_WAIT_CYCLE_BEFORE_USING_MASK … #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT … #define XENON_FC_SYNC_EN_DURATION_MASK … #define XENON_FC_SYNC_EN_DURATION_SHIFT … #define XENON_FC_SYNC_RST_EN_DURATION_MASK … #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT … #define XENON_FC_SYNC_RST_DURATION_MASK … #define XENON_FC_SYNC_RST_DURATION_SHIFT … #define XENON_EMMC_PHY_FUNC_CONTROL … #define XENON_EMMC_5_0_PHY_FUNC_CONTROL … #define XENON_ASYNC_DDRMODE_MASK … #define XENON_ASYNC_DDRMODE_SHIFT … #define XENON_CMD_DDR_MODE … #define XENON_DQ_DDR_MODE_SHIFT … #define XENON_DQ_DDR_MODE_MASK … #define XENON_DQ_ASYNC_MODE … #define XENON_EMMC_PHY_PAD_CONTROL … #define XENON_EMMC_5_0_PHY_PAD_CONTROL … #define XENON_REC_EN_SHIFT … #define XENON_REC_EN_MASK … #define XENON_FC_DQ_RECEN … #define XENON_FC_CMD_RECEN … #define XENON_FC_QSP_RECEN … #define XENON_FC_QSN_RECEN … #define XENON_OEN_QSN … #define XENON_AUTO_RECEN_CTRL … #define XENON_FC_ALL_CMOS_RECEIVER … #define XENON_EMMC5_FC_QSP_PD … #define XENON_EMMC5_FC_QSP_PU … #define XENON_EMMC5_FC_CMD_PD … #define XENON_EMMC5_FC_CMD_PU … #define XENON_EMMC5_FC_DQ_PD … #define XENON_EMMC5_FC_DQ_PU … #define XENON_EMMC_PHY_PAD_CONTROL1 … #define XENON_EMMC5_1_FC_QSP_PD … #define XENON_EMMC5_1_FC_QSP_PU … #define XENON_EMMC5_1_FC_CMD_PD … #define XENON_EMMC5_1_FC_CMD_PU … #define XENON_EMMC5_1_FC_DQ_PD … #define XENON_EMMC5_1_FC_DQ_PU … #define XENON_EMMC_PHY_PAD_CONTROL2 … #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 … #define XENON_ZNR_MASK … #define XENON_ZNR_SHIFT … #define XENON_ZPR_MASK … /* Preferred ZNR and ZPR value vary between different boards. * The specific ZNR and ZPR value should be defined here * according to board actual timing. */ #define XENON_ZNR_DEF_VALUE … #define XENON_ZPR_DEF_VALUE … #define XENON_EMMC_PHY_DLL_CONTROL … #define XENON_EMMC_5_0_PHY_DLL_CONTROL … #define XENON_DLL_ENABLE … #define XENON_DLL_UPDATE_STROBE_5_0 … #define XENON_DLL_REFCLK_SEL … #define XENON_DLL_UPDATE … #define XENON_DLL_PHSEL1_SHIFT … #define XENON_DLL_PHSEL0_SHIFT … #define XENON_DLL_PHASE_MASK … #define XENON_DLL_PHASE_90_DEGREE … #define XENON_DLL_FAST_LOCK … #define XENON_DLL_GAIN2X … #define XENON_DLL_BYPASS_EN … #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST … #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE … #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST … #define XENON_LOGIC_TIMING_VALUE … #define XENON_MAX_PHY_TIMEOUT_LOOPS … /* * List offset of PHY registers and some special register values * in eMMC PHY 5.0 or eMMC PHY 5.1 */ struct xenon_emmc_phy_regs { … }; static const char * const phy_types[] = …; enum xenon_phy_type_enum { … }; enum soc_pad_ctrl_type { … }; struct soc_pad_ctrl { … }; static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = …; static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = …; /* * eMMC PHY configuration and operations */ struct xenon_emmc_phy_params { … }; static int xenon_alloc_emmc_phy(struct sdhci_host *host) { … } static int xenon_check_stability_internal_clk(struct sdhci_host *host) { … } /* * eMMC 5.0/5.1 PHY init/re-init. * eMMC PHY init should be executed after: * 1. SDCLK frequency changes. * 2. SDCLK is stopped and re-enabled. * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl * are changed */ static int xenon_emmc_phy_init(struct sdhci_host *host) { … } #define ARMADA_3700_SOC_PAD_1_8V … #define ARMADA_3700_SOC_PAD_3_3V … static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, unsigned char signal_voltage) { … } /* * Set SoC PHY voltage PAD control register, * according to the operation voltage on PAD. * The detailed operation depends on SoC implementation. */ static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, unsigned char signal_voltage) { … } /* * Enable eMMC PHY HW DLL * DLL should be enabled and stable before HS200/SDR104 tuning, * and before HS400 data strobe setting. */ static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) { … } /* * Config to eMMC PHY to prepare for tuning. * Enable HW DLL and set the TUNING_STEP */ static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) { … } static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host) { … } /* Set HS400 Data Strobe and Enhanced Strobe */ static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host) { … } /* * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) * in SDR mode, enable Slow Mode to bypass eMMC PHY. * SDIO slower SDR mode also requires Slow Mode. * * If Slow Mode is enabled, return true. * Otherwise, return false. */ static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host, unsigned char timing) { … } /* * Set-up eMMC 5.0/5.1 PHY. * Specific configuration depends on the current speed mode in use. */ static void xenon_emmc_phy_set(struct sdhci_host *host, unsigned char timing) { … } static int get_dt_pad_ctrl_data(struct sdhci_host *host, struct device_node *np, struct xenon_emmc_phy_params *params) { … } static int xenon_emmc_phy_parse_params(struct sdhci_host *host, struct device *dev, struct xenon_emmc_phy_params *params) { … } /* Set SoC PHY Voltage PAD */ void xenon_soc_pad_ctrl(struct sdhci_host *host, unsigned char signal_voltage) { … } /* * Setting PHY when card is working in High Speed Mode. * HS400 set Data Strobe and Enhanced Strobe if it is supported. * HS200/SDR104 set tuning config to prepare for tuning. */ static int xenon_hs_delay_adj(struct sdhci_host *host) { … } /* * Adjust PHY setting. * PHY setting should be adjusted when SDCLK frequency, Bus Width * or Speed Mode is changed. * Additional config are required when card is working in High Speed mode, * after leaving Legacy Mode. */ int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios) { … } static int xenon_add_phy(struct device *dev, struct sdhci_host *host, const char *phy_name) { … } int xenon_phy_parse_params(struct device *dev, struct sdhci_host *host) { … }
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