/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017, HiSilicon. All rights reserved. */ #ifndef UFS_HISI_H_ #define UFS_HISI_H_ #define HBRN8_POLL_TOUT_MS … /* * ufs sysctrl specific define */ #define PSW_POWER_CTRL … #define PHY_ISO_EN … #define HC_LP_CTRL … #define PHY_CLK_CTRL … #define PSW_CLK_CTRL … #define CLOCK_GATE_BYPASS … #define RESET_CTRL_EN … #define UFS_SYSCTRL … #define UFS_DEVICE_RESET_CTRL … #define BIT_UFS_PSW_ISO_CTRL … #define BIT_UFS_PSW_MTCMOS_EN … #define BIT_UFS_REFCLK_ISO_EN … #define BIT_UFS_PHY_ISO_CTRL … #define BIT_SYSCTRL_LP_ISOL_EN … #define BIT_SYSCTRL_PWR_READY … #define BIT_SYSCTRL_REF_CLOCK_EN … #define MASK_SYSCTRL_REF_CLOCK_SEL … #define MASK_SYSCTRL_CFG_CLOCK_FREQ … #define UFS_FREQ_CFG_CLK … #define BIT_SYSCTRL_PSW_CLK_EN … #define MASK_UFS_CLK_GATE_BYPASS … #define BIT_SYSCTRL_LP_RESET_N … #define BIT_UFS_REFCLK_SRC_SEl … #define MASK_UFS_SYSCRTL_BYPASS … #define MASK_UFS_DEVICE_RESET … #define BIT_UFS_DEVICE_RESET … /* * M-TX Configuration Attributes for Hixxxx */ #define MPHY_TX_FSM_STATE … #define TX_FSM_HIBERN8 … /* * Hixxxx UFS HC specific Registers */ enum { … }; /* AHIT - Auto-Hibernate Idle Timer */ #define UFS_AHIT_AH8ITV_MASK … /* REG UFS_REG_OCPTHRTL definition */ #define UFS_HCLKDIV_NORMAL_VALUE … /* vendor specific pre-defined parameters */ #define SLOW … #define FAST … #define UFS_HISI_CAP_RESERVED … #define UFS_HISI_CAP_PHY10nm … struct ufs_hisi_host { … }; #define ufs_sys_ctrl_writel(host, val, reg) … #define ufs_sys_ctrl_readl(host, reg) … #define ufs_sys_ctrl_set_bits(host, mask, reg) … #define ufs_sys_ctrl_clr_bits(host, mask, reg) … #endif /* UFS_HISI_H_ */
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