/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* * Copyright 2021 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define __DT_BINDINGS_CLOCK_IMX8ULP_H #define IMX8ULP_CLK_DUMMY … /* CGC1 */ #define IMX8ULP_CLK_SPLL2 … #define IMX8ULP_CLK_SPLL3 … #define IMX8ULP_CLK_A35_SEL … #define IMX8ULP_CLK_A35_DIV … #define IMX8ULP_CLK_SPLL2_PRE_SEL … #define IMX8ULP_CLK_SPLL3_PRE_SEL … #define IMX8ULP_CLK_SPLL3_PFD0 … #define IMX8ULP_CLK_SPLL3_PFD1 … #define IMX8ULP_CLK_SPLL3_PFD2 … #define IMX8ULP_CLK_SPLL3_PFD3 … #define IMX8ULP_CLK_SPLL3_PFD0_DIV1 … #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 … #define IMX8ULP_CLK_SPLL3_PFD1_DIV1 … #define IMX8ULP_CLK_SPLL3_PFD1_DIV2 … #define IMX8ULP_CLK_SPLL3_PFD2_DIV1 … #define IMX8ULP_CLK_SPLL3_PFD2_DIV2 … #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 … #define IMX8ULP_CLK_SPLL3_PFD3_DIV2 … #define IMX8ULP_CLK_NIC_SEL … #define IMX8ULP_CLK_NIC_AD_DIVPLAT … #define IMX8ULP_CLK_NIC_PER_DIVPLAT … #define IMX8ULP_CLK_XBAR_SEL … #define IMX8ULP_CLK_XBAR_AD_DIVPLAT … #define IMX8ULP_CLK_XBAR_DIVBUS … #define IMX8ULP_CLK_XBAR_AD_SLOW … #define IMX8ULP_CLK_SOSC_DIV1 … #define IMX8ULP_CLK_SOSC_DIV2 … #define IMX8ULP_CLK_SOSC_DIV3 … #define IMX8ULP_CLK_FROSC_DIV1 … #define IMX8ULP_CLK_FROSC_DIV2 … #define IMX8ULP_CLK_FROSC_DIV3 … #define IMX8ULP_CLK_SPLL3_VCODIV … #define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE … #define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE … #define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE … #define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE … #define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE … #define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE … #define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE … #define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE … #define IMX8ULP_CLK_SOSC_DIV1_GATE … #define IMX8ULP_CLK_SOSC_DIV2_GATE … #define IMX8ULP_CLK_SOSC_DIV3_GATE … #define IMX8ULP_CLK_FROSC_DIV1_GATE … #define IMX8ULP_CLK_FROSC_DIV2_GATE … #define IMX8ULP_CLK_FROSC_DIV3_GATE … #define IMX8ULP_CLK_SAI4_SEL … #define IMX8ULP_CLK_SAI5_SEL … #define IMX8ULP_CLK_AUD_CLK1 … #define IMX8ULP_CLK_ARM … #define IMX8ULP_CLK_ENET_TS_SEL … #define IMX8ULP_CLK_CGC1_END … /* CGC2 */ #define IMX8ULP_CLK_PLL4_PRE_SEL … #define IMX8ULP_CLK_PLL4 … #define IMX8ULP_CLK_PLL4_VCODIV … #define IMX8ULP_CLK_DDR_SEL … #define IMX8ULP_CLK_DDR_DIV … #define IMX8ULP_CLK_LPAV_AXI_SEL … #define IMX8ULP_CLK_LPAV_AXI_DIV … #define IMX8ULP_CLK_LPAV_AHB_DIV … #define IMX8ULP_CLK_LPAV_BUS_DIV … #define IMX8ULP_CLK_PLL4_PFD0 … #define IMX8ULP_CLK_PLL4_PFD1 … #define IMX8ULP_CLK_PLL4_PFD2 … #define IMX8ULP_CLK_PLL4_PFD3 … #define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE … #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE … #define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE … #define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE … #define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE … #define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE … #define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE … #define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE … #define IMX8ULP_CLK_PLL4_PFD0_DIV1 … #define IMX8ULP_CLK_PLL4_PFD0_DIV2 … #define IMX8ULP_CLK_PLL4_PFD1_DIV1 … #define IMX8ULP_CLK_PLL4_PFD1_DIV2 … #define IMX8ULP_CLK_PLL4_PFD2_DIV1 … #define IMX8ULP_CLK_PLL4_PFD2_DIV2 … #define IMX8ULP_CLK_PLL4_PFD3_DIV1 … #define IMX8ULP_CLK_PLL4_PFD3_DIV2 … #define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE … #define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE … #define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE … #define IMX8ULP_CLK_CGC2_SOSC_DIV1 … #define IMX8ULP_CLK_CGC2_SOSC_DIV2 … #define IMX8ULP_CLK_CGC2_SOSC_DIV3 … #define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE … #define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE … #define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE … #define IMX8ULP_CLK_CGC2_FROSC_DIV1 … #define IMX8ULP_CLK_CGC2_FROSC_DIV2 … #define IMX8ULP_CLK_CGC2_FROSC_DIV3 … #define IMX8ULP_CLK_AUD_CLK2 … #define IMX8ULP_CLK_SAI6_SEL … #define IMX8ULP_CLK_SAI7_SEL … #define IMX8ULP_CLK_SPDIF_SEL … #define IMX8ULP_CLK_HIFI_SEL … #define IMX8ULP_CLK_HIFI_DIVCORE … #define IMX8ULP_CLK_HIFI_DIVPLAT … #define IMX8ULP_CLK_DSI_PHY_REF … #define IMX8ULP_CLK_CGC2_END … /* PCC3 */ #define IMX8ULP_CLK_WDOG3 … #define IMX8ULP_CLK_WDOG4 … #define IMX8ULP_CLK_LPIT1 … #define IMX8ULP_CLK_TPM4 … #define IMX8ULP_CLK_TPM5 … #define IMX8ULP_CLK_FLEXIO1 … #define IMX8ULP_CLK_I3C2 … #define IMX8ULP_CLK_LPI2C4 … #define IMX8ULP_CLK_LPI2C5 … #define IMX8ULP_CLK_LPUART4 … #define IMX8ULP_CLK_LPUART5 … #define IMX8ULP_CLK_LPSPI4 … #define IMX8ULP_CLK_LPSPI5 … #define IMX8ULP_CLK_DMA1_MP … #define IMX8ULP_CLK_DMA1_CH0 … #define IMX8ULP_CLK_DMA1_CH1 … #define IMX8ULP_CLK_DMA1_CH2 … #define IMX8ULP_CLK_DMA1_CH3 … #define IMX8ULP_CLK_DMA1_CH4 … #define IMX8ULP_CLK_DMA1_CH5 … #define IMX8ULP_CLK_DMA1_CH6 … #define IMX8ULP_CLK_DMA1_CH7 … #define IMX8ULP_CLK_DMA1_CH8 … #define IMX8ULP_CLK_DMA1_CH9 … #define IMX8ULP_CLK_DMA1_CH10 … #define IMX8ULP_CLK_DMA1_CH11 … #define IMX8ULP_CLK_DMA1_CH12 … #define IMX8ULP_CLK_DMA1_CH13 … #define IMX8ULP_CLK_DMA1_CH14 … #define IMX8ULP_CLK_DMA1_CH15 … #define IMX8ULP_CLK_DMA1_CH16 … #define IMX8ULP_CLK_DMA1_CH17 … #define IMX8ULP_CLK_DMA1_CH18 … #define IMX8ULP_CLK_DMA1_CH19 … #define IMX8ULP_CLK_DMA1_CH20 … #define IMX8ULP_CLK_DMA1_CH21 … #define IMX8ULP_CLK_DMA1_CH22 … #define IMX8ULP_CLK_DMA1_CH23 … #define IMX8ULP_CLK_DMA1_CH24 … #define IMX8ULP_CLK_DMA1_CH25 … #define IMX8ULP_CLK_DMA1_CH26 … #define IMX8ULP_CLK_DMA1_CH27 … #define IMX8ULP_CLK_DMA1_CH28 … #define IMX8ULP_CLK_DMA1_CH29 … #define IMX8ULP_CLK_DMA1_CH30 … #define IMX8ULP_CLK_DMA1_CH31 … #define IMX8ULP_CLK_MU3_A … #define IMX8ULP_CLK_MU0_B … #define IMX8ULP_CLK_PCC3_END … /* PCC4 */ #define IMX8ULP_CLK_FLEXSPI2 … #define IMX8ULP_CLK_TPM6 … #define IMX8ULP_CLK_TPM7 … #define IMX8ULP_CLK_LPI2C6 … #define IMX8ULP_CLK_LPI2C7 … #define IMX8ULP_CLK_LPUART6 … #define IMX8ULP_CLK_LPUART7 … #define IMX8ULP_CLK_SAI4 … #define IMX8ULP_CLK_SAI5 … #define IMX8ULP_CLK_PCTLE … #define IMX8ULP_CLK_PCTLF … #define IMX8ULP_CLK_USDHC0 … #define IMX8ULP_CLK_USDHC1 … #define IMX8ULP_CLK_USDHC2 … #define IMX8ULP_CLK_USB0 … #define IMX8ULP_CLK_USB0_PHY … #define IMX8ULP_CLK_USB1 … #define IMX8ULP_CLK_USB1_PHY … #define IMX8ULP_CLK_USB_XBAR … #define IMX8ULP_CLK_ENET … #define IMX8ULP_CLK_SFA1 … #define IMX8ULP_CLK_RGPIOE … #define IMX8ULP_CLK_RGPIOF … #define IMX8ULP_CLK_PCC4_END … /* PCC5 */ #define IMX8ULP_CLK_TPM8 … #define IMX8ULP_CLK_SAI6 … #define IMX8ULP_CLK_SAI7 … #define IMX8ULP_CLK_SPDIF … #define IMX8ULP_CLK_ISI … #define IMX8ULP_CLK_CSI_REGS … #define IMX8ULP_CLK_PCTLD … #define IMX8ULP_CLK_CSI … #define IMX8ULP_CLK_DSI … #define IMX8ULP_CLK_WDOG5 … #define IMX8ULP_CLK_EPDC … #define IMX8ULP_CLK_PXP … #define IMX8ULP_CLK_SFA2 … #define IMX8ULP_CLK_GPU2D … #define IMX8ULP_CLK_GPU3D … #define IMX8ULP_CLK_DC_NANO … #define IMX8ULP_CLK_CSI_CLK_UI … #define IMX8ULP_CLK_CSI_CLK_ESC … #define IMX8ULP_CLK_RGPIOD … #define IMX8ULP_CLK_DMA2_MP … #define IMX8ULP_CLK_DMA2_CH0 … #define IMX8ULP_CLK_DMA2_CH1 … #define IMX8ULP_CLK_DMA2_CH2 … #define IMX8ULP_CLK_DMA2_CH3 … #define IMX8ULP_CLK_DMA2_CH4 … #define IMX8ULP_CLK_DMA2_CH5 … #define IMX8ULP_CLK_DMA2_CH6 … #define IMX8ULP_CLK_DMA2_CH7 … #define IMX8ULP_CLK_DMA2_CH8 … #define IMX8ULP_CLK_DMA2_CH9 … #define IMX8ULP_CLK_DMA2_CH10 … #define IMX8ULP_CLK_DMA2_CH11 … #define IMX8ULP_CLK_DMA2_CH12 … #define IMX8ULP_CLK_DMA2_CH13 … #define IMX8ULP_CLK_DMA2_CH14 … #define IMX8ULP_CLK_DMA2_CH15 … #define IMX8ULP_CLK_DMA2_CH16 … #define IMX8ULP_CLK_DMA2_CH17 … #define IMX8ULP_CLK_DMA2_CH18 … #define IMX8ULP_CLK_DMA2_CH19 … #define IMX8ULP_CLK_DMA2_CH20 … #define IMX8ULP_CLK_DMA2_CH21 … #define IMX8ULP_CLK_DMA2_CH22 … #define IMX8ULP_CLK_DMA2_CH23 … #define IMX8ULP_CLK_DMA2_CH24 … #define IMX8ULP_CLK_DMA2_CH25 … #define IMX8ULP_CLK_DMA2_CH26 … #define IMX8ULP_CLK_DMA2_CH27 … #define IMX8ULP_CLK_DMA2_CH28 … #define IMX8ULP_CLK_DMA2_CH29 … #define IMX8ULP_CLK_DMA2_CH30 … #define IMX8ULP_CLK_DMA2_CH31 … #define IMX8ULP_CLK_MU2_B … #define IMX8ULP_CLK_MU3_B … #define IMX8ULP_CLK_AVD_SIM … #define IMX8ULP_CLK_DSI_TX_ESC … #define IMX8ULP_CLK_PCC5_END … #endif
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