/* * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved. * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include <linux/pci.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/vmalloc.h> #include <linux/module.h> #include "qib.h" /* * This file contains PCIe utility routines that are common to the * various QLogic InfiniPath adapters */ /* * Code to adjust PCIe capabilities. * To minimize the change footprint, we call it * from qib_pcie_params, which every chip-specific * file calls, even though this violates some * expectations of harmlessness. */ static void qib_tune_pcie_caps(struct qib_devdata *); static void qib_tune_pcie_coalesce(struct qib_devdata *); /* * Do all the common PCIe setup and initialization. * devdata is not yet allocated, and is not allocated until after this * routine returns success. Therefore qib_dev_err() can't be used for error * printing. */ int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* * Do remaining PCIe setup, once dd is allocated, and save away * fields required to re-initialize after a chip reset, or for * various other purposes */ int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior * to releasing the dd memory. * void because none of the core pcie cleanup returns are void */ void qib_pcie_ddcleanup(struct qib_devdata *dd) { … } /* * We save the msi lo and hi values, so we can restore them after * chip reset (the kernel PCI infrastructure doesn't yet handle that * correctly. */ static void qib_cache_msi_info(struct qib_devdata *dd, int pos) { … } int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent) { … } /** * qib_free_irq - Cleanup INTx and MSI interrupts * @dd: valid pointer to qib dev data * * Since cleanup for INTx and MSI interrupts is trivial, have a common * routine. * */ void qib_free_irq(struct qib_devdata *dd) { … } /* * Setup pcie interrupt stuff again after a reset. I'd like to just call * pci_enable_msi() again for msi, but when I do that, * the MSI enable bit doesn't get set in the command word, and * we switch to a different interrupt vector, which is confusing, * so I instead just do it all inline. Perhaps somehow can tie this * into the PCIe hotplug support at some point */ int qib_reinit_intr(struct qib_devdata *dd) { … } /* * These two routines are helper routines for the device reset code * to move all the pcie code out of the chip-specific driver code. */ void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) { … } void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) { … } static int qib_pcie_coalesce; module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); MODULE_PARM_DESC(…) …; /* * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300 * chipsets. This is known to be unsafe for some revisions of some * of these chipsets, with some BIOS settings, and enabling it on those * systems may result in the system crashing, and/or data corruption. */ static void qib_tune_pcie_coalesce(struct qib_devdata *dd) { … } /* * BIOS may not set PCIe bus-utilization parameters for best performance. * Check and optionally adjust them to maximize our throughput. */ static int qib_pcie_caps; module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); MODULE_PARM_DESC(…) …; static void qib_tune_pcie_caps(struct qib_devdata *dd) { … } /* End of PCIe capability tuning */ /* * From here through qib_pci_err_handler definition is invoked via * PCI error infrastructure, registered via pci */ static pci_ers_result_t qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { … } static pci_ers_result_t qib_pci_mmio_enabled(struct pci_dev *pdev) { … } static pci_ers_result_t qib_pci_slot_reset(struct pci_dev *pdev) { … } static void qib_pci_resume(struct pci_dev *pdev) { … } const struct pci_error_handlers qib_pci_err_handler = …;
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