/* * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. * * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * */ /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ #define QIB_7220_Revision_OFFS … #define QIB_7220_Revision_R_Simulator_LSB … #define QIB_7220_Revision_R_Simulator_RMASK … #define QIB_7220_Revision_R_Emulation_LSB … #define QIB_7220_Revision_R_Emulation_RMASK … #define QIB_7220_Revision_R_Emulation_Revcode_LSB … #define QIB_7220_Revision_R_Emulation_Revcode_RMASK … #define QIB_7220_Revision_BoardID_LSB … #define QIB_7220_Revision_BoardID_RMASK … #define QIB_7220_Revision_R_SW_LSB … #define QIB_7220_Revision_R_SW_RMASK … #define QIB_7220_Revision_R_Arch_LSB … #define QIB_7220_Revision_R_Arch_RMASK … #define QIB_7220_Revision_R_ChipRevMajor_LSB … #define QIB_7220_Revision_R_ChipRevMajor_RMASK … #define QIB_7220_Revision_R_ChipRevMinor_LSB … #define QIB_7220_Revision_R_ChipRevMinor_RMASK … #define QIB_7220_Control_OFFS … #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_LSB … #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK … #define QIB_7220_Control_PCIECplQDiagEn_LSB … #define QIB_7220_Control_PCIECplQDiagEn_RMASK … #define QIB_7220_Control_Reserved_LSB … #define QIB_7220_Control_Reserved_RMASK … #define QIB_7220_Control_TxLatency_LSB … #define QIB_7220_Control_TxLatency_RMASK … #define QIB_7220_Control_PCIERetryBufDiagEn_LSB … #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK … #define QIB_7220_Control_LinkEn_LSB … #define QIB_7220_Control_LinkEn_RMASK … #define QIB_7220_Control_FreezeMode_LSB … #define QIB_7220_Control_FreezeMode_RMASK … #define QIB_7220_Control_SyncReset_LSB … #define QIB_7220_Control_SyncReset_RMASK … #define QIB_7220_PageAlign_OFFS … #define QIB_7220_PortCnt_OFFS … #define QIB_7220_SendRegBase_OFFS … #define QIB_7220_UserRegBase_OFFS … #define QIB_7220_CntrRegBase_OFFS … #define QIB_7220_Scratch_OFFS … #define QIB_7220_IntMask_OFFS … #define QIB_7220_IntMask_SDmaIntMask_LSB … #define QIB_7220_IntMask_SDmaIntMask_RMASK … #define QIB_7220_IntMask_SDmaDisabledMasked_LSB … #define QIB_7220_IntMask_SDmaDisabledMasked_RMASK … #define QIB_7220_IntMask_Reserved_LSB … #define QIB_7220_IntMask_Reserved_RMASK … #define QIB_7220_IntMask_RcvUrg16IntMask_LSB … #define QIB_7220_IntMask_RcvUrg16IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg15IntMask_LSB … #define QIB_7220_IntMask_RcvUrg15IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg14IntMask_LSB … #define QIB_7220_IntMask_RcvUrg14IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg13IntMask_LSB … #define QIB_7220_IntMask_RcvUrg13IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg12IntMask_LSB … #define QIB_7220_IntMask_RcvUrg12IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg11IntMask_LSB … #define QIB_7220_IntMask_RcvUrg11IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg10IntMask_LSB … #define QIB_7220_IntMask_RcvUrg10IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg9IntMask_LSB … #define QIB_7220_IntMask_RcvUrg9IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg8IntMask_LSB … #define QIB_7220_IntMask_RcvUrg8IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg7IntMask_LSB … #define QIB_7220_IntMask_RcvUrg7IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg6IntMask_LSB … #define QIB_7220_IntMask_RcvUrg6IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg5IntMask_LSB … #define QIB_7220_IntMask_RcvUrg5IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg4IntMask_LSB … #define QIB_7220_IntMask_RcvUrg4IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg3IntMask_LSB … #define QIB_7220_IntMask_RcvUrg3IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg2IntMask_LSB … #define QIB_7220_IntMask_RcvUrg2IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg1IntMask_LSB … #define QIB_7220_IntMask_RcvUrg1IntMask_RMASK … #define QIB_7220_IntMask_RcvUrg0IntMask_LSB … #define QIB_7220_IntMask_RcvUrg0IntMask_RMASK … #define QIB_7220_IntMask_ErrorIntMask_LSB … #define QIB_7220_IntMask_ErrorIntMask_RMASK … #define QIB_7220_IntMask_PioSetIntMask_LSB … #define QIB_7220_IntMask_PioSetIntMask_RMASK … #define QIB_7220_IntMask_PioBufAvailIntMask_LSB … #define QIB_7220_IntMask_PioBufAvailIntMask_RMASK … #define QIB_7220_IntMask_assertGPIOIntMask_LSB … #define QIB_7220_IntMask_assertGPIOIntMask_RMASK … #define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_LSB … #define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_RMASK … #define QIB_7220_IntMask_JIntMask_LSB … #define QIB_7220_IntMask_JIntMask_RMASK … #define QIB_7220_IntMask_Reserved1_LSB … #define QIB_7220_IntMask_Reserved1_RMASK … #define QIB_7220_IntMask_RcvAvail16IntMask_LSB … #define QIB_7220_IntMask_RcvAvail16IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail15IntMask_LSB … #define QIB_7220_IntMask_RcvAvail15IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail14IntMask_LSB … #define QIB_7220_IntMask_RcvAvail14IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail13IntMask_LSB … #define QIB_7220_IntMask_RcvAvail13IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail12IntMask_LSB … #define QIB_7220_IntMask_RcvAvail12IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail11IntMask_LSB … #define QIB_7220_IntMask_RcvAvail11IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail10IntMask_LSB … #define QIB_7220_IntMask_RcvAvail10IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail9IntMask_LSB … #define QIB_7220_IntMask_RcvAvail9IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail8IntMask_LSB … #define QIB_7220_IntMask_RcvAvail8IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail7IntMask_LSB … #define QIB_7220_IntMask_RcvAvail7IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail6IntMask_LSB … #define QIB_7220_IntMask_RcvAvail6IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail5IntMask_LSB … #define QIB_7220_IntMask_RcvAvail5IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail4IntMask_LSB … #define QIB_7220_IntMask_RcvAvail4IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail3IntMask_LSB … #define QIB_7220_IntMask_RcvAvail3IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail2IntMask_LSB … #define QIB_7220_IntMask_RcvAvail2IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail1IntMask_LSB … #define QIB_7220_IntMask_RcvAvail1IntMask_RMASK … #define QIB_7220_IntMask_RcvAvail0IntMask_LSB … #define QIB_7220_IntMask_RcvAvail0IntMask_RMASK … #define QIB_7220_IntStatus_OFFS … #define QIB_7220_IntStatus_SDmaInt_LSB … #define QIB_7220_IntStatus_SDmaInt_RMASK … #define QIB_7220_IntStatus_SDmaDisabled_LSB … #define QIB_7220_IntStatus_SDmaDisabled_RMASK … #define QIB_7220_IntStatus_Reserved_LSB … #define QIB_7220_IntStatus_Reserved_RMASK … #define QIB_7220_IntStatus_RcvUrg16_LSB … #define QIB_7220_IntStatus_RcvUrg16_RMASK … #define QIB_7220_IntStatus_RcvUrg15_LSB … #define QIB_7220_IntStatus_RcvUrg15_RMASK … #define QIB_7220_IntStatus_RcvUrg14_LSB … #define QIB_7220_IntStatus_RcvUrg14_RMASK … #define QIB_7220_IntStatus_RcvUrg13_LSB … #define QIB_7220_IntStatus_RcvUrg13_RMASK … #define QIB_7220_IntStatus_RcvUrg12_LSB … #define QIB_7220_IntStatus_RcvUrg12_RMASK … #define QIB_7220_IntStatus_RcvUrg11_LSB … #define QIB_7220_IntStatus_RcvUrg11_RMASK … #define QIB_7220_IntStatus_RcvUrg10_LSB … #define QIB_7220_IntStatus_RcvUrg10_RMASK … #define QIB_7220_IntStatus_RcvUrg9_LSB … #define QIB_7220_IntStatus_RcvUrg9_RMASK … #define QIB_7220_IntStatus_RcvUrg8_LSB … #define QIB_7220_IntStatus_RcvUrg8_RMASK … #define QIB_7220_IntStatus_RcvUrg7_LSB … #define QIB_7220_IntStatus_RcvUrg7_RMASK … #define QIB_7220_IntStatus_RcvUrg6_LSB … #define QIB_7220_IntStatus_RcvUrg6_RMASK … #define QIB_7220_IntStatus_RcvUrg5_LSB … #define QIB_7220_IntStatus_RcvUrg5_RMASK … #define QIB_7220_IntStatus_RcvUrg4_LSB … #define QIB_7220_IntStatus_RcvUrg4_RMASK … #define QIB_7220_IntStatus_RcvUrg3_LSB … #define QIB_7220_IntStatus_RcvUrg3_RMASK … #define QIB_7220_IntStatus_RcvUrg2_LSB … #define QIB_7220_IntStatus_RcvUrg2_RMASK … #define QIB_7220_IntStatus_RcvUrg1_LSB … #define QIB_7220_IntStatus_RcvUrg1_RMASK … #define QIB_7220_IntStatus_RcvUrg0_LSB … #define QIB_7220_IntStatus_RcvUrg0_RMASK … #define QIB_7220_IntStatus_Error_LSB … #define QIB_7220_IntStatus_Error_RMASK … #define QIB_7220_IntStatus_PioSent_LSB … #define QIB_7220_IntStatus_PioSent_RMASK … #define QIB_7220_IntStatus_PioBufAvail_LSB … #define QIB_7220_IntStatus_PioBufAvail_RMASK … #define QIB_7220_IntStatus_assertGPIO_LSB … #define QIB_7220_IntStatus_assertGPIO_RMASK … #define QIB_7220_IntStatus_IBSerdesTrimDone_LSB … #define QIB_7220_IntStatus_IBSerdesTrimDone_RMASK … #define QIB_7220_IntStatus_JInt_LSB … #define QIB_7220_IntStatus_JInt_RMASK … #define QIB_7220_IntStatus_Reserved1_LSB … #define QIB_7220_IntStatus_Reserved1_RMASK … #define QIB_7220_IntStatus_RcvAvail16_LSB … #define QIB_7220_IntStatus_RcvAvail16_RMASK … #define QIB_7220_IntStatus_RcvAvail15_LSB … #define QIB_7220_IntStatus_RcvAvail15_RMASK … #define QIB_7220_IntStatus_RcvAvail14_LSB … #define QIB_7220_IntStatus_RcvAvail14_RMASK … #define QIB_7220_IntStatus_RcvAvail13_LSB … #define QIB_7220_IntStatus_RcvAvail13_RMASK … #define QIB_7220_IntStatus_RcvAvail12_LSB … #define QIB_7220_IntStatus_RcvAvail12_RMASK … #define QIB_7220_IntStatus_RcvAvail11_LSB … #define QIB_7220_IntStatus_RcvAvail11_RMASK … #define QIB_7220_IntStatus_RcvAvail10_LSB … #define QIB_7220_IntStatus_RcvAvail10_RMASK … #define QIB_7220_IntStatus_RcvAvail9_LSB … #define QIB_7220_IntStatus_RcvAvail9_RMASK … #define QIB_7220_IntStatus_RcvAvail8_LSB … #define QIB_7220_IntStatus_RcvAvail8_RMASK … #define QIB_7220_IntStatus_RcvAvail7_LSB … #define QIB_7220_IntStatus_RcvAvail7_RMASK … #define QIB_7220_IntStatus_RcvAvail6_LSB … #define QIB_7220_IntStatus_RcvAvail6_RMASK … #define QIB_7220_IntStatus_RcvAvail5_LSB … #define QIB_7220_IntStatus_RcvAvail5_RMASK … #define QIB_7220_IntStatus_RcvAvail4_LSB … #define QIB_7220_IntStatus_RcvAvail4_RMASK … #define QIB_7220_IntStatus_RcvAvail3_LSB … #define QIB_7220_IntStatus_RcvAvail3_RMASK … #define QIB_7220_IntStatus_RcvAvail2_LSB … #define QIB_7220_IntStatus_RcvAvail2_RMASK … #define QIB_7220_IntStatus_RcvAvail1_LSB … #define QIB_7220_IntStatus_RcvAvail1_RMASK … #define QIB_7220_IntStatus_RcvAvail0_LSB … #define QIB_7220_IntStatus_RcvAvail0_RMASK … #define QIB_7220_IntClear_OFFS … #define QIB_7220_IntClear_SDmaIntClear_LSB … #define QIB_7220_IntClear_SDmaIntClear_RMASK … #define QIB_7220_IntClear_SDmaDisabledClear_LSB … #define QIB_7220_IntClear_SDmaDisabledClear_RMASK … #define QIB_7220_IntClear_Reserved_LSB … #define QIB_7220_IntClear_Reserved_RMASK … #define QIB_7220_IntClear_RcvUrg16IntClear_LSB … #define QIB_7220_IntClear_RcvUrg16IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg15IntClear_LSB … #define QIB_7220_IntClear_RcvUrg15IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg14IntClear_LSB … #define QIB_7220_IntClear_RcvUrg14IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg13IntClear_LSB … #define QIB_7220_IntClear_RcvUrg13IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg12IntClear_LSB … #define QIB_7220_IntClear_RcvUrg12IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg11IntClear_LSB … #define QIB_7220_IntClear_RcvUrg11IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg10IntClear_LSB … #define QIB_7220_IntClear_RcvUrg10IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg9IntClear_LSB … #define QIB_7220_IntClear_RcvUrg9IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg8IntClear_LSB … #define QIB_7220_IntClear_RcvUrg8IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg7IntClear_LSB … #define QIB_7220_IntClear_RcvUrg7IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg6IntClear_LSB … #define QIB_7220_IntClear_RcvUrg6IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg5IntClear_LSB … #define QIB_7220_IntClear_RcvUrg5IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg4IntClear_LSB … #define QIB_7220_IntClear_RcvUrg4IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg3IntClear_LSB … #define QIB_7220_IntClear_RcvUrg3IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg2IntClear_LSB … #define QIB_7220_IntClear_RcvUrg2IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg1IntClear_LSB … #define QIB_7220_IntClear_RcvUrg1IntClear_RMASK … #define QIB_7220_IntClear_RcvUrg0IntClear_LSB … #define QIB_7220_IntClear_RcvUrg0IntClear_RMASK … #define QIB_7220_IntClear_ErrorIntClear_LSB … #define QIB_7220_IntClear_ErrorIntClear_RMASK … #define QIB_7220_IntClear_PioSetIntClear_LSB … #define QIB_7220_IntClear_PioSetIntClear_RMASK … #define QIB_7220_IntClear_PioBufAvailIntClear_LSB … #define QIB_7220_IntClear_PioBufAvailIntClear_RMASK … #define QIB_7220_IntClear_assertGPIOIntClear_LSB … #define QIB_7220_IntClear_assertGPIOIntClear_RMASK … #define QIB_7220_IntClear_IBSerdesTrimDoneClear_LSB … #define QIB_7220_IntClear_IBSerdesTrimDoneClear_RMASK … #define QIB_7220_IntClear_JIntClear_LSB … #define QIB_7220_IntClear_JIntClear_RMASK … #define QIB_7220_IntClear_Reserved1_LSB … #define QIB_7220_IntClear_Reserved1_RMASK … #define QIB_7220_IntClear_RcvAvail16IntClear_LSB … #define QIB_7220_IntClear_RcvAvail16IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail15IntClear_LSB … #define QIB_7220_IntClear_RcvAvail15IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail14IntClear_LSB … #define QIB_7220_IntClear_RcvAvail14IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail13IntClear_LSB … #define QIB_7220_IntClear_RcvAvail13IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail12IntClear_LSB … #define QIB_7220_IntClear_RcvAvail12IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail11IntClear_LSB … #define QIB_7220_IntClear_RcvAvail11IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail10IntClear_LSB … #define QIB_7220_IntClear_RcvAvail10IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail9IntClear_LSB … #define QIB_7220_IntClear_RcvAvail9IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail8IntClear_LSB … #define QIB_7220_IntClear_RcvAvail8IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail7IntClear_LSB … #define QIB_7220_IntClear_RcvAvail7IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail6IntClear_LSB … #define QIB_7220_IntClear_RcvAvail6IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail5IntClear_LSB … #define QIB_7220_IntClear_RcvAvail5IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail4IntClear_LSB … #define QIB_7220_IntClear_RcvAvail4IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail3IntClear_LSB … #define QIB_7220_IntClear_RcvAvail3IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail2IntClear_LSB … #define QIB_7220_IntClear_RcvAvail2IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail1IntClear_LSB … #define QIB_7220_IntClear_RcvAvail1IntClear_RMASK … #define QIB_7220_IntClear_RcvAvail0IntClear_LSB … #define QIB_7220_IntClear_RcvAvail0IntClear_RMASK … #define QIB_7220_ErrMask_OFFS … #define QIB_7220_ErrMask_Reserved_LSB … #define QIB_7220_ErrMask_Reserved_RMASK … #define QIB_7220_ErrMask_InvalidEEPCmdMask_LSB … #define QIB_7220_ErrMask_InvalidEEPCmdMask_RMASK … #define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_LSB … #define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_RMASK … #define QIB_7220_ErrMask_HardwareErrMask_LSB … #define QIB_7220_ErrMask_HardwareErrMask_RMASK … #define QIB_7220_ErrMask_ResetNegatedMask_LSB … #define QIB_7220_ErrMask_ResetNegatedMask_RMASK … #define QIB_7220_ErrMask_InvalidAddrErrMask_LSB … #define QIB_7220_ErrMask_InvalidAddrErrMask_RMASK … #define QIB_7220_ErrMask_IBStatusChangedMask_LSB … #define QIB_7220_ErrMask_IBStatusChangedMask_RMASK … #define QIB_7220_ErrMask_SDmaUnexpDataErrMask_LSB … #define QIB_7220_ErrMask_SDmaUnexpDataErrMask_RMASK … #define QIB_7220_ErrMask_SDmaMissingDwErrMask_LSB … #define QIB_7220_ErrMask_SDmaMissingDwErrMask_RMASK … #define QIB_7220_ErrMask_SDmaDwEnErrMask_LSB … #define QIB_7220_ErrMask_SDmaDwEnErrMask_RMASK … #define QIB_7220_ErrMask_SDmaRpyTagErrMask_LSB … #define QIB_7220_ErrMask_SDmaRpyTagErrMask_RMASK … #define QIB_7220_ErrMask_SDma1stDescErrMask_LSB … #define QIB_7220_ErrMask_SDma1stDescErrMask_RMASK … #define QIB_7220_ErrMask_SDmaBaseErrMask_LSB … #define QIB_7220_ErrMask_SDmaBaseErrMask_RMASK … #define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_LSB … #define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_RMASK … #define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_LSB … #define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_RMASK … #define QIB_7220_ErrMask_SDmaGenMismatchErrMask_LSB … #define QIB_7220_ErrMask_SDmaGenMismatchErrMask_RMASK … #define QIB_7220_ErrMask_SendBufMisuseErrMask_LSB … #define QIB_7220_ErrMask_SendBufMisuseErrMask_RMASK … #define QIB_7220_ErrMask_SendUnsupportedVLErrMask_LSB … #define QIB_7220_ErrMask_SendUnsupportedVLErrMask_RMASK … #define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_LSB … #define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_RMASK … #define QIB_7220_ErrMask_SendPioArmLaunchErrMask_LSB … #define QIB_7220_ErrMask_SendPioArmLaunchErrMask_RMASK … #define QIB_7220_ErrMask_SendDroppedDataPktErrMask_LSB … #define QIB_7220_ErrMask_SendDroppedDataPktErrMask_RMASK … #define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_LSB … #define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_RMASK … #define QIB_7220_ErrMask_SendPktLenErrMask_LSB … #define QIB_7220_ErrMask_SendPktLenErrMask_RMASK … #define QIB_7220_ErrMask_SendUnderRunErrMask_LSB … #define QIB_7220_ErrMask_SendUnderRunErrMask_RMASK … #define QIB_7220_ErrMask_SendMaxPktLenErrMask_LSB … #define QIB_7220_ErrMask_SendMaxPktLenErrMask_RMASK … #define QIB_7220_ErrMask_SendMinPktLenErrMask_LSB … #define QIB_7220_ErrMask_SendMinPktLenErrMask_RMASK … #define QIB_7220_ErrMask_SDmaDisabledErrMask_LSB … #define QIB_7220_ErrMask_SDmaDisabledErrMask_RMASK … #define QIB_7220_ErrMask_SendSpecialTriggerErrMask_LSB … #define QIB_7220_ErrMask_SendSpecialTriggerErrMask_RMASK … #define QIB_7220_ErrMask_Reserved1_LSB … #define QIB_7220_ErrMask_Reserved1_RMASK … #define QIB_7220_ErrMask_RcvIBLostLinkErrMask_LSB … #define QIB_7220_ErrMask_RcvIBLostLinkErrMask_RMASK … #define QIB_7220_ErrMask_RcvHdrErrMask_LSB … #define QIB_7220_ErrMask_RcvHdrErrMask_RMASK … #define QIB_7220_ErrMask_RcvHdrLenErrMask_LSB … #define QIB_7220_ErrMask_RcvHdrLenErrMask_RMASK … #define QIB_7220_ErrMask_RcvBadTidErrMask_LSB … #define QIB_7220_ErrMask_RcvBadTidErrMask_RMASK … #define QIB_7220_ErrMask_RcvHdrFullErrMask_LSB … #define QIB_7220_ErrMask_RcvHdrFullErrMask_RMASK … #define QIB_7220_ErrMask_RcvEgrFullErrMask_LSB … #define QIB_7220_ErrMask_RcvEgrFullErrMask_RMASK … #define QIB_7220_ErrMask_RcvBadVersionErrMask_LSB … #define QIB_7220_ErrMask_RcvBadVersionErrMask_RMASK … #define QIB_7220_ErrMask_RcvIBFlowErrMask_LSB … #define QIB_7220_ErrMask_RcvIBFlowErrMask_RMASK … #define QIB_7220_ErrMask_RcvEBPErrMask_LSB … #define QIB_7220_ErrMask_RcvEBPErrMask_RMASK … #define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_LSB … #define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_RMASK … #define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_LSB … #define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_RMASK … #define QIB_7220_ErrMask_RcvShortPktLenErrMask_LSB … #define QIB_7220_ErrMask_RcvShortPktLenErrMask_RMASK … #define QIB_7220_ErrMask_RcvLongPktLenErrMask_LSB … #define QIB_7220_ErrMask_RcvLongPktLenErrMask_RMASK … #define QIB_7220_ErrMask_RcvMaxPktLenErrMask_LSB … #define QIB_7220_ErrMask_RcvMaxPktLenErrMask_RMASK … #define QIB_7220_ErrMask_RcvMinPktLenErrMask_LSB … #define QIB_7220_ErrMask_RcvMinPktLenErrMask_RMASK … #define QIB_7220_ErrMask_RcvICRCErrMask_LSB … #define QIB_7220_ErrMask_RcvICRCErrMask_RMASK … #define QIB_7220_ErrMask_RcvVCRCErrMask_LSB … #define QIB_7220_ErrMask_RcvVCRCErrMask_RMASK … #define QIB_7220_ErrMask_RcvFormatErrMask_LSB … #define QIB_7220_ErrMask_RcvFormatErrMask_RMASK … #define QIB_7220_ErrStatus_OFFS … #define QIB_7220_ErrStatus_Reserved_LSB … #define QIB_7220_ErrStatus_Reserved_RMASK … #define QIB_7220_ErrStatus_InvalidEEPCmdErr_LSB … #define QIB_7220_ErrStatus_InvalidEEPCmdErr_RMASK … #define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_LSB … #define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_RMASK … #define QIB_7220_ErrStatus_HardwareErr_LSB … #define QIB_7220_ErrStatus_HardwareErr_RMASK … #define QIB_7220_ErrStatus_ResetNegated_LSB … #define QIB_7220_ErrStatus_ResetNegated_RMASK … #define QIB_7220_ErrStatus_InvalidAddrErr_LSB … #define QIB_7220_ErrStatus_InvalidAddrErr_RMASK … #define QIB_7220_ErrStatus_IBStatusChanged_LSB … #define QIB_7220_ErrStatus_IBStatusChanged_RMASK … #define QIB_7220_ErrStatus_SDmaUnexpDataErr_LSB … #define QIB_7220_ErrStatus_SDmaUnexpDataErr_RMASK … #define QIB_7220_ErrStatus_SDmaMissingDwErr_LSB … #define QIB_7220_ErrStatus_SDmaMissingDwErr_RMASK … #define QIB_7220_ErrStatus_SDmaDwEnErr_LSB … #define QIB_7220_ErrStatus_SDmaDwEnErr_RMASK … #define QIB_7220_ErrStatus_SDmaRpyTagErr_LSB … #define QIB_7220_ErrStatus_SDmaRpyTagErr_RMASK … #define QIB_7220_ErrStatus_SDma1stDescErr_LSB … #define QIB_7220_ErrStatus_SDma1stDescErr_RMASK … #define QIB_7220_ErrStatus_SDmaBaseErr_LSB … #define QIB_7220_ErrStatus_SDmaBaseErr_RMASK … #define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_LSB … #define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_RMASK … #define QIB_7220_ErrStatus_SDmaOutOfBoundErr_LSB … #define QIB_7220_ErrStatus_SDmaOutOfBoundErr_RMASK … #define QIB_7220_ErrStatus_SDmaGenMismatchErr_LSB … #define QIB_7220_ErrStatus_SDmaGenMismatchErr_RMASK … #define QIB_7220_ErrStatus_SendBufMisuseErr_LSB … #define QIB_7220_ErrStatus_SendBufMisuseErr_RMASK … #define QIB_7220_ErrStatus_SendUnsupportedVLErr_LSB … #define QIB_7220_ErrStatus_SendUnsupportedVLErr_RMASK … #define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_LSB … #define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_RMASK … #define QIB_7220_ErrStatus_SendPioArmLaunchErr_LSB … #define QIB_7220_ErrStatus_SendPioArmLaunchErr_RMASK … #define QIB_7220_ErrStatus_SendDroppedDataPktErr_LSB … #define QIB_7220_ErrStatus_SendDroppedDataPktErr_RMASK … #define QIB_7220_ErrStatus_SendDroppedSmpPktErr_LSB … #define QIB_7220_ErrStatus_SendDroppedSmpPktErr_RMASK … #define QIB_7220_ErrStatus_SendPktLenErr_LSB … #define QIB_7220_ErrStatus_SendPktLenErr_RMASK … #define QIB_7220_ErrStatus_SendUnderRunErr_LSB … #define QIB_7220_ErrStatus_SendUnderRunErr_RMASK … #define QIB_7220_ErrStatus_SendMaxPktLenErr_LSB … #define QIB_7220_ErrStatus_SendMaxPktLenErr_RMASK … #define QIB_7220_ErrStatus_SendMinPktLenErr_LSB … #define QIB_7220_ErrStatus_SendMinPktLenErr_RMASK … #define QIB_7220_ErrStatus_SDmaDisabledErr_LSB … #define QIB_7220_ErrStatus_SDmaDisabledErr_RMASK … #define QIB_7220_ErrStatus_SendSpecialTriggerErr_LSB … #define QIB_7220_ErrStatus_SendSpecialTriggerErr_RMASK … #define QIB_7220_ErrStatus_Reserved1_LSB … #define QIB_7220_ErrStatus_Reserved1_RMASK … #define QIB_7220_ErrStatus_RcvIBLostLinkErr_LSB … #define QIB_7220_ErrStatus_RcvIBLostLinkErr_RMASK … #define QIB_7220_ErrStatus_RcvHdrErr_LSB … #define QIB_7220_ErrStatus_RcvHdrErr_RMASK … #define QIB_7220_ErrStatus_RcvHdrLenErr_LSB … #define QIB_7220_ErrStatus_RcvHdrLenErr_RMASK … #define QIB_7220_ErrStatus_RcvBadTidErr_LSB … #define QIB_7220_ErrStatus_RcvBadTidErr_RMASK … #define QIB_7220_ErrStatus_RcvHdrFullErr_LSB … #define QIB_7220_ErrStatus_RcvHdrFullErr_RMASK … #define QIB_7220_ErrStatus_RcvEgrFullErr_LSB … #define QIB_7220_ErrStatus_RcvEgrFullErr_RMASK … #define QIB_7220_ErrStatus_RcvBadVersionErr_LSB … #define QIB_7220_ErrStatus_RcvBadVersionErr_RMASK … #define QIB_7220_ErrStatus_RcvIBFlowErr_LSB … #define QIB_7220_ErrStatus_RcvIBFlowErr_RMASK … #define QIB_7220_ErrStatus_RcvEBPErr_LSB … #define QIB_7220_ErrStatus_RcvEBPErr_RMASK … #define QIB_7220_ErrStatus_RcvUnsupportedVLErr_LSB … #define QIB_7220_ErrStatus_RcvUnsupportedVLErr_RMASK … #define QIB_7220_ErrStatus_RcvUnexpectedCharErr_LSB … #define QIB_7220_ErrStatus_RcvUnexpectedCharErr_RMASK … #define QIB_7220_ErrStatus_RcvShortPktLenErr_LSB … #define QIB_7220_ErrStatus_RcvShortPktLenErr_RMASK … #define QIB_7220_ErrStatus_RcvLongPktLenErr_LSB … #define QIB_7220_ErrStatus_RcvLongPktLenErr_RMASK … #define QIB_7220_ErrStatus_RcvMaxPktLenErr_LSB … #define QIB_7220_ErrStatus_RcvMaxPktLenErr_RMASK … #define QIB_7220_ErrStatus_RcvMinPktLenErr_LSB … #define QIB_7220_ErrStatus_RcvMinPktLenErr_RMASK … #define QIB_7220_ErrStatus_RcvICRCErr_LSB … #define QIB_7220_ErrStatus_RcvICRCErr_RMASK … #define QIB_7220_ErrStatus_RcvVCRCErr_LSB … #define QIB_7220_ErrStatus_RcvVCRCErr_RMASK … #define QIB_7220_ErrStatus_RcvFormatErr_LSB … #define QIB_7220_ErrStatus_RcvFormatErr_RMASK … #define QIB_7220_ErrClear_OFFS … #define QIB_7220_ErrClear_Reserved_LSB … #define QIB_7220_ErrClear_Reserved_RMASK … #define QIB_7220_ErrClear_InvalidEEPCmdErrClear_LSB … #define QIB_7220_ErrClear_InvalidEEPCmdErrClear_RMASK … #define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_LSB … #define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_RMASK … #define QIB_7220_ErrClear_HardwareErrClear_LSB … #define QIB_7220_ErrClear_HardwareErrClear_RMASK … #define QIB_7220_ErrClear_ResetNegatedClear_LSB … #define QIB_7220_ErrClear_ResetNegatedClear_RMASK … #define QIB_7220_ErrClear_InvalidAddrErrClear_LSB … #define QIB_7220_ErrClear_InvalidAddrErrClear_RMASK … #define QIB_7220_ErrClear_IBStatusChangedClear_LSB … #define QIB_7220_ErrClear_IBStatusChangedClear_RMASK … #define QIB_7220_ErrClear_SDmaUnexpDataErrClear_LSB … #define QIB_7220_ErrClear_SDmaUnexpDataErrClear_RMASK … #define QIB_7220_ErrClear_SDmaMissingDwErrClear_LSB … #define QIB_7220_ErrClear_SDmaMissingDwErrClear_RMASK … #define QIB_7220_ErrClear_SDmaDwEnErrClear_LSB … #define QIB_7220_ErrClear_SDmaDwEnErrClear_RMASK … #define QIB_7220_ErrClear_SDmaRpyTagErrClear_LSB … #define QIB_7220_ErrClear_SDmaRpyTagErrClear_RMASK … #define QIB_7220_ErrClear_SDma1stDescErrClear_LSB … #define QIB_7220_ErrClear_SDma1stDescErrClear_RMASK … #define QIB_7220_ErrClear_SDmaBaseErrClear_LSB … #define QIB_7220_ErrClear_SDmaBaseErrClear_RMASK … #define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_LSB … #define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_RMASK … #define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_LSB … #define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_RMASK … #define QIB_7220_ErrClear_SDmaGenMismatchErrClear_LSB … #define QIB_7220_ErrClear_SDmaGenMismatchErrClear_RMASK … #define QIB_7220_ErrClear_SendBufMisuseErrClear_LSB … #define QIB_7220_ErrClear_SendBufMisuseErrClear_RMASK … #define QIB_7220_ErrClear_SendUnsupportedVLErrClear_LSB … #define QIB_7220_ErrClear_SendUnsupportedVLErrClear_RMASK … #define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_LSB … #define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_RMASK … #define QIB_7220_ErrClear_SendPioArmLaunchErrClear_LSB … #define QIB_7220_ErrClear_SendPioArmLaunchErrClear_RMASK … #define QIB_7220_ErrClear_SendDroppedDataPktErrClear_LSB … #define QIB_7220_ErrClear_SendDroppedDataPktErrClear_RMASK … #define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_LSB … #define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_RMASK … #define QIB_7220_ErrClear_SendPktLenErrClear_LSB … #define QIB_7220_ErrClear_SendPktLenErrClear_RMASK … #define QIB_7220_ErrClear_SendUnderRunErrClear_LSB … #define QIB_7220_ErrClear_SendUnderRunErrClear_RMASK … #define QIB_7220_ErrClear_SendMaxPktLenErrClear_LSB … #define QIB_7220_ErrClear_SendMaxPktLenErrClear_RMASK … #define QIB_7220_ErrClear_SendMinPktLenErrClear_LSB … #define QIB_7220_ErrClear_SendMinPktLenErrClear_RMASK … #define QIB_7220_ErrClear_SDmaDisabledErrClear_LSB … #define QIB_7220_ErrClear_SDmaDisabledErrClear_RMASK … #define QIB_7220_ErrClear_SendSpecialTriggerErrClear_LSB … #define QIB_7220_ErrClear_SendSpecialTriggerErrClear_RMASK … #define QIB_7220_ErrClear_Reserved1_LSB … #define QIB_7220_ErrClear_Reserved1_RMASK … #define QIB_7220_ErrClear_RcvIBLostLinkErrClear_LSB … #define QIB_7220_ErrClear_RcvIBLostLinkErrClear_RMASK … #define QIB_7220_ErrClear_RcvHdrErrClear_LSB … #define QIB_7220_ErrClear_RcvHdrErrClear_RMASK … #define QIB_7220_ErrClear_RcvHdrLenErrClear_LSB … #define QIB_7220_ErrClear_RcvHdrLenErrClear_RMASK … #define QIB_7220_ErrClear_RcvBadTidErrClear_LSB … #define QIB_7220_ErrClear_RcvBadTidErrClear_RMASK … #define QIB_7220_ErrClear_RcvHdrFullErrClear_LSB … #define QIB_7220_ErrClear_RcvHdrFullErrClear_RMASK … #define QIB_7220_ErrClear_RcvEgrFullErrClear_LSB … #define QIB_7220_ErrClear_RcvEgrFullErrClear_RMASK … #define QIB_7220_ErrClear_RcvBadVersionErrClear_LSB … #define QIB_7220_ErrClear_RcvBadVersionErrClear_RMASK … #define QIB_7220_ErrClear_RcvIBFlowErrClear_LSB … #define QIB_7220_ErrClear_RcvIBFlowErrClear_RMASK … #define QIB_7220_ErrClear_RcvEBPErrClear_LSB … #define QIB_7220_ErrClear_RcvEBPErrClear_RMASK … #define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_LSB … #define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_RMASK … #define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_LSB … #define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_RMASK … #define QIB_7220_ErrClear_RcvShortPktLenErrClear_LSB … #define QIB_7220_ErrClear_RcvShortPktLenErrClear_RMASK … #define QIB_7220_ErrClear_RcvLongPktLenErrClear_LSB … #define QIB_7220_ErrClear_RcvLongPktLenErrClear_RMASK … #define QIB_7220_ErrClear_RcvMaxPktLenErrClear_LSB … #define QIB_7220_ErrClear_RcvMaxPktLenErrClear_RMASK … #define QIB_7220_ErrClear_RcvMinPktLenErrClear_LSB … #define QIB_7220_ErrClear_RcvMinPktLenErrClear_RMASK … #define QIB_7220_ErrClear_RcvICRCErrClear_LSB … #define QIB_7220_ErrClear_RcvICRCErrClear_RMASK … #define QIB_7220_ErrClear_RcvVCRCErrClear_LSB … #define QIB_7220_ErrClear_RcvVCRCErrClear_RMASK … #define QIB_7220_ErrClear_RcvFormatErrClear_LSB … #define QIB_7220_ErrClear_RcvFormatErrClear_RMASK … #define QIB_7220_HwErrMask_OFFS … #define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_LSB … #define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_RMASK … #define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_LSB … #define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_RMASK … #define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_LSB … #define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_RMASK … #define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_LSB … #define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_RMASK … #define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_LSB … #define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_RMASK … #define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_LSB … #define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_RMASK … #define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB … #define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK … #define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB … #define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK … #define QIB_7220_HwErrMask_Reserved_LSB … #define QIB_7220_HwErrMask_Reserved_RMASK … #define QIB_7220_HwErrMask_PowerOnBISTFailedMask_LSB … #define QIB_7220_HwErrMask_PowerOnBISTFailedMask_RMASK … #define QIB_7220_HwErrMask_Reserved1_LSB … #define QIB_7220_HwErrMask_Reserved1_RMASK … #define QIB_7220_HwErrMask_RXEMemParityErrMask_LSB … #define QIB_7220_HwErrMask_RXEMemParityErrMask_RMASK … #define QIB_7220_HwErrMask_TXEMemParityErrMask_LSB … #define QIB_7220_HwErrMask_TXEMemParityErrMask_RMASK … #define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_LSB … #define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_RMASK … #define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_LSB … #define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_RMASK … #define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_LSB … #define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_RMASK … #define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_LSB … #define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_RMASK … #define QIB_7220_HwErrMask_Reserved2_LSB … #define QIB_7220_HwErrMask_Reserved2_RMASK … #define QIB_7220_HwErrMask_PCIeBusParityErrMask_LSB … #define QIB_7220_HwErrMask_PCIeBusParityErrMask_RMASK … #define QIB_7220_HwErrMask_PcieCplTimeoutMask_LSB … #define QIB_7220_HwErrMask_PcieCplTimeoutMask_RMASK … #define QIB_7220_HwErrMask_PoisonedTLPMask_LSB … #define QIB_7220_HwErrMask_PoisonedTLPMask_RMASK … #define QIB_7220_HwErrMask_SDmaMemReadErrMask_LSB … #define QIB_7220_HwErrMask_SDmaMemReadErrMask_RMASK … #define QIB_7220_HwErrMask_Reserved3_LSB … #define QIB_7220_HwErrMask_Reserved3_RMASK … #define QIB_7220_HwErrMask_PCIeMemParityErrMask_LSB … #define QIB_7220_HwErrMask_PCIeMemParityErrMask_RMASK … #define QIB_7220_HwErrStatus_OFFS … #define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_LSB … #define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_RMASK … #define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_LSB … #define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_RMASK … #define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_LSB … #define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_RMASK … #define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_LSB … #define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_RMASK … #define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_LSB … #define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_RMASK … #define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_LSB … #define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_RMASK … #define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB … #define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK … #define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB … #define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK … #define QIB_7220_HwErrStatus_Reserved_LSB … #define QIB_7220_HwErrStatus_Reserved_RMASK … #define QIB_7220_HwErrStatus_PowerOnBISTFailed_LSB … #define QIB_7220_HwErrStatus_PowerOnBISTFailed_RMASK … #define QIB_7220_HwErrStatus_Reserved1_LSB … #define QIB_7220_HwErrStatus_Reserved1_RMASK … #define QIB_7220_HwErrStatus_RXEMemParity_LSB … #define QIB_7220_HwErrStatus_RXEMemParity_RMASK … #define QIB_7220_HwErrStatus_TXEMemParity_LSB … #define QIB_7220_HwErrStatus_TXEMemParity_RMASK … #define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_LSB … #define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_RMASK … #define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_LSB … #define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_RMASK … #define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_LSB … #define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_RMASK … #define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_LSB … #define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_RMASK … #define QIB_7220_HwErrStatus_Reserved2_LSB … #define QIB_7220_HwErrStatus_Reserved2_RMASK … #define QIB_7220_HwErrStatus_PCIeBusParity_LSB … #define QIB_7220_HwErrStatus_PCIeBusParity_RMASK … #define QIB_7220_HwErrStatus_PcieCplTimeout_LSB … #define QIB_7220_HwErrStatus_PcieCplTimeout_RMASK … #define QIB_7220_HwErrStatus_PoisenedTLP_LSB … #define QIB_7220_HwErrStatus_PoisenedTLP_RMASK … #define QIB_7220_HwErrStatus_SDmaMemReadErr_LSB … #define QIB_7220_HwErrStatus_SDmaMemReadErr_RMASK … #define QIB_7220_HwErrStatus_Reserved3_LSB … #define QIB_7220_HwErrStatus_Reserved3_RMASK … #define QIB_7220_HwErrStatus_PCIeMemParity_LSB … #define QIB_7220_HwErrStatus_PCIeMemParity_RMASK … #define QIB_7220_HwErrClear_OFFS … #define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_LSB … #define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_RMASK … #define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_LSB … #define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_RMASK … #define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_LSB … #define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_RMASK … #define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_LSB … #define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_RMASK … #define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_LSB … #define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_RMASK … #define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_LSB … #define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_RMASK … #define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB … #define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK … #define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB … #define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK … #define QIB_7220_HwErrClear_Reserved_LSB … #define QIB_7220_HwErrClear_Reserved_RMASK … #define QIB_7220_HwErrClear_PowerOnBISTFailedClear_LSB … #define QIB_7220_HwErrClear_PowerOnBISTFailedClear_RMASK … #define QIB_7220_HwErrClear_Reserved1_LSB … #define QIB_7220_HwErrClear_Reserved1_RMASK … #define QIB_7220_HwErrClear_RXEMemParityClear_LSB … #define QIB_7220_HwErrClear_RXEMemParityClear_RMASK … #define QIB_7220_HwErrClear_TXEMemParityClear_LSB … #define QIB_7220_HwErrClear_TXEMemParityClear_RMASK … #define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_LSB … #define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_RMASK … #define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_LSB … #define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_RMASK … #define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_LSB … #define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_RMASK … #define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_LSB … #define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_RMASK … #define QIB_7220_HwErrClear_Reserved2_LSB … #define QIB_7220_HwErrClear_Reserved2_RMASK … #define QIB_7220_HwErrClear_PCIeBusParityClr_LSB … #define QIB_7220_HwErrClear_PCIeBusParityClr_RMASK … #define QIB_7220_HwErrClear_PcieCplTimeoutClear_LSB … #define QIB_7220_HwErrClear_PcieCplTimeoutClear_RMASK … #define QIB_7220_HwErrClear_PoisonedTLPClear_LSB … #define QIB_7220_HwErrClear_PoisonedTLPClear_RMASK … #define QIB_7220_HwErrClear_SDmaMemReadErrClear_LSB … #define QIB_7220_HwErrClear_SDmaMemReadErrClear_RMASK … #define QIB_7220_HwErrClear_Reserved3_LSB … #define QIB_7220_HwErrClear_Reserved3_RMASK … #define QIB_7220_HwErrClear_PCIeMemParityClr_LSB … #define QIB_7220_HwErrClear_PCIeMemParityClr_RMASK … #define QIB_7220_HwDiagCtrl_OFFS … #define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK … #define QIB_7220_HwDiagCtrl_CounterWrEnable_LSB … #define QIB_7220_HwDiagCtrl_CounterWrEnable_RMASK … #define QIB_7220_HwDiagCtrl_CounterDisable_LSB … #define QIB_7220_HwDiagCtrl_CounterDisable_RMASK … #define QIB_7220_HwDiagCtrl_Reserved_LSB … #define QIB_7220_HwDiagCtrl_Reserved_RMASK … #define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_RMASK … #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_LSB … #define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_RMASK … #define QIB_7220_HwDiagCtrl_Reserved1_LSB … #define QIB_7220_HwDiagCtrl_Reserved1_RMASK … #define QIB_7220_HwDiagCtrl_forcePCIeBusParity_LSB … #define QIB_7220_HwDiagCtrl_forcePCIeBusParity_RMASK … #define QIB_7220_HwDiagCtrl_Reserved2_LSB … #define QIB_7220_HwDiagCtrl_Reserved2_RMASK … #define QIB_7220_HwDiagCtrl_forcePCIeMemParity_LSB … #define QIB_7220_HwDiagCtrl_forcePCIeMemParity_RMASK … #define QIB_7220_REG_0000B8_OFFS … #define QIB_7220_IBCStatus_OFFS … #define QIB_7220_IBCStatus_TxCreditOk_LSB … #define QIB_7220_IBCStatus_TxCreditOk_RMASK … #define QIB_7220_IBCStatus_TxReady_LSB … #define QIB_7220_IBCStatus_TxReady_RMASK … #define QIB_7220_IBCStatus_Reserved_LSB … #define QIB_7220_IBCStatus_Reserved_RMASK … #define QIB_7220_IBCStatus_IBTxLaneReversed_LSB … #define QIB_7220_IBCStatus_IBTxLaneReversed_RMASK … #define QIB_7220_IBCStatus_IBRxLaneReversed_LSB … #define QIB_7220_IBCStatus_IBRxLaneReversed_RMASK … #define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_LSB … #define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_RMASK … #define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_LSB … #define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_RMASK … #define QIB_7220_IBCStatus_LinkWidthActive_LSB … #define QIB_7220_IBCStatus_LinkWidthActive_RMASK … #define QIB_7220_IBCStatus_LinkSpeedActive_LSB … #define QIB_7220_IBCStatus_LinkSpeedActive_RMASK … #define QIB_7220_IBCStatus_LinkState_LSB … #define QIB_7220_IBCStatus_LinkState_RMASK … #define QIB_7220_IBCStatus_LinkTrainingState_LSB … #define QIB_7220_IBCStatus_LinkTrainingState_RMASK … #define QIB_7220_IBCCtrl_OFFS … #define QIB_7220_IBCCtrl_Loopback_LSB … #define QIB_7220_IBCCtrl_Loopback_RMASK … #define QIB_7220_IBCCtrl_LinkDownDefaultState_LSB … #define QIB_7220_IBCCtrl_LinkDownDefaultState_RMASK … #define QIB_7220_IBCCtrl_Reserved_LSB … #define QIB_7220_IBCCtrl_Reserved_RMASK … #define QIB_7220_IBCCtrl_CreditScale_LSB … #define QIB_7220_IBCCtrl_CreditScale_RMASK … #define QIB_7220_IBCCtrl_OverrunThreshold_LSB … #define QIB_7220_IBCCtrl_OverrunThreshold_RMASK … #define QIB_7220_IBCCtrl_PhyerrThreshold_LSB … #define QIB_7220_IBCCtrl_PhyerrThreshold_RMASK … #define QIB_7220_IBCCtrl_MaxPktLen_LSB … #define QIB_7220_IBCCtrl_MaxPktLen_RMASK … #define QIB_7220_IBCCtrl_LinkCmd_LSB … #define QIB_7220_IBCCtrl_LinkCmd_RMASK … #define QIB_7220_IBCCtrl_LinkInitCmd_LSB … #define QIB_7220_IBCCtrl_LinkInitCmd_RMASK … #define QIB_7220_IBCCtrl_FlowCtrlWaterMark_LSB … #define QIB_7220_IBCCtrl_FlowCtrlWaterMark_RMASK … #define QIB_7220_IBCCtrl_FlowCtrlPeriod_LSB … #define QIB_7220_IBCCtrl_FlowCtrlPeriod_RMASK … #define QIB_7220_EXTStatus_OFFS … #define QIB_7220_EXTStatus_GPIOIn_LSB … #define QIB_7220_EXTStatus_GPIOIn_RMASK … #define QIB_7220_EXTStatus_Reserved_LSB … #define QIB_7220_EXTStatus_Reserved_RMASK … #define QIB_7220_EXTStatus_Reserved1_LSB … #define QIB_7220_EXTStatus_Reserved1_RMASK … #define QIB_7220_EXTStatus_MemBISTDisabled_LSB … #define QIB_7220_EXTStatus_MemBISTDisabled_RMASK … #define QIB_7220_EXTStatus_MemBISTEndTest_LSB … #define QIB_7220_EXTStatus_MemBISTEndTest_RMASK … #define QIB_7220_EXTStatus_Reserved2_LSB … #define QIB_7220_EXTStatus_Reserved2_RMASK … #define QIB_7220_EXTCtrl_OFFS … #define QIB_7220_EXTCtrl_GPIOOe_LSB … #define QIB_7220_EXTCtrl_GPIOOe_RMASK … #define QIB_7220_EXTCtrl_GPIOInvert_LSB … #define QIB_7220_EXTCtrl_GPIOInvert_RMASK … #define QIB_7220_EXTCtrl_Reserved_LSB … #define QIB_7220_EXTCtrl_Reserved_RMASK … #define QIB_7220_EXTCtrl_LEDPriPortGreenOn_LSB … #define QIB_7220_EXTCtrl_LEDPriPortGreenOn_RMASK … #define QIB_7220_EXTCtrl_LEDPriPortYellowOn_LSB … #define QIB_7220_EXTCtrl_LEDPriPortYellowOn_RMASK … #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_LSB … #define QIB_7220_EXTCtrl_LEDGblOkGreenOn_RMASK … #define QIB_7220_EXTCtrl_LEDGblErrRedOff_LSB … #define QIB_7220_EXTCtrl_LEDGblErrRedOff_RMASK … #define QIB_7220_GPIOOut_OFFS … #define QIB_7220_GPIOMask_OFFS … #define QIB_7220_GPIOStatus_OFFS … #define QIB_7220_GPIOClear_OFFS … #define QIB_7220_RcvCtrl_OFFS … #define QIB_7220_RcvCtrl_Reserved_LSB … #define QIB_7220_RcvCtrl_Reserved_RMASK … #define QIB_7220_RcvCtrl_RcvQPMapEnable_LSB … #define QIB_7220_RcvCtrl_RcvQPMapEnable_RMASK … #define QIB_7220_RcvCtrl_PortCfg_LSB … #define QIB_7220_RcvCtrl_PortCfg_RMASK … #define QIB_7220_RcvCtrl_TailUpd_LSB … #define QIB_7220_RcvCtrl_TailUpd_RMASK … #define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_LSB … #define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_RMASK … #define QIB_7220_RcvCtrl_IntrAvail_LSB … #define QIB_7220_RcvCtrl_IntrAvail_RMASK … #define QIB_7220_RcvCtrl_PortEnable_LSB … #define QIB_7220_RcvCtrl_PortEnable_RMASK … #define QIB_7220_RcvBTHQP_OFFS … #define QIB_7220_RcvBTHQP_Reserved_LSB … #define QIB_7220_RcvBTHQP_Reserved_RMASK … #define QIB_7220_RcvBTHQP_RcvBTHQP_LSB … #define QIB_7220_RcvBTHQP_RcvBTHQP_RMASK … #define QIB_7220_RcvHdrSize_OFFS … #define QIB_7220_RcvHdrCnt_OFFS … #define QIB_7220_RcvHdrEntSize_OFFS … #define QIB_7220_RcvTIDBase_OFFS … #define QIB_7220_RcvTIDCnt_OFFS … #define QIB_7220_RcvEgrBase_OFFS … #define QIB_7220_RcvEgrCnt_OFFS … #define QIB_7220_RcvBufBase_OFFS … #define QIB_7220_RcvBufSize_OFFS … #define QIB_7220_RxIntMemBase_OFFS … #define QIB_7220_RxIntMemSize_OFFS … #define QIB_7220_RcvPartitionKey_OFFS … #define QIB_7220_RcvQPMulticastPort_OFFS … #define QIB_7220_RcvQPMulticastPort_Reserved_LSB … #define QIB_7220_RcvQPMulticastPort_Reserved_RMASK … #define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_LSB … #define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_RMASK … #define QIB_7220_RcvPktLEDCnt_OFFS … #define QIB_7220_RcvPktLEDCnt_ONperiod_LSB … #define QIB_7220_RcvPktLEDCnt_ONperiod_RMASK … #define QIB_7220_RcvPktLEDCnt_OFFperiod_LSB … #define QIB_7220_RcvPktLEDCnt_OFFperiod_RMASK … #define QIB_7220_IBCDDRCtrl_OFFS … #define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_LSB … #define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_RMASK … #define QIB_7220_IBCDDRCtrl_IB_DLID_LSB … #define QIB_7220_IBCDDRCtrl_IB_DLID_RMASK … #define QIB_7220_IBCDDRCtrl_Reserved_LSB … #define QIB_7220_IBCDDRCtrl_Reserved_RMASK … #define QIB_7220_IBCDDRCtrl_HRTBT_REQ_LSB … #define QIB_7220_IBCDDRCtrl_HRTBT_REQ_RMASK … #define QIB_7220_IBCDDRCtrl_HRTBT_PORT_LSB … #define QIB_7220_IBCDDRCtrl_HRTBT_PORT_RMASK … #define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_LSB … #define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_RMASK … #define QIB_7220_IBCDDRCtrl_HRTBT_ENB_LSB … #define QIB_7220_IBCDDRCtrl_HRTBT_ENB_RMASK … #define QIB_7220_IBCDDRCtrl_SD_DDS_LSB … #define QIB_7220_IBCDDRCtrl_SD_DDS_RMASK … #define QIB_7220_IBCDDRCtrl_SD_DDSV_LSB … #define QIB_7220_IBCDDRCtrl_SD_DDSV_RMASK … #define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_LSB … #define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_RMASK … #define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_LSB … #define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_RMASK … #define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_LSB … #define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_RMASK … #define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_LSB … #define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_RMASK … #define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_LSB … #define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_RMASK … #define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_LSB … #define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_RMASK … #define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_LSB … #define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_RMASK … #define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_LSB … #define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_RMASK … #define QIB_7220_IBCDDRCtrl_SD_SPEED_LSB … #define QIB_7220_IBCDDRCtrl_SD_SPEED_RMASK … #define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_LSB … #define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_RMASK … #define QIB_7220_HRTBT_GUID_OFFS … #define QIB_7220_IBCDDRCtrl2_OFFS … #define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_LSB … #define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_RMASK … #define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_LSB … #define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_RMASK … #define QIB_7220_IBCDDRStatus_OFFS … #define QIB_7220_IBCDDRStatus_heartbeat_timed_out_LSB … #define QIB_7220_IBCDDRStatus_heartbeat_timed_out_RMASK … #define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_LSB … #define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_RMASK … #define QIB_7220_IBCDDRStatus_RxEqLocalDevice_LSB … #define QIB_7220_IBCDDRStatus_RxEqLocalDevice_RMASK … #define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_LSB … #define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_RMASK … #define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_LSB … #define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_RMASK … #define QIB_7220_JIntReload_OFFS … #define QIB_7220_JIntReload_J_limit_reload_LSB … #define QIB_7220_JIntReload_J_limit_reload_RMASK … #define QIB_7220_JIntReload_J_reload_LSB … #define QIB_7220_JIntReload_J_reload_RMASK … #define QIB_7220_IBNCModeCtrl_OFFS … #define QIB_7220_IBNCModeCtrl_Reserved_LSB … #define QIB_7220_IBNCModeCtrl_Reserved_RMASK … #define QIB_7220_IBNCModeCtrl_TSMCode_TS2_LSB … #define QIB_7220_IBNCModeCtrl_TSMCode_TS2_RMASK … #define QIB_7220_IBNCModeCtrl_TSMCode_TS1_LSB … #define QIB_7220_IBNCModeCtrl_TSMCode_TS1_RMASK … #define QIB_7220_IBNCModeCtrl_Reserved1_LSB … #define QIB_7220_IBNCModeCtrl_Reserved1_RMASK … #define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_LSB … #define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_RMASK … #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_LSB … #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_RMASK … #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_LSB … #define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_RMASK … #define QIB_7220_SendCtrl_OFFS … #define QIB_7220_SendCtrl_Disarm_LSB … #define QIB_7220_SendCtrl_Disarm_RMASK … #define QIB_7220_SendCtrl_Reserved_LSB … #define QIB_7220_SendCtrl_Reserved_RMASK … #define QIB_7220_SendCtrl_AvailUpdThld_LSB … #define QIB_7220_SendCtrl_AvailUpdThld_RMASK … #define QIB_7220_SendCtrl_DisarmPIOBuf_LSB … #define QIB_7220_SendCtrl_DisarmPIOBuf_RMASK … #define QIB_7220_SendCtrl_Reserved1_LSB … #define QIB_7220_SendCtrl_Reserved1_RMASK … #define QIB_7220_SendCtrl_SDmaHalt_LSB … #define QIB_7220_SendCtrl_SDmaHalt_RMASK … #define QIB_7220_SendCtrl_SDmaEnable_LSB … #define QIB_7220_SendCtrl_SDmaEnable_RMASK … #define QIB_7220_SendCtrl_SDmaSingleDescriptor_LSB … #define QIB_7220_SendCtrl_SDmaSingleDescriptor_RMASK … #define QIB_7220_SendCtrl_SDmaIntEnable_LSB … #define QIB_7220_SendCtrl_SDmaIntEnable_RMASK … #define QIB_7220_SendCtrl_Reserved2_LSB … #define QIB_7220_SendCtrl_Reserved2_RMASK … #define QIB_7220_SendCtrl_SSpecialTriggerEn_LSB … #define QIB_7220_SendCtrl_SSpecialTriggerEn_RMASK … #define QIB_7220_SendCtrl_SPioEnable_LSB … #define QIB_7220_SendCtrl_SPioEnable_RMASK … #define QIB_7220_SendCtrl_SendBufAvailUpd_LSB … #define QIB_7220_SendCtrl_SendBufAvailUpd_RMASK … #define QIB_7220_SendCtrl_SendIntBufAvail_LSB … #define QIB_7220_SendCtrl_SendIntBufAvail_RMASK … #define QIB_7220_SendCtrl_Abort_LSB … #define QIB_7220_SendCtrl_Abort_RMASK … #define QIB_7220_SendBufBase_OFFS … #define QIB_7220_SendBufBase_Reserved_LSB … #define QIB_7220_SendBufBase_Reserved_RMASK … #define QIB_7220_SendBufBase_BaseAddr_LargePIO_LSB … #define QIB_7220_SendBufBase_BaseAddr_LargePIO_RMASK … #define QIB_7220_SendBufBase_Reserved1_LSB … #define QIB_7220_SendBufBase_Reserved1_RMASK … #define QIB_7220_SendBufBase_BaseAddr_SmallPIO_LSB … #define QIB_7220_SendBufBase_BaseAddr_SmallPIO_RMASK … #define QIB_7220_SendBufSize_OFFS … #define QIB_7220_SendBufSize_Reserved_LSB … #define QIB_7220_SendBufSize_Reserved_RMASK … #define QIB_7220_SendBufSize_Size_LargePIO_LSB … #define QIB_7220_SendBufSize_Size_LargePIO_RMASK … #define QIB_7220_SendBufSize_Reserved1_LSB … #define QIB_7220_SendBufSize_Reserved1_RMASK … #define QIB_7220_SendBufSize_Size_SmallPIO_LSB … #define QIB_7220_SendBufSize_Size_SmallPIO_RMASK … #define QIB_7220_SendBufCnt_OFFS … #define QIB_7220_SendBufCnt_Reserved_LSB … #define QIB_7220_SendBufCnt_Reserved_RMASK … #define QIB_7220_SendBufCnt_Num_LargeBuffers_LSB … #define QIB_7220_SendBufCnt_Num_LargeBuffers_RMASK … #define QIB_7220_SendBufCnt_Reserved1_LSB … #define QIB_7220_SendBufCnt_Reserved1_RMASK … #define QIB_7220_SendBufCnt_Num_SmallBuffers_LSB … #define QIB_7220_SendBufCnt_Num_SmallBuffers_RMASK … #define QIB_7220_SendBufAvailAddr_OFFS … #define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_LSB … #define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_RMASK … #define QIB_7220_SendBufAvailAddr_Reserved_LSB … #define QIB_7220_SendBufAvailAddr_Reserved_RMASK … #define QIB_7220_TxIntMemBase_OFFS … #define QIB_7220_TxIntMemSize_OFFS … #define QIB_7220_SendDmaBase_OFFS … #define QIB_7220_SendDmaBase_Reserved_LSB … #define QIB_7220_SendDmaBase_Reserved_RMASK … #define QIB_7220_SendDmaBase_SendDmaBase_LSB … #define QIB_7220_SendDmaBase_SendDmaBase_RMASK … #define QIB_7220_SendDmaLenGen_OFFS … #define QIB_7220_SendDmaLenGen_Reserved_LSB … #define QIB_7220_SendDmaLenGen_Reserved_RMASK … #define QIB_7220_SendDmaLenGen_Generation_LSB … #define QIB_7220_SendDmaLenGen_Generation_MSB … #define QIB_7220_SendDmaLenGen_Generation_RMASK … #define QIB_7220_SendDmaLenGen_Length_LSB … #define QIB_7220_SendDmaLenGen_Length_RMASK … #define QIB_7220_SendDmaTail_OFFS … #define QIB_7220_SendDmaTail_Reserved_LSB … #define QIB_7220_SendDmaTail_Reserved_RMASK … #define QIB_7220_SendDmaTail_SendDmaTail_LSB … #define QIB_7220_SendDmaTail_SendDmaTail_RMASK … #define QIB_7220_SendDmaHead_OFFS … #define QIB_7220_SendDmaHead_Reserved_LSB … #define QIB_7220_SendDmaHead_Reserved_RMASK … #define QIB_7220_SendDmaHead_InternalSendDmaHead_LSB … #define QIB_7220_SendDmaHead_InternalSendDmaHead_RMASK … #define QIB_7220_SendDmaHead_Reserved1_LSB … #define QIB_7220_SendDmaHead_Reserved1_RMASK … #define QIB_7220_SendDmaHead_SendDmaHead_LSB … #define QIB_7220_SendDmaHead_SendDmaHead_RMASK … #define QIB_7220_SendDmaHeadAddr_OFFS … #define QIB_7220_SendDmaHeadAddr_Reserved_LSB … #define QIB_7220_SendDmaHeadAddr_Reserved_RMASK … #define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_LSB … #define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_RMASK … #define QIB_7220_SendDmaBufMask0_OFFS … #define QIB_7220_SendDmaBufMask0_BufMask_63_0_LSB … #define QIB_7220_SendDmaBufMask0_BufMask_63_0_RMASK … #define QIB_7220_SendDmaStatus_OFFS … #define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_LSB … #define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_RMASK … #define QIB_7220_SendDmaStatus_AbortInProg_LSB … #define QIB_7220_SendDmaStatus_AbortInProg_RMASK … #define QIB_7220_SendDmaStatus_InternalSDmaEnable_LSB … #define QIB_7220_SendDmaStatus_InternalSDmaEnable_RMASK … #define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_LSB … #define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_RMASK … #define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_LSB … #define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_RMASK … #define QIB_7220_SendDmaStatus_RpyTag_7_0_LSB … #define QIB_7220_SendDmaStatus_RpyTag_7_0_RMASK … #define QIB_7220_SendDmaStatus_ScbFull_LSB … #define QIB_7220_SendDmaStatus_ScbFull_RMASK … #define QIB_7220_SendDmaStatus_ScbEmpty_LSB … #define QIB_7220_SendDmaStatus_ScbEmpty_RMASK … #define QIB_7220_SendDmaStatus_ScbEntryValid_LSB … #define QIB_7220_SendDmaStatus_ScbEntryValid_RMASK … #define QIB_7220_SendDmaStatus_ScbFetchDescFlag_LSB … #define QIB_7220_SendDmaStatus_ScbFetchDescFlag_RMASK … #define QIB_7220_SendDmaStatus_SplFifoReadyToGo_LSB … #define QIB_7220_SendDmaStatus_SplFifoReadyToGo_RMASK … #define QIB_7220_SendDmaStatus_SplFifoDisarmed_LSB … #define QIB_7220_SendDmaStatus_SplFifoDisarmed_RMASK … #define QIB_7220_SendDmaStatus_SplFifoEmpty_LSB … #define QIB_7220_SendDmaStatus_SplFifoEmpty_RMASK … #define QIB_7220_SendDmaStatus_SplFifoFull_LSB … #define QIB_7220_SendDmaStatus_SplFifoFull_RMASK … #define QIB_7220_SendDmaStatus_SplFifoBufNum_LSB … #define QIB_7220_SendDmaStatus_SplFifoBufNum_RMASK … #define QIB_7220_SendDmaStatus_SplFifoDescIndex_LSB … #define QIB_7220_SendDmaStatus_SplFifoDescIndex_RMASK … #define QIB_7220_SendBufErr0_OFFS … #define QIB_7220_SendBufErr0_SendBufErr_63_0_LSB … #define QIB_7220_SendBufErr0_SendBufErr_63_0_RMASK … #define QIB_7220_RcvHdrAddr0_OFFS … #define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_LSB … #define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_RMASK … #define QIB_7220_RcvHdrAddr0_Reserved_LSB … #define QIB_7220_RcvHdrAddr0_Reserved_RMASK … #define QIB_7220_RcvHdrTailAddr0_OFFS … #define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB … #define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK … #define QIB_7220_RcvHdrTailAddr0_Reserved_LSB … #define QIB_7220_RcvHdrTailAddr0_Reserved_RMASK … #define QIB_7220_ibsd_epb_access_ctrl_OFFS … #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_LSB … #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_RMASK … #define QIB_7220_ibsd_epb_access_ctrl_Reserved_LSB … #define QIB_7220_ibsd_epb_access_ctrl_Reserved_RMASK … #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_LSB … #define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_OFFS … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_Reserved_LSB … #define QIB_7220_ibsd_epb_transaction_reg_Reserved_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_LSB … #define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_Reserved1_LSB … #define QIB_7220_ibsd_epb_transaction_reg_Reserved1_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_Reserved2_LSB … #define QIB_7220_ibsd_epb_transaction_reg_Reserved2_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_RMASK … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_LSB … #define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_RMASK … #define QIB_7220_XGXSCfg_OFFS … #define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_LSB … #define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_RMASK … #define QIB_7220_XGXSCfg_Reserved_LSB … #define QIB_7220_XGXSCfg_Reserved_RMASK … #define QIB_7220_XGXSCfg_link_sync_mask_LSB … #define QIB_7220_XGXSCfg_link_sync_mask_RMASK … #define QIB_7220_XGXSCfg_Reserved1_LSB … #define QIB_7220_XGXSCfg_Reserved1_RMASK … #define QIB_7220_XGXSCfg_xcv_reset_LSB … #define QIB_7220_XGXSCfg_xcv_reset_RMASK … #define QIB_7220_XGXSCfg_Reserved2_LSB … #define QIB_7220_XGXSCfg_Reserved2_RMASK … #define QIB_7220_XGXSCfg_tx_rx_reset_LSB … #define QIB_7220_XGXSCfg_tx_rx_reset_RMASK … #define QIB_7220_IBSerDesCtrl_OFFS … #define QIB_7220_IBSerDesCtrl_Reserved_LSB … #define QIB_7220_IBSerDesCtrl_Reserved_RMASK … #define QIB_7220_IBSerDesCtrl_INT_uC_LSB … #define QIB_7220_IBSerDesCtrl_INT_uC_RMASK … #define QIB_7220_IBSerDesCtrl_CKSEL_uC_LSB … #define QIB_7220_IBSerDesCtrl_CKSEL_uC_RMASK … #define QIB_7220_IBSerDesCtrl_PLLN_LSB … #define QIB_7220_IBSerDesCtrl_PLLN_RMASK … #define QIB_7220_IBSerDesCtrl_PLLM_LSB … #define QIB_7220_IBSerDesCtrl_PLLM_RMASK … #define QIB_7220_IBSerDesCtrl_TXOBPD_LSB … #define QIB_7220_IBSerDesCtrl_TXOBPD_RMASK … #define QIB_7220_IBSerDesCtrl_TWC_LSB … #define QIB_7220_IBSerDesCtrl_TWC_RMASK … #define QIB_7220_IBSerDesCtrl_RXIDLE_LSB … #define QIB_7220_IBSerDesCtrl_RXIDLE_RMASK … #define QIB_7220_IBSerDesCtrl_RXINV_LSB … #define QIB_7220_IBSerDesCtrl_RXINV_RMASK … #define QIB_7220_IBSerDesCtrl_TXINV_LSB … #define QIB_7220_IBSerDesCtrl_TXINV_RMASK … #define QIB_7220_IBSerDesCtrl_Reserved1_LSB … #define QIB_7220_IBSerDesCtrl_Reserved1_RMASK … #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_LSB … #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_RMASK … #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_LSB … #define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_RMASK … #define QIB_7220_IBSerDesCtrl_Reserved2_LSB … #define QIB_7220_IBSerDesCtrl_Reserved2_RMASK … #define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_LSB … #define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_RMASK … #define QIB_7220_pciesd_epb_access_ctrl_OFFS … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_LSB … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_RMASK … #define QIB_7220_pciesd_epb_access_ctrl_Reserved_LSB … #define QIB_7220_pciesd_epb_access_ctrl_Reserved_RMASK … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_LSB … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_RMASK … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_LSB … #define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_OFFS … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_Reserved_LSB … #define QIB_7220_pciesd_epb_transaction_reg_Reserved_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_LSB … #define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_Reserved1_LSB … #define QIB_7220_pciesd_epb_transaction_reg_Reserved1_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_RMASK … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_LSB … #define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_RMASK … #define QIB_7220_SerDes_DDSRXEQ0_OFFS … #define QIB_7220_SerDes_DDSRXEQ0_reg_addr_LSB … #define QIB_7220_SerDes_DDSRXEQ0_reg_addr_RMASK … #define QIB_7220_SerDes_DDSRXEQ0_element_num_LSB … #define QIB_7220_SerDes_DDSRXEQ0_element_num_RMASK … #define QIB_7220_LBIntCnt_OFFS … #define QIB_7220_LBFlowStallCnt_OFFS … #define QIB_7220_TxSDmaDescCnt_OFFS … #define QIB_7220_TxUnsupVLErrCnt_OFFS … #define QIB_7220_TxDataPktCnt_OFFS … #define QIB_7220_TxFlowPktCnt_OFFS … #define QIB_7220_TxDwordCnt_OFFS … #define QIB_7220_TxLenErrCnt_OFFS … #define QIB_7220_TxMaxMinLenErrCnt_OFFS … #define QIB_7220_TxUnderrunCnt_OFFS … #define QIB_7220_TxFlowStallCnt_OFFS … #define QIB_7220_TxDroppedPktCnt_OFFS … #define QIB_7220_RxDroppedPktCnt_OFFS … #define QIB_7220_RxDataPktCnt_OFFS … #define QIB_7220_RxFlowPktCnt_OFFS … #define QIB_7220_RxDwordCnt_OFFS … #define QIB_7220_RxLenErrCnt_OFFS … #define QIB_7220_RxMaxMinLenErrCnt_OFFS … #define QIB_7220_RxICRCErrCnt_OFFS … #define QIB_7220_RxVCRCErrCnt_OFFS … #define QIB_7220_RxFlowCtrlViolCnt_OFFS … #define QIB_7220_RxVersionErrCnt_OFFS … #define QIB_7220_RxLinkMalformCnt_OFFS … #define QIB_7220_RxEBPCnt_OFFS … #define QIB_7220_RxLPCRCErrCnt_OFFS … #define QIB_7220_RxBufOvflCnt_OFFS … #define QIB_7220_RxTIDFullErrCnt_OFFS … #define QIB_7220_RxTIDValidErrCnt_OFFS … #define QIB_7220_RxPKeyMismatchCnt_OFFS … #define QIB_7220_RxP0HdrEgrOvflCnt_OFFS … #define QIB_7220_IBStatusChangeCnt_OFFS … #define QIB_7220_IBLinkErrRecoveryCnt_OFFS … #define QIB_7220_IBLinkDownedCnt_OFFS … #define QIB_7220_IBSymbolErrCnt_OFFS … #define QIB_7220_RxVL15DroppedPktCnt_OFFS … #define QIB_7220_RxOtherLocalPhyErrCnt_OFFS … #define QIB_7220_PcieRetryBufDiagQwordCnt_OFFS … #define QIB_7220_ExcessBufferOvflCnt_OFFS … #define QIB_7220_LocalLinkIntegrityErrCnt_OFFS … #define QIB_7220_RxVlErrCnt_OFFS … #define QIB_7220_RxDlidFltrCnt_OFFS … #define QIB_7220_CNT_0131C8_OFFS … #define QIB_7220_PSStat_OFFS … #define QIB_7220_PSStart_OFFS … #define QIB_7220_PSInterval_OFFS … #define QIB_7220_PSRcvDataCount_OFFS … #define QIB_7220_PSRcvPktsCount_OFFS … #define QIB_7220_PSXmitDataCount_OFFS … #define QIB_7220_PSXmitPktsCount_OFFS … #define QIB_7220_PSXmitWaitCount_OFFS … #define QIB_7220_CNT_013240_OFFS … #define QIB_7220_RcvEgrArray_OFFS … #define QIB_7220_MEM_038000_OFFS … #define QIB_7220_RcvTIDArray0_OFFS … #define QIB_7220_PIOLaunchFIFO_OFFS … #define QIB_7220_MEM_064480_OFFS … #define QIB_7220_SendPIOpbcCache_OFFS … #define QIB_7220_MEM_064C80_OFFS … #define QIB_7220_PreLaunchFIFO_OFFS … #define QIB_7220_MEM_065080_OFFS … #define QIB_7220_ScoreBoard_OFFS … #define QIB_7220_MEM_065440_OFFS … #define QIB_7220_DescriptorFIFO_OFFS … #define QIB_7220_MEM_065880_OFFS … #define QIB_7220_RcvBuf1_OFFS … #define QIB_7220_MEM_074800_OFFS … #define QIB_7220_RcvBuf2_OFFS … #define QIB_7220_MEM_076400_OFFS … #define QIB_7220_RcvFlags_OFFS … #define QIB_7220_MEM_078400_OFFS … #define QIB_7220_RcvLookupBuf1_OFFS … #define QIB_7220_MEM_07A400_OFFS … #define QIB_7220_RcvDMADatBuf_OFFS … #define QIB_7220_RcvDMAHdrBuf_OFFS … #define QIB_7220_MiscRXEIntMem_OFFS … #define QIB_7220_MEM_07D400_OFFS … #define QIB_7220_PCIERcvBuf_OFFS … #define QIB_7220_PCIERetryBuf_OFFS … #define QIB_7220_PCIERcvBufRdToWrAddr_OFFS … #define QIB_7220_PCIECplBuf_OFFS … #define QIB_7220_IBSerDesMappTable_OFFS … #define QIB_7220_MEM_095000_OFFS … #define QIB_7220_SendBuf0_MA_OFFS … #define QIB_7220_MEM_1A0000_OFFS …
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