/* * Copyright (c) 2013 Intel Corporation. All rights reserved. * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ /* * This file contains all of the code that is specific to the SerDes * on the QLogic_IB 7220 chip. */ #include <linux/pci.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/firmware.h> #include "qib.h" #include "qib_7220.h" #define SD7220_FW_NAME … MODULE_FIRMWARE(…); /* * Same as in qib_iba7220.c, but just the registers needed here. * Could move whole set to qib_7220.h, but decided better to keep * local. */ #define KREG_IDX(regname) … #define kr_hwerrclear … #define kr_hwerrmask … #define kr_hwerrstatus … #define kr_ibcstatus … #define kr_ibserdesctrl … #define kr_scratch … #define kr_xgxs_cfg … /* these are used only here, not in qib_iba7220.c */ #define kr_ibsd_epb_access_ctrl … #define kr_ibsd_epb_transaction_reg … #define kr_pciesd_epb_transaction_reg … #define kr_pciesd_epb_access_ctrl … #define kr_serdes_ddsrxeq0 … /* * The IBSerDesMappTable is a memory that holds values to be stored in * various SerDes registers by IBC. */ #define kr_serdes_maptable … /* * Below used for sdnum parameter, selecting one of the two sections * used for PCIe, or the single SerDes used for IB. */ #define PCIE_SERDES0 … #define PCIE_SERDES1 … /* * The EPB requires addressing in a particular form. EPB_LOC() is intended * to make #definitions a little more readable. */ #define EPB_ADDR_SHF … #define EPB_LOC(chn, elt, reg) … #define EPB_IB_QUAD0_CS_SHF … #define EPB_IB_QUAD0_CS … #define EPB_IB_UC_CS_SHF … #define EPB_PCIE_UC_CS_SHF … #define EPB_GLOBAL_WR … /* Forward declarations. */ static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, u32 data, u32 mask); static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, int mask); static int qib_sd_trimdone_poll(struct qib_devdata *dd); static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where); static int qib_sd_setvals(struct qib_devdata *dd); static int qib_sd_early(struct qib_devdata *dd); static int qib_sd_dactrim(struct qib_devdata *dd); static int qib_internal_presets(struct qib_devdata *dd); /* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */ static int qib_sd_trimself(struct qib_devdata *dd, int val); static int epb_access(struct qib_devdata *dd, int sdnum, int claim); static int qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw); static int qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw); /* * Below keeps track of whether the "once per power-on" initialization has * been done, because uC code Version 1.32.17 or higher allows the uC to * be reset at will, and Automatic Equalization may require it. So the * state of the reset "pin", is no longer valid. Instead, we check for the * actual uC code having been loaded. */ static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd, const struct firmware *fw) { … } /* repeat #define for local use. "Real" #define is in qib_iba7220.c */ #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR … #define IB_MPREG5 … #define IB_MPREG6 … #define UC_PAR_CLR_D … #define UC_PAR_CLR_M … #define IB_CTRL2(chn) … #define START_EQ1(chan) … void qib_sd7220_clr_ibpar(struct qib_devdata *dd) { … } /* * After a reset or other unusual event, the epb interface may need * to be re-synchronized, between the host and the uC. * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected) */ #define IBSD_RESYNC_TRIES … #define IB_PGUDP(chn) … #define IB_CMUDONE(chn) … static int qib_resync_ibepb(struct qib_devdata *dd) { … } /* * Localize the stuff that should be done to change IB uC reset * returns <0 for errors. */ static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst) { … } static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where) { … } /* * Below is portion of IBA7220-specific bringup_serdes() that actually * deals with registers and memory within the SerDes itself. * Post IB uC code version 1.32.17, was_reset being 1 is not really * informative, so we double-check. */ int qib_sd7220_init(struct qib_devdata *dd) { … } #define EPB_ACC_REQ … #define EPB_ACC_GNT … #define EPB_DATA_MASK … #define EPB_RD … #define EPB_TRANS_RDY … #define EPB_TRANS_ERR … #define EPB_TRANS_TRIES … /* * query, claim, release ownership of the EPB (External Parallel Bus) * for a specified SERDES. * the "claim" parameter is >0 to claim, <0 to release, 0 to query. * Returns <0 for errors, >0 if we had ownership, else 0. */ static int epb_access(struct qib_devdata *dd, int sdnum, int claim) { … } /* * Lemma to deal with race condition of write..read to epb regs */ static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp) { … } /** * qib_sd7220_reg_mod - modify SERDES register * @dd: the qlogic_ib device * @sdnum: which SERDES to access * @loc: location - channel, element, register, as packed by EPB_LOC() macro. * @wd: Write Data - value to set in register * @mask: ones where data should be spliced into reg. * * Basic register read/modify/write, with un-needed acesses elided. That is, * a mask of zero will prevent write, while a mask of 0xFF will prevent read. * returns current (presumed, if a write was done) contents of selected * register, or <0 if errors. */ static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, u32 wd, u32 mask) { … } #define EPB_ROM_R … #define EPB_ROM_W … /* * Below, all uC-related, use appropriate UC_CS, depending * on which SerDes is used. */ #define EPB_UC_CTL … #define EPB_MADDRL … #define EPB_MADDRH … #define EPB_ROMDATA … #define EPB_RAMDATA … /* Transfer date to/from uC Program RAM of IB or PCIe SerDes */ static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc, u8 *buf, int cnt, int rd_notwr) { … } #define PROG_CHUNK … static int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum, const u8 *img, int len, int offset) { … } #define VFY_CHUNK … #define SD_PRAM_ERROR_LIMIT … static int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum, const u8 *img, int len, int offset) { … } static int qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw) { … } static int qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw) { … } /* * IRQ not set up at this point in init, so we poll. */ #define IB_SERDES_TRIM_DONE … #define TRIM_TMO … static int qib_sd_trimdone_poll(struct qib_devdata *dd) { … } #define TX_FAST_ELT … /* * Set the "negotiation" values for SERDES. These are used by the IB1.2 * link negotiation. Macros below are attempt to keep the values a * little more human-editable. * First, values related to Drive De-emphasis Settings. */ #define NUM_DDS_REGS … #define DDS_REG_MAP … #define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) … static struct dds_init { … } dds_init_vals[] = …; /* * Now the RXEQ section of the table. */ /* Hardware packs an element number and register address thus: */ #define RXEQ_INIT_RDESC(elt, addr) … #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) … #define RXEQ_VAL_ALL(elt, adr, val) … #define RXEQ_SDR_DFELTH … #define RXEQ_SDR_TLTH … #define RXEQ_SDR_G1CNT_Z1CNT … #define RXEQ_SDR_ZCNT … static struct rxeq_init { … } rxeq_init_vals[] = …; /* There are 17 values from vendor, but IBC only accesses the first 16 */ #define DDS_ROWS … #define RXEQ_ROWS … static int qib_sd_setvals(struct qib_devdata *dd) { … } #define CMUCTRL5 … #define RXHSCTRL0(chan) … #define VCDL_DAC2(chan) … #define VCDL_CTRL0(chan) … #define VCDL_CTRL2(chan) … #define START_EQ2(chan) … /* * Repeat a "store" across all channels of the IB SerDes. * Although nominally it inherits the "read value" of the last * channel it modified, the only really useful return is <0 for * failure, >= 0 for success. The parameter 'loc' is assumed to * be the location in some channel of the register to be modified * The caller can specify use of the "gang write" option of EPB, * in which case we use the specified channel data for any fields * not explicitely written. */ static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, int mask) { … } /* * Set the Tx values normally modified by IBC in IB1.2 mode to default * values, as gotten from first row of init table. */ static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi) { … } /* * Set the Rx values normally modified by IBC in IB1.2 mode to default * values, as gotten from selected column of init table. */ static int set_rxeq_vals(struct qib_devdata *dd, int vsel) { … } /* * Set the default values (row 0) for DDR Driver Demphasis. * we do this initially and whenever we turn off IB-1.2 * * The "default" values for Rx equalization are also stored to * SerDes registers. Formerly (and still default), we used set 2. * For experimenting with cables and link-partners, we allow changing * that via a module parameter. */ static unsigned qib_rxeq_set = …; module_param_named(rxeq_default_set, qib_rxeq_set, uint, S_IWUSR | S_IRUGO); MODULE_PARM_DESC(…) …; static int qib_internal_presets(struct qib_devdata *dd) { … } int qib_sd7220_presets(struct qib_devdata *dd) { … } static int qib_sd_trimself(struct qib_devdata *dd, int val) { … } static int qib_sd_early(struct qib_devdata *dd) { … } #define BACTRL(chnl) … #define LDOUTCTRL1(chnl) … #define RXHSSTATUS(chnl) … static int qib_sd_dactrim(struct qib_devdata *dd) { … } #define RELOCK_FIRST_MS … #define RXLSPPM(chan) … void toggle_7220_rclkrls(struct qib_devdata *dd) { … } /* * Shut down the timer that polls for relock occasions, if needed * this is "hooked" from qib_7220_quiet_serdes(), which is called * just before qib_shutdown_device() in qib_driver.c shuts down all * the other timers */ void shutdown_7220_relock_poll(struct qib_devdata *dd) { … } static unsigned qib_relock_by_timer = …; module_param_named(relock_by_timer, qib_relock_by_timer, uint, S_IWUSR | S_IRUGO); MODULE_PARM_DESC(…) …; static void qib_run_relock(struct timer_list *t) { … } void set_7220_relock_poll(struct qib_devdata *dd, int ibup) { … }
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