/* * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ #define QIB_7322_Revision_OFFS … #define QIB_7322_Revision_DEF … #define QIB_7322_Revision_R_Simulator_LSB … #define QIB_7322_Revision_R_Simulator_MSB … #define QIB_7322_Revision_R_Simulator_RMASK … #define QIB_7322_Revision_R_Emulation_LSB … #define QIB_7322_Revision_R_Emulation_MSB … #define QIB_7322_Revision_R_Emulation_RMASK … #define QIB_7322_Revision_R_Emulation_Revcode_LSB … #define QIB_7322_Revision_R_Emulation_Revcode_MSB … #define QIB_7322_Revision_R_Emulation_Revcode_RMASK … #define QIB_7322_Revision_BoardID_LSB … #define QIB_7322_Revision_BoardID_MSB … #define QIB_7322_Revision_BoardID_RMASK … #define QIB_7322_Revision_R_SW_LSB … #define QIB_7322_Revision_R_SW_MSB … #define QIB_7322_Revision_R_SW_RMASK … #define QIB_7322_Revision_R_Arch_LSB … #define QIB_7322_Revision_R_Arch_MSB … #define QIB_7322_Revision_R_Arch_RMASK … #define QIB_7322_Revision_R_ChipRevMajor_LSB … #define QIB_7322_Revision_R_ChipRevMajor_MSB … #define QIB_7322_Revision_R_ChipRevMajor_RMASK … #define QIB_7322_Revision_R_ChipRevMinor_LSB … #define QIB_7322_Revision_R_ChipRevMinor_MSB … #define QIB_7322_Revision_R_ChipRevMinor_RMASK … #define QIB_7322_Control_OFFS … #define QIB_7322_Control_DEF … #define QIB_7322_Control_PCIECplQDiagEn_LSB … #define QIB_7322_Control_PCIECplQDiagEn_MSB … #define QIB_7322_Control_PCIECplQDiagEn_RMASK … #define QIB_7322_Control_PCIEPostQDiagEn_LSB … #define QIB_7322_Control_PCIEPostQDiagEn_MSB … #define QIB_7322_Control_PCIEPostQDiagEn_RMASK … #define QIB_7322_Control_SDmaDescFetchPriorityEn_LSB … #define QIB_7322_Control_SDmaDescFetchPriorityEn_MSB … #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK … #define QIB_7322_Control_PCIERetryBufDiagEn_LSB … #define QIB_7322_Control_PCIERetryBufDiagEn_MSB … #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK … #define QIB_7322_Control_FreezeMode_LSB … #define QIB_7322_Control_FreezeMode_MSB … #define QIB_7322_Control_FreezeMode_RMASK … #define QIB_7322_Control_SyncReset_LSB … #define QIB_7322_Control_SyncReset_MSB … #define QIB_7322_Control_SyncReset_RMASK … #define QIB_7322_PageAlign_OFFS … #define QIB_7322_PageAlign_DEF … #define QIB_7322_ContextCnt_OFFS … #define QIB_7322_ContextCnt_DEF … #define QIB_7322_Scratch_OFFS … #define QIB_7322_Scratch_DEF … #define QIB_7322_CntrRegBase_OFFS … #define QIB_7322_CntrRegBase_DEF … #define QIB_7322_SendRegBase_OFFS … #define QIB_7322_SendRegBase_DEF … #define QIB_7322_UserRegBase_OFFS … #define QIB_7322_UserRegBase_DEF … #define QIB_7322_IntMask_OFFS … #define QIB_7322_IntMask_DEF … #define QIB_7322_IntMask_SDmaIntMask_1_LSB … #define QIB_7322_IntMask_SDmaIntMask_1_MSB … #define QIB_7322_IntMask_SDmaIntMask_1_RMASK … #define QIB_7322_IntMask_SDmaIntMask_0_LSB … #define QIB_7322_IntMask_SDmaIntMask_0_MSB … #define QIB_7322_IntMask_SDmaIntMask_0_RMASK … #define QIB_7322_IntMask_SDmaProgressIntMask_1_LSB … #define QIB_7322_IntMask_SDmaProgressIntMask_1_MSB … #define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK … #define QIB_7322_IntMask_SDmaProgressIntMask_0_LSB … #define QIB_7322_IntMask_SDmaProgressIntMask_0_MSB … #define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK … #define QIB_7322_IntMask_SDmaIdleIntMask_1_LSB … #define QIB_7322_IntMask_SDmaIdleIntMask_1_MSB … #define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK … #define QIB_7322_IntMask_SDmaIdleIntMask_0_LSB … #define QIB_7322_IntMask_SDmaIdleIntMask_0_MSB … #define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK … #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_LSB … #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_MSB … #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK … #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_LSB … #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_MSB … #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK … #define QIB_7322_IntMask_RcvUrg17IntMask_LSB … #define QIB_7322_IntMask_RcvUrg17IntMask_MSB … #define QIB_7322_IntMask_RcvUrg17IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg16IntMask_LSB … #define QIB_7322_IntMask_RcvUrg16IntMask_MSB … #define QIB_7322_IntMask_RcvUrg16IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg15IntMask_LSB … #define QIB_7322_IntMask_RcvUrg15IntMask_MSB … #define QIB_7322_IntMask_RcvUrg15IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg14IntMask_LSB … #define QIB_7322_IntMask_RcvUrg14IntMask_MSB … #define QIB_7322_IntMask_RcvUrg14IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg13IntMask_LSB … #define QIB_7322_IntMask_RcvUrg13IntMask_MSB … #define QIB_7322_IntMask_RcvUrg13IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg12IntMask_LSB … #define QIB_7322_IntMask_RcvUrg12IntMask_MSB … #define QIB_7322_IntMask_RcvUrg12IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg11IntMask_LSB … #define QIB_7322_IntMask_RcvUrg11IntMask_MSB … #define QIB_7322_IntMask_RcvUrg11IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg10IntMask_LSB … #define QIB_7322_IntMask_RcvUrg10IntMask_MSB … #define QIB_7322_IntMask_RcvUrg10IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg9IntMask_LSB … #define QIB_7322_IntMask_RcvUrg9IntMask_MSB … #define QIB_7322_IntMask_RcvUrg9IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg8IntMask_LSB … #define QIB_7322_IntMask_RcvUrg8IntMask_MSB … #define QIB_7322_IntMask_RcvUrg8IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg7IntMask_LSB … #define QIB_7322_IntMask_RcvUrg7IntMask_MSB … #define QIB_7322_IntMask_RcvUrg7IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg6IntMask_LSB … #define QIB_7322_IntMask_RcvUrg6IntMask_MSB … #define QIB_7322_IntMask_RcvUrg6IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg5IntMask_LSB … #define QIB_7322_IntMask_RcvUrg5IntMask_MSB … #define QIB_7322_IntMask_RcvUrg5IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg4IntMask_LSB … #define QIB_7322_IntMask_RcvUrg4IntMask_MSB … #define QIB_7322_IntMask_RcvUrg4IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg3IntMask_LSB … #define QIB_7322_IntMask_RcvUrg3IntMask_MSB … #define QIB_7322_IntMask_RcvUrg3IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg2IntMask_LSB … #define QIB_7322_IntMask_RcvUrg2IntMask_MSB … #define QIB_7322_IntMask_RcvUrg2IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg1IntMask_LSB … #define QIB_7322_IntMask_RcvUrg1IntMask_MSB … #define QIB_7322_IntMask_RcvUrg1IntMask_RMASK … #define QIB_7322_IntMask_RcvUrg0IntMask_LSB … #define QIB_7322_IntMask_RcvUrg0IntMask_MSB … #define QIB_7322_IntMask_RcvUrg0IntMask_RMASK … #define QIB_7322_IntMask_ErrIntMask_1_LSB … #define QIB_7322_IntMask_ErrIntMask_1_MSB … #define QIB_7322_IntMask_ErrIntMask_1_RMASK … #define QIB_7322_IntMask_ErrIntMask_0_LSB … #define QIB_7322_IntMask_ErrIntMask_0_MSB … #define QIB_7322_IntMask_ErrIntMask_0_RMASK … #define QIB_7322_IntMask_ErrIntMask_LSB … #define QIB_7322_IntMask_ErrIntMask_MSB … #define QIB_7322_IntMask_ErrIntMask_RMASK … #define QIB_7322_IntMask_AssertGPIOIntMask_LSB … #define QIB_7322_IntMask_AssertGPIOIntMask_MSB … #define QIB_7322_IntMask_AssertGPIOIntMask_RMASK … #define QIB_7322_IntMask_SendDoneIntMask_1_LSB … #define QIB_7322_IntMask_SendDoneIntMask_1_MSB … #define QIB_7322_IntMask_SendDoneIntMask_1_RMASK … #define QIB_7322_IntMask_SendDoneIntMask_0_LSB … #define QIB_7322_IntMask_SendDoneIntMask_0_MSB … #define QIB_7322_IntMask_SendDoneIntMask_0_RMASK … #define QIB_7322_IntMask_SendBufAvailIntMask_LSB … #define QIB_7322_IntMask_SendBufAvailIntMask_MSB … #define QIB_7322_IntMask_SendBufAvailIntMask_RMASK … #define QIB_7322_IntMask_RcvAvail17IntMask_LSB … #define QIB_7322_IntMask_RcvAvail17IntMask_MSB … #define QIB_7322_IntMask_RcvAvail17IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail16IntMask_LSB … #define QIB_7322_IntMask_RcvAvail16IntMask_MSB … #define QIB_7322_IntMask_RcvAvail16IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail15IntMask_LSB … #define QIB_7322_IntMask_RcvAvail15IntMask_MSB … #define QIB_7322_IntMask_RcvAvail15IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail14IntMask_LSB … #define QIB_7322_IntMask_RcvAvail14IntMask_MSB … #define QIB_7322_IntMask_RcvAvail14IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail13IntMask_LSB … #define QIB_7322_IntMask_RcvAvail13IntMask_MSB … #define QIB_7322_IntMask_RcvAvail13IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail12IntMask_LSB … #define QIB_7322_IntMask_RcvAvail12IntMask_MSB … #define QIB_7322_IntMask_RcvAvail12IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail11IntMask_LSB … #define QIB_7322_IntMask_RcvAvail11IntMask_MSB … #define QIB_7322_IntMask_RcvAvail11IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail10IntMask_LSB … #define QIB_7322_IntMask_RcvAvail10IntMask_MSB … #define QIB_7322_IntMask_RcvAvail10IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail9IntMask_LSB … #define QIB_7322_IntMask_RcvAvail9IntMask_MSB … #define QIB_7322_IntMask_RcvAvail9IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail8IntMask_LSB … #define QIB_7322_IntMask_RcvAvail8IntMask_MSB … #define QIB_7322_IntMask_RcvAvail8IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail7IntMask_LSB … #define QIB_7322_IntMask_RcvAvail7IntMask_MSB … #define QIB_7322_IntMask_RcvAvail7IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail6IntMask_LSB … #define QIB_7322_IntMask_RcvAvail6IntMask_MSB … #define QIB_7322_IntMask_RcvAvail6IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail5IntMask_LSB … #define QIB_7322_IntMask_RcvAvail5IntMask_MSB … #define QIB_7322_IntMask_RcvAvail5IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail4IntMask_LSB … #define QIB_7322_IntMask_RcvAvail4IntMask_MSB … #define QIB_7322_IntMask_RcvAvail4IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail3IntMask_LSB … #define QIB_7322_IntMask_RcvAvail3IntMask_MSB … #define QIB_7322_IntMask_RcvAvail3IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail2IntMask_LSB … #define QIB_7322_IntMask_RcvAvail2IntMask_MSB … #define QIB_7322_IntMask_RcvAvail2IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail1IntMask_LSB … #define QIB_7322_IntMask_RcvAvail1IntMask_MSB … #define QIB_7322_IntMask_RcvAvail1IntMask_RMASK … #define QIB_7322_IntMask_RcvAvail0IntMask_LSB … #define QIB_7322_IntMask_RcvAvail0IntMask_MSB … #define QIB_7322_IntMask_RcvAvail0IntMask_RMASK … #define QIB_7322_IntStatus_OFFS … #define QIB_7322_IntStatus_DEF … #define QIB_7322_IntStatus_SDmaInt_1_LSB … #define QIB_7322_IntStatus_SDmaInt_1_MSB … #define QIB_7322_IntStatus_SDmaInt_1_RMASK … #define QIB_7322_IntStatus_SDmaInt_0_LSB … #define QIB_7322_IntStatus_SDmaInt_0_MSB … #define QIB_7322_IntStatus_SDmaInt_0_RMASK … #define QIB_7322_IntStatus_SDmaProgressInt_1_LSB … #define QIB_7322_IntStatus_SDmaProgressInt_1_MSB … #define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK … #define QIB_7322_IntStatus_SDmaProgressInt_0_LSB … #define QIB_7322_IntStatus_SDmaProgressInt_0_MSB … #define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK … #define QIB_7322_IntStatus_SDmaIdleInt_1_LSB … #define QIB_7322_IntStatus_SDmaIdleInt_1_MSB … #define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK … #define QIB_7322_IntStatus_SDmaIdleInt_0_LSB … #define QIB_7322_IntStatus_SDmaIdleInt_0_MSB … #define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK … #define QIB_7322_IntStatus_SDmaCleanupDone_1_LSB … #define QIB_7322_IntStatus_SDmaCleanupDone_1_MSB … #define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK … #define QIB_7322_IntStatus_SDmaCleanupDone_0_LSB … #define QIB_7322_IntStatus_SDmaCleanupDone_0_MSB … #define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK … #define QIB_7322_IntStatus_RcvUrg17_LSB … #define QIB_7322_IntStatus_RcvUrg17_MSB … #define QIB_7322_IntStatus_RcvUrg17_RMASK … #define QIB_7322_IntStatus_RcvUrg16_LSB … #define QIB_7322_IntStatus_RcvUrg16_MSB … #define QIB_7322_IntStatus_RcvUrg16_RMASK … #define QIB_7322_IntStatus_RcvUrg15_LSB … #define QIB_7322_IntStatus_RcvUrg15_MSB … #define QIB_7322_IntStatus_RcvUrg15_RMASK … #define QIB_7322_IntStatus_RcvUrg14_LSB … #define QIB_7322_IntStatus_RcvUrg14_MSB … #define QIB_7322_IntStatus_RcvUrg14_RMASK … #define QIB_7322_IntStatus_RcvUrg13_LSB … #define QIB_7322_IntStatus_RcvUrg13_MSB … #define QIB_7322_IntStatus_RcvUrg13_RMASK … #define QIB_7322_IntStatus_RcvUrg12_LSB … #define QIB_7322_IntStatus_RcvUrg12_MSB … #define QIB_7322_IntStatus_RcvUrg12_RMASK … #define QIB_7322_IntStatus_RcvUrg11_LSB … #define QIB_7322_IntStatus_RcvUrg11_MSB … #define QIB_7322_IntStatus_RcvUrg11_RMASK … #define QIB_7322_IntStatus_RcvUrg10_LSB … #define QIB_7322_IntStatus_RcvUrg10_MSB … #define QIB_7322_IntStatus_RcvUrg10_RMASK … #define QIB_7322_IntStatus_RcvUrg9_LSB … #define QIB_7322_IntStatus_RcvUrg9_MSB … #define QIB_7322_IntStatus_RcvUrg9_RMASK … #define QIB_7322_IntStatus_RcvUrg8_LSB … #define QIB_7322_IntStatus_RcvUrg8_MSB … #define QIB_7322_IntStatus_RcvUrg8_RMASK … #define QIB_7322_IntStatus_RcvUrg7_LSB … #define QIB_7322_IntStatus_RcvUrg7_MSB … #define QIB_7322_IntStatus_RcvUrg7_RMASK … #define QIB_7322_IntStatus_RcvUrg6_LSB … #define QIB_7322_IntStatus_RcvUrg6_MSB … #define QIB_7322_IntStatus_RcvUrg6_RMASK … #define QIB_7322_IntStatus_RcvUrg5_LSB … #define QIB_7322_IntStatus_RcvUrg5_MSB … #define QIB_7322_IntStatus_RcvUrg5_RMASK … #define QIB_7322_IntStatus_RcvUrg4_LSB … #define QIB_7322_IntStatus_RcvUrg4_MSB … #define QIB_7322_IntStatus_RcvUrg4_RMASK … #define QIB_7322_IntStatus_RcvUrg3_LSB … #define QIB_7322_IntStatus_RcvUrg3_MSB … #define QIB_7322_IntStatus_RcvUrg3_RMASK … #define QIB_7322_IntStatus_RcvUrg2_LSB … #define QIB_7322_IntStatus_RcvUrg2_MSB … #define QIB_7322_IntStatus_RcvUrg2_RMASK … #define QIB_7322_IntStatus_RcvUrg1_LSB … #define QIB_7322_IntStatus_RcvUrg1_MSB … #define QIB_7322_IntStatus_RcvUrg1_RMASK … #define QIB_7322_IntStatus_RcvUrg0_LSB … #define QIB_7322_IntStatus_RcvUrg0_MSB … #define QIB_7322_IntStatus_RcvUrg0_RMASK … #define QIB_7322_IntStatus_Err_1_LSB … #define QIB_7322_IntStatus_Err_1_MSB … #define QIB_7322_IntStatus_Err_1_RMASK … #define QIB_7322_IntStatus_Err_0_LSB … #define QIB_7322_IntStatus_Err_0_MSB … #define QIB_7322_IntStatus_Err_0_RMASK … #define QIB_7322_IntStatus_Err_LSB … #define QIB_7322_IntStatus_Err_MSB … #define QIB_7322_IntStatus_Err_RMASK … #define QIB_7322_IntStatus_AssertGPIO_LSB … #define QIB_7322_IntStatus_AssertGPIO_MSB … #define QIB_7322_IntStatus_AssertGPIO_RMASK … #define QIB_7322_IntStatus_SendDone_1_LSB … #define QIB_7322_IntStatus_SendDone_1_MSB … #define QIB_7322_IntStatus_SendDone_1_RMASK … #define QIB_7322_IntStatus_SendDone_0_LSB … #define QIB_7322_IntStatus_SendDone_0_MSB … #define QIB_7322_IntStatus_SendDone_0_RMASK … #define QIB_7322_IntStatus_SendBufAvail_LSB … #define QIB_7322_IntStatus_SendBufAvail_MSB … #define QIB_7322_IntStatus_SendBufAvail_RMASK … #define QIB_7322_IntStatus_RcvAvail17_LSB … #define QIB_7322_IntStatus_RcvAvail17_MSB … #define QIB_7322_IntStatus_RcvAvail17_RMASK … #define QIB_7322_IntStatus_RcvAvail16_LSB … #define QIB_7322_IntStatus_RcvAvail16_MSB … #define QIB_7322_IntStatus_RcvAvail16_RMASK … #define QIB_7322_IntStatus_RcvAvail15_LSB … #define QIB_7322_IntStatus_RcvAvail15_MSB … #define QIB_7322_IntStatus_RcvAvail15_RMASK … #define QIB_7322_IntStatus_RcvAvail14_LSB … #define QIB_7322_IntStatus_RcvAvail14_MSB … #define QIB_7322_IntStatus_RcvAvail14_RMASK … #define QIB_7322_IntStatus_RcvAvail13_LSB … #define QIB_7322_IntStatus_RcvAvail13_MSB … #define QIB_7322_IntStatus_RcvAvail13_RMASK … #define QIB_7322_IntStatus_RcvAvail12_LSB … #define QIB_7322_IntStatus_RcvAvail12_MSB … #define QIB_7322_IntStatus_RcvAvail12_RMASK … #define QIB_7322_IntStatus_RcvAvail11_LSB … #define QIB_7322_IntStatus_RcvAvail11_MSB … #define QIB_7322_IntStatus_RcvAvail11_RMASK … #define QIB_7322_IntStatus_RcvAvail10_LSB … #define QIB_7322_IntStatus_RcvAvail10_MSB … #define QIB_7322_IntStatus_RcvAvail10_RMASK … #define QIB_7322_IntStatus_RcvAvail9_LSB … #define QIB_7322_IntStatus_RcvAvail9_MSB … #define QIB_7322_IntStatus_RcvAvail9_RMASK … #define QIB_7322_IntStatus_RcvAvail8_LSB … #define QIB_7322_IntStatus_RcvAvail8_MSB … #define QIB_7322_IntStatus_RcvAvail8_RMASK … #define QIB_7322_IntStatus_RcvAvail7_LSB … #define QIB_7322_IntStatus_RcvAvail7_MSB … #define QIB_7322_IntStatus_RcvAvail7_RMASK … #define QIB_7322_IntStatus_RcvAvail6_LSB … #define QIB_7322_IntStatus_RcvAvail6_MSB … #define QIB_7322_IntStatus_RcvAvail6_RMASK … #define QIB_7322_IntStatus_RcvAvail5_LSB … #define QIB_7322_IntStatus_RcvAvail5_MSB … #define QIB_7322_IntStatus_RcvAvail5_RMASK … #define QIB_7322_IntStatus_RcvAvail4_LSB … #define QIB_7322_IntStatus_RcvAvail4_MSB … #define QIB_7322_IntStatus_RcvAvail4_RMASK … #define QIB_7322_IntStatus_RcvAvail3_LSB … #define QIB_7322_IntStatus_RcvAvail3_MSB … #define QIB_7322_IntStatus_RcvAvail3_RMASK … #define QIB_7322_IntStatus_RcvAvail2_LSB … #define QIB_7322_IntStatus_RcvAvail2_MSB … #define QIB_7322_IntStatus_RcvAvail2_RMASK … #define QIB_7322_IntStatus_RcvAvail1_LSB … #define QIB_7322_IntStatus_RcvAvail1_MSB … #define QIB_7322_IntStatus_RcvAvail1_RMASK … #define QIB_7322_IntStatus_RcvAvail0_LSB … #define QIB_7322_IntStatus_RcvAvail0_MSB … #define QIB_7322_IntStatus_RcvAvail0_RMASK … #define QIB_7322_IntClear_OFFS … #define QIB_7322_IntClear_DEF … #define QIB_7322_IntClear_SDmaIntClear_1_LSB … #define QIB_7322_IntClear_SDmaIntClear_1_MSB … #define QIB_7322_IntClear_SDmaIntClear_1_RMASK … #define QIB_7322_IntClear_SDmaIntClear_0_LSB … #define QIB_7322_IntClear_SDmaIntClear_0_MSB … #define QIB_7322_IntClear_SDmaIntClear_0_RMASK … #define QIB_7322_IntClear_SDmaProgressIntClear_1_LSB … #define QIB_7322_IntClear_SDmaProgressIntClear_1_MSB … #define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK … #define QIB_7322_IntClear_SDmaProgressIntClear_0_LSB … #define QIB_7322_IntClear_SDmaProgressIntClear_0_MSB … #define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK … #define QIB_7322_IntClear_SDmaIdleIntClear_1_LSB … #define QIB_7322_IntClear_SDmaIdleIntClear_1_MSB … #define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK … #define QIB_7322_IntClear_SDmaIdleIntClear_0_LSB … #define QIB_7322_IntClear_SDmaIdleIntClear_0_MSB … #define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK … #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_LSB … #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_MSB … #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK … #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_LSB … #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_MSB … #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK … #define QIB_7322_IntClear_RcvUrg17IntClear_LSB … #define QIB_7322_IntClear_RcvUrg17IntClear_MSB … #define QIB_7322_IntClear_RcvUrg17IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg16IntClear_LSB … #define QIB_7322_IntClear_RcvUrg16IntClear_MSB … #define QIB_7322_IntClear_RcvUrg16IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg15IntClear_LSB … #define QIB_7322_IntClear_RcvUrg15IntClear_MSB … #define QIB_7322_IntClear_RcvUrg15IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg14IntClear_LSB … #define QIB_7322_IntClear_RcvUrg14IntClear_MSB … #define QIB_7322_IntClear_RcvUrg14IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg13IntClear_LSB … #define QIB_7322_IntClear_RcvUrg13IntClear_MSB … #define QIB_7322_IntClear_RcvUrg13IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg12IntClear_LSB … #define QIB_7322_IntClear_RcvUrg12IntClear_MSB … #define QIB_7322_IntClear_RcvUrg12IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg11IntClear_LSB … #define QIB_7322_IntClear_RcvUrg11IntClear_MSB … #define QIB_7322_IntClear_RcvUrg11IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg10IntClear_LSB … #define QIB_7322_IntClear_RcvUrg10IntClear_MSB … #define QIB_7322_IntClear_RcvUrg10IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg9IntClear_LSB … #define QIB_7322_IntClear_RcvUrg9IntClear_MSB … #define QIB_7322_IntClear_RcvUrg9IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg8IntClear_LSB … #define QIB_7322_IntClear_RcvUrg8IntClear_MSB … #define QIB_7322_IntClear_RcvUrg8IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg7IntClear_LSB … #define QIB_7322_IntClear_RcvUrg7IntClear_MSB … #define QIB_7322_IntClear_RcvUrg7IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg6IntClear_LSB … #define QIB_7322_IntClear_RcvUrg6IntClear_MSB … #define QIB_7322_IntClear_RcvUrg6IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg5IntClear_LSB … #define QIB_7322_IntClear_RcvUrg5IntClear_MSB … #define QIB_7322_IntClear_RcvUrg5IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg4IntClear_LSB … #define QIB_7322_IntClear_RcvUrg4IntClear_MSB … #define QIB_7322_IntClear_RcvUrg4IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg3IntClear_LSB … #define QIB_7322_IntClear_RcvUrg3IntClear_MSB … #define QIB_7322_IntClear_RcvUrg3IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg2IntClear_LSB … #define QIB_7322_IntClear_RcvUrg2IntClear_MSB … #define QIB_7322_IntClear_RcvUrg2IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg1IntClear_LSB … #define QIB_7322_IntClear_RcvUrg1IntClear_MSB … #define QIB_7322_IntClear_RcvUrg1IntClear_RMASK … #define QIB_7322_IntClear_RcvUrg0IntClear_LSB … #define QIB_7322_IntClear_RcvUrg0IntClear_MSB … #define QIB_7322_IntClear_RcvUrg0IntClear_RMASK … #define QIB_7322_IntClear_ErrIntClear_1_LSB … #define QIB_7322_IntClear_ErrIntClear_1_MSB … #define QIB_7322_IntClear_ErrIntClear_1_RMASK … #define QIB_7322_IntClear_ErrIntClear_0_LSB … #define QIB_7322_IntClear_ErrIntClear_0_MSB … #define QIB_7322_IntClear_ErrIntClear_0_RMASK … #define QIB_7322_IntClear_ErrIntClear_LSB … #define QIB_7322_IntClear_ErrIntClear_MSB … #define QIB_7322_IntClear_ErrIntClear_RMASK … #define QIB_7322_IntClear_AssertGPIOIntClear_LSB … #define QIB_7322_IntClear_AssertGPIOIntClear_MSB … #define QIB_7322_IntClear_AssertGPIOIntClear_RMASK … #define QIB_7322_IntClear_SendDoneIntClear_1_LSB … #define QIB_7322_IntClear_SendDoneIntClear_1_MSB … #define QIB_7322_IntClear_SendDoneIntClear_1_RMASK … #define QIB_7322_IntClear_SendDoneIntClear_0_LSB … #define QIB_7322_IntClear_SendDoneIntClear_0_MSB … #define QIB_7322_IntClear_SendDoneIntClear_0_RMASK … #define QIB_7322_IntClear_SendBufAvailIntClear_LSB … #define QIB_7322_IntClear_SendBufAvailIntClear_MSB … #define QIB_7322_IntClear_SendBufAvailIntClear_RMASK … #define QIB_7322_IntClear_RcvAvail17IntClear_LSB … #define QIB_7322_IntClear_RcvAvail17IntClear_MSB … #define QIB_7322_IntClear_RcvAvail17IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail16IntClear_LSB … #define QIB_7322_IntClear_RcvAvail16IntClear_MSB … #define QIB_7322_IntClear_RcvAvail16IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail15IntClear_LSB … #define QIB_7322_IntClear_RcvAvail15IntClear_MSB … #define QIB_7322_IntClear_RcvAvail15IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail14IntClear_LSB … #define QIB_7322_IntClear_RcvAvail14IntClear_MSB … #define QIB_7322_IntClear_RcvAvail14IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail13IntClear_LSB … #define QIB_7322_IntClear_RcvAvail13IntClear_MSB … #define QIB_7322_IntClear_RcvAvail13IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail12IntClear_LSB … #define QIB_7322_IntClear_RcvAvail12IntClear_MSB … #define QIB_7322_IntClear_RcvAvail12IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail11IntClear_LSB … #define QIB_7322_IntClear_RcvAvail11IntClear_MSB … #define QIB_7322_IntClear_RcvAvail11IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail10IntClear_LSB … #define QIB_7322_IntClear_RcvAvail10IntClear_MSB … #define QIB_7322_IntClear_RcvAvail10IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail9IntClear_LSB … #define QIB_7322_IntClear_RcvAvail9IntClear_MSB … #define QIB_7322_IntClear_RcvAvail9IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail8IntClear_LSB … #define QIB_7322_IntClear_RcvAvail8IntClear_MSB … #define QIB_7322_IntClear_RcvAvail8IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail7IntClear_LSB … #define QIB_7322_IntClear_RcvAvail7IntClear_MSB … #define QIB_7322_IntClear_RcvAvail7IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail6IntClear_LSB … #define QIB_7322_IntClear_RcvAvail6IntClear_MSB … #define QIB_7322_IntClear_RcvAvail6IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail5IntClear_LSB … #define QIB_7322_IntClear_RcvAvail5IntClear_MSB … #define QIB_7322_IntClear_RcvAvail5IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail4IntClear_LSB … #define QIB_7322_IntClear_RcvAvail4IntClear_MSB … #define QIB_7322_IntClear_RcvAvail4IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail3IntClear_LSB … #define QIB_7322_IntClear_RcvAvail3IntClear_MSB … #define QIB_7322_IntClear_RcvAvail3IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail2IntClear_LSB … #define QIB_7322_IntClear_RcvAvail2IntClear_MSB … #define QIB_7322_IntClear_RcvAvail2IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail1IntClear_LSB … #define QIB_7322_IntClear_RcvAvail1IntClear_MSB … #define QIB_7322_IntClear_RcvAvail1IntClear_RMASK … #define QIB_7322_IntClear_RcvAvail0IntClear_LSB … #define QIB_7322_IntClear_RcvAvail0IntClear_MSB … #define QIB_7322_IntClear_RcvAvail0IntClear_RMASK … #define QIB_7322_ErrMask_OFFS … #define QIB_7322_ErrMask_DEF … #define QIB_7322_ErrMask_ResetNegatedMask_LSB … #define QIB_7322_ErrMask_ResetNegatedMask_MSB … #define QIB_7322_ErrMask_ResetNegatedMask_RMASK … #define QIB_7322_ErrMask_HardwareErrMask_LSB … #define QIB_7322_ErrMask_HardwareErrMask_MSB … #define QIB_7322_ErrMask_HardwareErrMask_RMASK … #define QIB_7322_ErrMask_InvalidAddrErrMask_LSB … #define QIB_7322_ErrMask_InvalidAddrErrMask_MSB … #define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK … #define QIB_7322_ErrMask_SDmaVL15ErrMask_LSB … #define QIB_7322_ErrMask_SDmaVL15ErrMask_MSB … #define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK … #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_LSB … #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_MSB … #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK … #define QIB_7322_ErrMask_InvalidEEPCmdMask_LSB … #define QIB_7322_ErrMask_InvalidEEPCmdMask_MSB … #define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK … #define QIB_7322_ErrMask_RcvContextShareErrMask_LSB … #define QIB_7322_ErrMask_RcvContextShareErrMask_MSB … #define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK … #define QIB_7322_ErrMask_SendVLMismatchErrMask_LSB … #define QIB_7322_ErrMask_SendVLMismatchErrMask_MSB … #define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK … #define QIB_7322_ErrMask_SendArmLaunchErrMask_LSB … #define QIB_7322_ErrMask_SendArmLaunchErrMask_MSB … #define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK … #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_LSB … #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_MSB … #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK … #define QIB_7322_ErrMask_SDmaWrongPortErrMask_LSB … #define QIB_7322_ErrMask_SDmaWrongPortErrMask_MSB … #define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK … #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_LSB … #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_MSB … #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK … #define QIB_7322_ErrMask_RcvHdrFullErrMask_LSB … #define QIB_7322_ErrMask_RcvHdrFullErrMask_MSB … #define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK … #define QIB_7322_ErrMask_RcvEgrFullErrMask_LSB … #define QIB_7322_ErrMask_RcvEgrFullErrMask_MSB … #define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK … #define QIB_7322_ErrStatus_OFFS … #define QIB_7322_ErrStatus_DEF … #define QIB_7322_ErrStatus_ResetNegated_LSB … #define QIB_7322_ErrStatus_ResetNegated_MSB … #define QIB_7322_ErrStatus_ResetNegated_RMASK … #define QIB_7322_ErrStatus_HardwareErr_LSB … #define QIB_7322_ErrStatus_HardwareErr_MSB … #define QIB_7322_ErrStatus_HardwareErr_RMASK … #define QIB_7322_ErrStatus_InvalidAddrErr_LSB … #define QIB_7322_ErrStatus_InvalidAddrErr_MSB … #define QIB_7322_ErrStatus_InvalidAddrErr_RMASK … #define QIB_7322_ErrStatus_SDmaVL15Err_LSB … #define QIB_7322_ErrStatus_SDmaVL15Err_MSB … #define QIB_7322_ErrStatus_SDmaVL15Err_RMASK … #define QIB_7322_ErrStatus_SBufVL15MisUseErr_LSB … #define QIB_7322_ErrStatus_SBufVL15MisUseErr_MSB … #define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK … #define QIB_7322_ErrStatus_InvalidEEPCmdErr_LSB … #define QIB_7322_ErrStatus_InvalidEEPCmdErr_MSB … #define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK … #define QIB_7322_ErrStatus_RcvContextShareErr_LSB … #define QIB_7322_ErrStatus_RcvContextShareErr_MSB … #define QIB_7322_ErrStatus_RcvContextShareErr_RMASK … #define QIB_7322_ErrStatus_SendVLMismatchErr_LSB … #define QIB_7322_ErrStatus_SendVLMismatchErr_MSB … #define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK … #define QIB_7322_ErrStatus_SendArmLaunchErr_LSB … #define QIB_7322_ErrStatus_SendArmLaunchErr_MSB … #define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK … #define QIB_7322_ErrStatus_SendSpecialTriggerErr_LSB … #define QIB_7322_ErrStatus_SendSpecialTriggerErr_MSB … #define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK … #define QIB_7322_ErrStatus_SDmaWrongPortErr_LSB … #define QIB_7322_ErrStatus_SDmaWrongPortErr_MSB … #define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK … #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_LSB … #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_MSB … #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK … #define QIB_7322_ErrStatus_RcvHdrFullErr_LSB … #define QIB_7322_ErrStatus_RcvHdrFullErr_MSB … #define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK … #define QIB_7322_ErrStatus_RcvEgrFullErr_LSB … #define QIB_7322_ErrStatus_RcvEgrFullErr_MSB … #define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK … #define QIB_7322_ErrClear_OFFS … #define QIB_7322_ErrClear_DEF … #define QIB_7322_ErrClear_ResetNegatedClear_LSB … #define QIB_7322_ErrClear_ResetNegatedClear_MSB … #define QIB_7322_ErrClear_ResetNegatedClear_RMASK … #define QIB_7322_ErrClear_HardwareErrClear_LSB … #define QIB_7322_ErrClear_HardwareErrClear_MSB … #define QIB_7322_ErrClear_HardwareErrClear_RMASK … #define QIB_7322_ErrClear_InvalidAddrErrClear_LSB … #define QIB_7322_ErrClear_InvalidAddrErrClear_MSB … #define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK … #define QIB_7322_ErrClear_SDmaVL15ErrClear_LSB … #define QIB_7322_ErrClear_SDmaVL15ErrClear_MSB … #define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK … #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_LSB … #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_MSB … #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK … #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_LSB … #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_MSB … #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK … #define QIB_7322_ErrClear_RcvContextShareErrClear_LSB … #define QIB_7322_ErrClear_RcvContextShareErrClear_MSB … #define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK … #define QIB_7322_ErrClear_SendVLMismatchErrMask_LSB … #define QIB_7322_ErrClear_SendVLMismatchErrMask_MSB … #define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK … #define QIB_7322_ErrClear_SendArmLaunchErrClear_LSB … #define QIB_7322_ErrClear_SendArmLaunchErrClear_MSB … #define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK … #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_LSB … #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_MSB … #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK … #define QIB_7322_ErrClear_SDmaWrongPortErrClear_LSB … #define QIB_7322_ErrClear_SDmaWrongPortErrClear_MSB … #define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK … #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_LSB … #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_MSB … #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK … #define QIB_7322_ErrClear_RcvHdrFullErrClear_LSB … #define QIB_7322_ErrClear_RcvHdrFullErrClear_MSB … #define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK … #define QIB_7322_ErrClear_RcvEgrFullErrClear_LSB … #define QIB_7322_ErrClear_RcvEgrFullErrClear_MSB … #define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK … #define QIB_7322_HwErrMask_OFFS … #define QIB_7322_HwErrMask_DEF … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_LSB … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_MSB … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_LSB … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_MSB … #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK … #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_LSB … #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_MSB … #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK … #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_LSB … #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_MSB … #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK … #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_LSB … #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_MSB … #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK … #define QIB_7322_HwErrMask_MemoryErrMask_LSB … #define QIB_7322_HwErrMask_MemoryErrMask_MSB … #define QIB_7322_HwErrMask_MemoryErrMask_RMASK … #define QIB_7322_HwErrMask_pcie_phy_txParityErr_LSB … #define QIB_7322_HwErrMask_pcie_phy_txParityErr_MSB … #define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK … #define QIB_7322_HwErrMask_PCIeBusParityErrMask_LSB … #define QIB_7322_HwErrMask_PCIeBusParityErrMask_MSB … #define QIB_7322_HwErrMask_PCIeBusParityErrMask_RMASK … #define QIB_7322_HwErrMask_PcieCplTimeoutMask_LSB … #define QIB_7322_HwErrMask_PcieCplTimeoutMask_MSB … #define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK … #define QIB_7322_HwErrMask_PciePoisonedTLPMask_LSB … #define QIB_7322_HwErrMask_PciePoisonedTLPMask_MSB … #define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_LSB … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_MSB … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_LSB … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_MSB … #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_LSB … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_MSB … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK … #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_LSB … #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_MSB … #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_RMASK … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_LSB … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_MSB … #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK … #define QIB_7322_HwErrMask_statusValidNoEopMask_LSB … #define QIB_7322_HwErrMask_statusValidNoEopMask_MSB … #define QIB_7322_HwErrMask_statusValidNoEopMask_RMASK … #define QIB_7322_HwErrMask_LATriggeredMask_LSB … #define QIB_7322_HwErrMask_LATriggeredMask_MSB … #define QIB_7322_HwErrMask_LATriggeredMask_RMASK … #define QIB_7322_HwErrStatus_OFFS … #define QIB_7322_HwErrStatus_DEF … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_LSB … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_MSB … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_LSB … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_MSB … #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK … #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_LSB … #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_MSB … #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK … #define QIB_7322_HwErrStatus_PowerOnBISTFailed_LSB … #define QIB_7322_HwErrStatus_PowerOnBISTFailed_MSB … #define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK … #define QIB_7322_HwErrStatus_TempsenseTholdReached_LSB … #define QIB_7322_HwErrStatus_TempsenseTholdReached_MSB … #define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK … #define QIB_7322_HwErrStatus_MemoryErr_LSB … #define QIB_7322_HwErrStatus_MemoryErr_MSB … #define QIB_7322_HwErrStatus_MemoryErr_RMASK … #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_LSB … #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_MSB … #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK … #define QIB_7322_HwErrStatus_PCIeBusParity_LSB … #define QIB_7322_HwErrStatus_PCIeBusParity_MSB … #define QIB_7322_HwErrStatus_PCIeBusParity_RMASK … #define QIB_7322_HwErrStatus_PcieCplTimeout_LSB … #define QIB_7322_HwErrStatus_PcieCplTimeout_MSB … #define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK … #define QIB_7322_HwErrStatus_PciePoisonedTLP_LSB … #define QIB_7322_HwErrStatus_PciePoisonedTLP_MSB … #define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK … #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_LSB … #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_MSB … #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK … #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_LSB … #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_MSB … #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_LSB … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_MSB … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK … #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_LSB … #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_MSB … #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_RMASK … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_LSB … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_MSB … #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK … #define QIB_7322_HwErrStatus_statusValidNoEop_LSB … #define QIB_7322_HwErrStatus_statusValidNoEop_MSB … #define QIB_7322_HwErrStatus_statusValidNoEop_RMASK … #define QIB_7322_HwErrStatus_LATriggered_LSB … #define QIB_7322_HwErrStatus_LATriggered_MSB … #define QIB_7322_HwErrStatus_LATriggered_RMASK … #define QIB_7322_HwErrClear_OFFS … #define QIB_7322_HwErrClear_DEF … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_LSB … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_MSB … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_LSB … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_MSB … #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK … #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_LSB … #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_MSB … #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK … #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_LSB … #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_MSB … #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK … #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_LSB … #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_MSB … #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK … #define QIB_7322_HwErrClear_MemoryErrClear_LSB … #define QIB_7322_HwErrClear_MemoryErrClear_MSB … #define QIB_7322_HwErrClear_MemoryErrClear_RMASK … #define QIB_7322_HwErrClear_pcie_phy_txParityErr_LSB … #define QIB_7322_HwErrClear_pcie_phy_txParityErr_MSB … #define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK … #define QIB_7322_HwErrClear_PCIeBusParityClear_LSB … #define QIB_7322_HwErrClear_PCIeBusParityClear_MSB … #define QIB_7322_HwErrClear_PCIeBusParityClear_RMASK … #define QIB_7322_HwErrClear_PcieCplTimeoutClear_LSB … #define QIB_7322_HwErrClear_PcieCplTimeoutClear_MSB … #define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK … #define QIB_7322_HwErrClear_PciePoisonedTLPClear_LSB … #define QIB_7322_HwErrClear_PciePoisonedTLPClear_MSB … #define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_LSB … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_MSB … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_LSB … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_MSB … #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_LSB … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_MSB … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK … #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_LSB … #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_MSB … #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_RMASK … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_LSB … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_MSB … #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK … #define QIB_7322_HwErrClear_statusValidNoEopClear_LSB … #define QIB_7322_HwErrClear_statusValidNoEopClear_MSB … #define QIB_7322_HwErrClear_statusValidNoEopClear_RMASK … #define QIB_7322_HwErrClear_LATriggeredClear_LSB … #define QIB_7322_HwErrClear_LATriggeredClear_MSB … #define QIB_7322_HwErrClear_LATriggeredClear_RMASK … #define QIB_7322_HwDiagCtrl_OFFS … #define QIB_7322_HwDiagCtrl_DEF … #define QIB_7322_HwDiagCtrl_Diagnostic_LSB … #define QIB_7322_HwDiagCtrl_Diagnostic_MSB … #define QIB_7322_HwDiagCtrl_Diagnostic_RMASK … #define QIB_7322_HwDiagCtrl_CounterWrEnable_LSB … #define QIB_7322_HwDiagCtrl_CounterWrEnable_MSB … #define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK … #define QIB_7322_HwDiagCtrl_CounterDisable_LSB … #define QIB_7322_HwDiagCtrl_CounterDisable_MSB … #define QIB_7322_HwDiagCtrl_CounterDisable_RMASK … #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_LSB … #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_MSB … #define QIB_7322_HwDiagCtrl_forcePCIeBusParity_RMASK … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_LSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_MSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_LSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_MSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_RMASK … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_LSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_MSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_LSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_MSB … #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_RMASK … #define QIB_7322_EXTStatus_OFFS … #define QIB_7322_EXTStatus_DEF … #define QIB_7322_EXTStatus_GPIOIn_LSB … #define QIB_7322_EXTStatus_GPIOIn_MSB … #define QIB_7322_EXTStatus_GPIOIn_RMASK … #define QIB_7322_EXTStatus_MemBISTDisabled_LSB … #define QIB_7322_EXTStatus_MemBISTDisabled_MSB … #define QIB_7322_EXTStatus_MemBISTDisabled_RMASK … #define QIB_7322_EXTStatus_MemBISTEndTest_LSB … #define QIB_7322_EXTStatus_MemBISTEndTest_MSB … #define QIB_7322_EXTStatus_MemBISTEndTest_RMASK … #define QIB_7322_EXTCtrl_OFFS … #define QIB_7322_EXTCtrl_DEF … #define QIB_7322_EXTCtrl_GPIOOe_LSB … #define QIB_7322_EXTCtrl_GPIOOe_MSB … #define QIB_7322_EXTCtrl_GPIOOe_RMASK … #define QIB_7322_EXTCtrl_GPIOInvert_LSB … #define QIB_7322_EXTCtrl_GPIOInvert_MSB … #define QIB_7322_EXTCtrl_GPIOInvert_RMASK … #define QIB_7322_EXTCtrl_LEDPort1GreenOn_LSB … #define QIB_7322_EXTCtrl_LEDPort1GreenOn_MSB … #define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK … #define QIB_7322_EXTCtrl_LEDPort1YellowOn_LSB … #define QIB_7322_EXTCtrl_LEDPort1YellowOn_MSB … #define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK … #define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB … #define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB … #define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK … #define QIB_7322_EXTCtrl_LEDPort0YellowOn_LSB … #define QIB_7322_EXTCtrl_LEDPort0YellowOn_MSB … #define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK … #define QIB_7322_GPIOOut_OFFS … #define QIB_7322_GPIOOut_DEF … #define QIB_7322_GPIOMask_OFFS … #define QIB_7322_GPIOMask_DEF … #define QIB_7322_GPIOStatus_OFFS … #define QIB_7322_GPIOStatus_DEF … #define QIB_7322_GPIOClear_OFFS … #define QIB_7322_GPIOClear_DEF … #define QIB_7322_RcvCtrl_OFFS … #define QIB_7322_RcvCtrl_DEF … #define QIB_7322_RcvCtrl_TidReDirect_LSB … #define QIB_7322_RcvCtrl_TidReDirect_MSB … #define QIB_7322_RcvCtrl_TidReDirect_RMASK … #define QIB_7322_RcvCtrl_TailUpd_LSB … #define QIB_7322_RcvCtrl_TailUpd_MSB … #define QIB_7322_RcvCtrl_TailUpd_RMASK … #define QIB_7322_RcvCtrl_XrcTypeCode_LSB … #define QIB_7322_RcvCtrl_XrcTypeCode_MSB … #define QIB_7322_RcvCtrl_XrcTypeCode_RMASK … #define QIB_7322_RcvCtrl_TidFlowEnable_LSB … #define QIB_7322_RcvCtrl_TidFlowEnable_MSB … #define QIB_7322_RcvCtrl_TidFlowEnable_RMASK … #define QIB_7322_RcvCtrl_ContextCfg_LSB … #define QIB_7322_RcvCtrl_ContextCfg_MSB … #define QIB_7322_RcvCtrl_ContextCfg_RMASK … #define QIB_7322_RcvCtrl_IntrAvail_LSB … #define QIB_7322_RcvCtrl_IntrAvail_MSB … #define QIB_7322_RcvCtrl_IntrAvail_RMASK … #define QIB_7322_RcvCtrl_dontDropRHQFull_LSB … #define QIB_7322_RcvCtrl_dontDropRHQFull_MSB … #define QIB_7322_RcvCtrl_dontDropRHQFull_RMASK … #define QIB_7322_RcvHdrSize_OFFS … #define QIB_7322_RcvHdrSize_DEF … #define QIB_7322_RcvHdrCnt_OFFS … #define QIB_7322_RcvHdrCnt_DEF … #define QIB_7322_RcvHdrEntSize_OFFS … #define QIB_7322_RcvHdrEntSize_DEF … #define QIB_7322_RcvTIDBase_OFFS … #define QIB_7322_RcvTIDBase_DEF … #define QIB_7322_RcvTIDCnt_OFFS … #define QIB_7322_RcvTIDCnt_DEF … #define QIB_7322_RcvEgrBase_OFFS … #define QIB_7322_RcvEgrBase_DEF … #define QIB_7322_RcvEgrCnt_OFFS … #define QIB_7322_RcvEgrCnt_DEF … #define QIB_7322_RcvBufBase_OFFS … #define QIB_7322_RcvBufBase_DEF … #define QIB_7322_RcvBufSize_OFFS … #define QIB_7322_RcvBufSize_DEF … #define QIB_7322_RxIntMemBase_OFFS … #define QIB_7322_RxIntMemBase_DEF … #define QIB_7322_RxIntMemSize_OFFS … #define QIB_7322_RxIntMemSize_DEF … #define QIB_7322_feature_mask_OFFS … #define QIB_7322_feature_mask_DEF … #define QIB_7322_active_feature_mask_OFFS … #define QIB_7322_active_feature_mask_DEF … #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK … #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK … #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK … #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK … #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK … #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_LSB … #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_MSB … #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK … #define QIB_7322_SendCtrl_OFFS … #define QIB_7322_SendCtrl_DEF … #define QIB_7322_SendCtrl_Disarm_LSB … #define QIB_7322_SendCtrl_Disarm_MSB … #define QIB_7322_SendCtrl_Disarm_RMASK … #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_LSB … #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_MSB … #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK … #define QIB_7322_SendCtrl_AvailUpdThld_LSB … #define QIB_7322_SendCtrl_AvailUpdThld_MSB … #define QIB_7322_SendCtrl_AvailUpdThld_RMASK … #define QIB_7322_SendCtrl_DisarmSendBuf_LSB … #define QIB_7322_SendCtrl_DisarmSendBuf_MSB … #define QIB_7322_SendCtrl_DisarmSendBuf_RMASK … #define QIB_7322_SendCtrl_SpecialTriggerEn_LSB … #define QIB_7322_SendCtrl_SpecialTriggerEn_MSB … #define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK … #define QIB_7322_SendCtrl_SendBufAvailUpd_LSB … #define QIB_7322_SendCtrl_SendBufAvailUpd_MSB … #define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK … #define QIB_7322_SendCtrl_SendIntBufAvail_LSB … #define QIB_7322_SendCtrl_SendIntBufAvail_MSB … #define QIB_7322_SendCtrl_SendIntBufAvail_RMASK … #define QIB_7322_SendBufBase_OFFS … #define QIB_7322_SendBufBase_DEF … #define QIB_7322_SendBufBase_BaseAddr_LargePIO_LSB … #define QIB_7322_SendBufBase_BaseAddr_LargePIO_MSB … #define QIB_7322_SendBufBase_BaseAddr_LargePIO_RMASK … #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_LSB … #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_MSB … #define QIB_7322_SendBufBase_BaseAddr_SmallPIO_RMASK … #define QIB_7322_SendBufSize_OFFS … #define QIB_7322_SendBufSize_DEF … #define QIB_7322_SendBufSize_Size_LargePIO_LSB … #define QIB_7322_SendBufSize_Size_LargePIO_MSB … #define QIB_7322_SendBufSize_Size_LargePIO_RMASK … #define QIB_7322_SendBufSize_Size_SmallPIO_LSB … #define QIB_7322_SendBufSize_Size_SmallPIO_MSB … #define QIB_7322_SendBufSize_Size_SmallPIO_RMASK … #define QIB_7322_SendBufCnt_OFFS … #define QIB_7322_SendBufCnt_DEF … #define QIB_7322_SendBufCnt_Num_LargeBuffers_LSB … #define QIB_7322_SendBufCnt_Num_LargeBuffers_MSB … #define QIB_7322_SendBufCnt_Num_LargeBuffers_RMASK … #define QIB_7322_SendBufCnt_Num_SmallBuffers_LSB … #define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB … #define QIB_7322_SendBufCnt_Num_SmallBuffers_RMASK … #define QIB_7322_SendBufAvailAddr_OFFS … #define QIB_7322_SendBufAvailAddr_DEF … #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_LSB … #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_MSB … #define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_RMASK … #define QIB_7322_SendBufErr0_OFFS … #define QIB_7322_SendBufErr0_DEF … #define QIB_7322_SendBufErr0_SendBufErr_63_0_LSB … #define QIB_7322_SendBufErr0_SendBufErr_63_0_MSB … #define QIB_7322_SendBufErr0_SendBufErr_63_0_RMASK … #define QIB_7322_AvailUpdCount_OFFS … #define QIB_7322_AvailUpdCount_DEF … #define QIB_7322_AvailUpdCount_AvailUpdCount_LSB … #define QIB_7322_AvailUpdCount_AvailUpdCount_MSB … #define QIB_7322_AvailUpdCount_AvailUpdCount_RMASK … #define QIB_7322_RcvHdrAddr0_OFFS … #define QIB_7322_RcvHdrAddr0_DEF … #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_LSB … #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_MSB … #define QIB_7322_RcvHdrAddr0_RcvHdrAddr_RMASK … #define QIB_7322_RcvHdrTailAddr0_OFFS … #define QIB_7322_RcvHdrTailAddr0_DEF … #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_LSB … #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_MSB … #define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_RMASK … #define QIB_7322_ahb_access_ctrl_OFFS … #define QIB_7322_ahb_access_ctrl_DEF … #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB … #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_MSB … #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_RMASK … #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_LSB … #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_MSB … #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK … #define QIB_7322_ahb_transaction_reg_OFFS … #define QIB_7322_ahb_transaction_reg_DEF … #define QIB_7322_ahb_transaction_reg_ahb_data_LSB … #define QIB_7322_ahb_transaction_reg_ahb_data_MSB … #define QIB_7322_ahb_transaction_reg_ahb_data_RMASK … #define QIB_7322_ahb_transaction_reg_ahb_rdy_LSB … #define QIB_7322_ahb_transaction_reg_ahb_rdy_MSB … #define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK … #define QIB_7322_ahb_transaction_reg_ahb_req_err_LSB … #define QIB_7322_ahb_transaction_reg_ahb_req_err_MSB … #define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK … #define QIB_7322_ahb_transaction_reg_write_not_read_LSB … #define QIB_7322_ahb_transaction_reg_write_not_read_MSB … #define QIB_7322_ahb_transaction_reg_write_not_read_RMASK … #define QIB_7322_ahb_transaction_reg_ahb_address_LSB … #define QIB_7322_ahb_transaction_reg_ahb_address_MSB … #define QIB_7322_ahb_transaction_reg_ahb_address_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_OFFS … #define QIB_7322_SPC_JTAG_ACCESS_REG_DEF … #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK … #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_LSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_MSB … #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK … #define QIB_7322_SendCheckMask0_OFFS … #define QIB_7322_SendCheckMask0_DEF … #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_LSB … #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_MSB … #define QIB_7322_SendCheckMask0_SendCheckMask_63_32_RMASK … #define QIB_7322_SendGRHCheckMask0_OFFS … #define QIB_7322_SendGRHCheckMask0_DEF … #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_LSB … #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_MSB … #define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_RMASK … #define QIB_7322_SendIBPacketMask0_OFFS … #define QIB_7322_SendIBPacketMask0_DEF … #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_LSB … #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_MSB … #define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_RMASK … #define QIB_7322_IntRedirect0_OFFS … #define QIB_7322_IntRedirect0_DEF … #define QIB_7322_IntRedirect0_vec11_LSB … #define QIB_7322_IntRedirect0_vec11_MSB … #define QIB_7322_IntRedirect0_vec11_RMASK … #define QIB_7322_IntRedirect0_vec10_LSB … #define QIB_7322_IntRedirect0_vec10_MSB … #define QIB_7322_IntRedirect0_vec10_RMASK … #define QIB_7322_IntRedirect0_vec9_LSB … #define QIB_7322_IntRedirect0_vec9_MSB … #define QIB_7322_IntRedirect0_vec9_RMASK … #define QIB_7322_IntRedirect0_vec8_LSB … #define QIB_7322_IntRedirect0_vec8_MSB … #define QIB_7322_IntRedirect0_vec8_RMASK … #define QIB_7322_IntRedirect0_vec7_LSB … #define QIB_7322_IntRedirect0_vec7_MSB … #define QIB_7322_IntRedirect0_vec7_RMASK … #define QIB_7322_IntRedirect0_vec6_LSB … #define QIB_7322_IntRedirect0_vec6_MSB … #define QIB_7322_IntRedirect0_vec6_RMASK … #define QIB_7322_IntRedirect0_vec5_LSB … #define QIB_7322_IntRedirect0_vec5_MSB … #define QIB_7322_IntRedirect0_vec5_RMASK … #define QIB_7322_IntRedirect0_vec4_LSB … #define QIB_7322_IntRedirect0_vec4_MSB … #define QIB_7322_IntRedirect0_vec4_RMASK … #define QIB_7322_IntRedirect0_vec3_LSB … #define QIB_7322_IntRedirect0_vec3_MSB … #define QIB_7322_IntRedirect0_vec3_RMASK … #define QIB_7322_IntRedirect0_vec2_LSB … #define QIB_7322_IntRedirect0_vec2_MSB … #define QIB_7322_IntRedirect0_vec2_RMASK … #define QIB_7322_IntRedirect0_vec1_LSB … #define QIB_7322_IntRedirect0_vec1_MSB … #define QIB_7322_IntRedirect0_vec1_RMASK … #define QIB_7322_IntRedirect0_vec0_LSB … #define QIB_7322_IntRedirect0_vec0_MSB … #define QIB_7322_IntRedirect0_vec0_RMASK … #define QIB_7322_Int_Granted_OFFS … #define QIB_7322_Int_Granted_DEF … #define QIB_7322_vec_clr_without_int_OFFS … #define QIB_7322_vec_clr_without_int_DEF … #define QIB_7322_DCACtrlA_OFFS … #define QIB_7322_DCACtrlA_DEF … #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_LSB … #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_MSB … #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK … #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_LSB … #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_MSB … #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK … #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_LSB … #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_MSB … #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK … #define QIB_7322_DCACtrlA_EagerDCAEnable_LSB … #define QIB_7322_DCACtrlA_EagerDCAEnable_MSB … #define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK … #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_LSB … #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_MSB … #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK … #define QIB_7322_DCACtrlB_OFFS … #define QIB_7322_DCACtrlB_DEF … #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_LSB … #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_MSB … #define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_LSB … #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_MSB … #define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_LSB … #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_MSB … #define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_LSB … #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_MSB … #define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_LSB … #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_MSB … #define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_LSB … #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_MSB … #define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB … #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_MSB … #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_LSB … #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_MSB … #define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_RMASK … #define QIB_7322_DCACtrlC_OFFS … #define QIB_7322_DCACtrlC_DEF … #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_LSB … #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_MSB … #define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_LSB … #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_MSB … #define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_LSB … #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_MSB … #define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_LSB … #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_MSB … #define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_LSB … #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_MSB … #define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_LSB … #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_MSB … #define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB … #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_MSB … #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_LSB … #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_MSB … #define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_RMASK … #define QIB_7322_DCACtrlD_OFFS … #define QIB_7322_DCACtrlD_DEF … #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_LSB … #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_MSB … #define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_LSB … #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_MSB … #define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_LSB … #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_MSB … #define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_LSB … #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_MSB … #define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_LSB … #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_MSB … #define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_LSB … #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_MSB … #define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB … #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_MSB … #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_LSB … #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_MSB … #define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_RMASK … #define QIB_7322_DCACtrlE_OFFS … #define QIB_7322_DCACtrlE_DEF … #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_LSB … #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_MSB … #define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_LSB … #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_MSB … #define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_LSB … #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_MSB … #define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_LSB … #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_MSB … #define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_LSB … #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_MSB … #define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_LSB … #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_MSB … #define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB … #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_MSB … #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_LSB … #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_MSB … #define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_RMASK … #define QIB_7322_DCACtrlF_OFFS … #define QIB_7322_DCACtrlF_DEF … #define QIB_7322_DCACtrlF_SendDma1DCAOPH_LSB … #define QIB_7322_DCACtrlF_SendDma1DCAOPH_MSB … #define QIB_7322_DCACtrlF_SendDma1DCAOPH_RMASK … #define QIB_7322_DCACtrlF_SendDma0DCAOPH_LSB … #define QIB_7322_DCACtrlF_SendDma0DCAOPH_MSB … #define QIB_7322_DCACtrlF_SendDma0DCAOPH_RMASK … #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_LSB … #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_MSB … #define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_LSB … #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_MSB … #define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_RMASK … #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB … #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_MSB … #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_RMASK … #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_LSB … #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_MSB … #define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_RMASK … #define QIB_7322_RcvAvailTimeOut0_OFFS … #define QIB_7322_RcvAvailTimeOut0_DEF … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_LSB … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_MSB … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_RMASK … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_LSB … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_MSB … #define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_RMASK … #define QIB_7322_CntrRegBase_0_OFFS … #define QIB_7322_CntrRegBase_0_DEF … #define QIB_7322_ErrMask_0_OFFS … #define QIB_7322_ErrMask_0_DEF … #define QIB_7322_ErrMask_0_IBStatusChangedMask_LSB … #define QIB_7322_ErrMask_0_IBStatusChangedMask_MSB … #define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK … #define QIB_7322_ErrMask_0_SHeadersErrMask_LSB … #define QIB_7322_ErrMask_0_SHeadersErrMask_MSB … #define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK … #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_LSB … #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_MSB … #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaHaltErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaHaltErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK … #define QIB_7322_ErrMask_0_SDma1stDescErrMask_LSB … #define QIB_7322_ErrMask_0_SDma1stDescErrMask_MSB … #define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaBaseErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaBaseErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK … #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_LSB … #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_MSB … #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK … #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_LSB … #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_MSB … #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK … #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_LSB … #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_MSB … #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK … #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_LSB … #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_MSB … #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK … #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_LSB … #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_MSB … #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK … #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_LSB … #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_MSB … #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK … #define QIB_7322_ErrMask_0_SendPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_SendPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_SendUnderRunErrMask_LSB … #define QIB_7322_ErrMask_0_SendUnderRunErrMask_MSB … #define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK … #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_LSB … #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_MSB … #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvHdrErrMask_LSB … #define QIB_7322_ErrMask_0_RcvHdrErrMask_MSB … #define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_LSB … #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_MSB … #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvBadTidErrMask_LSB … #define QIB_7322_ErrMask_0_RcvBadTidErrMask_MSB … #define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_LSB … #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_MSB … #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_LSB … #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_MSB … #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvEBPErrMask_LSB … #define QIB_7322_ErrMask_0_RcvEBPErrMask_MSB … #define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB … #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB … #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_LSB … #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_MSB … #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_LSB … #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_MSB … #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvICRCErrMask_LSB … #define QIB_7322_ErrMask_0_RcvICRCErrMask_MSB … #define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB … #define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB … #define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK … #define QIB_7322_ErrMask_0_RcvFormatErrMask_LSB … #define QIB_7322_ErrMask_0_RcvFormatErrMask_MSB … #define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK … #define QIB_7322_ErrStatus_0_OFFS … #define QIB_7322_ErrStatus_0_DEF … #define QIB_7322_ErrStatus_0_IBStatusChanged_LSB … #define QIB_7322_ErrStatus_0_IBStatusChanged_MSB … #define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK … #define QIB_7322_ErrStatus_0_SHeadersErr_LSB … #define QIB_7322_ErrStatus_0_SHeadersErr_MSB … #define QIB_7322_ErrStatus_0_SHeadersErr_RMASK … #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_LSB … #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_MSB … #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaHaltErr_LSB … #define QIB_7322_ErrStatus_0_SDmaHaltErr_MSB … #define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_LSB … #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_MSB … #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_LSB … #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_MSB … #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_LSB … #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_MSB … #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaDwEnErr_LSB … #define QIB_7322_ErrStatus_0_SDmaDwEnErr_MSB … #define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_LSB … #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_MSB … #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK … #define QIB_7322_ErrStatus_0_SDma1stDescErr_LSB … #define QIB_7322_ErrStatus_0_SDma1stDescErr_MSB … #define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaBaseErr_LSB … #define QIB_7322_ErrStatus_0_SDmaBaseErr_MSB … #define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_LSB … #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_MSB … #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_LSB … #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_MSB … #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK … #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_LSB … #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_MSB … #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK … #define QIB_7322_ErrStatus_0_SendBufMisuseErr_LSB … #define QIB_7322_ErrStatus_0_SendBufMisuseErr_MSB … #define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK … #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_LSB … #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_MSB … #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK … #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_LSB … #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_MSB … #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK … #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_LSB … #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_MSB … #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK … #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_LSB … #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_MSB … #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK … #define QIB_7322_ErrStatus_0_SendPktLenErr_LSB … #define QIB_7322_ErrStatus_0_SendPktLenErr_MSB … #define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_SendUnderRunErr_LSB … #define QIB_7322_ErrStatus_0_SendUnderRunErr_MSB … #define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK … #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_LSB … #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_MSB … #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_SendMinPktLenErr_LSB … #define QIB_7322_ErrStatus_0_SendMinPktLenErr_MSB … #define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_LSB … #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_MSB … #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK … #define QIB_7322_ErrStatus_0_RcvHdrErr_LSB … #define QIB_7322_ErrStatus_0_RcvHdrErr_MSB … #define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK … #define QIB_7322_ErrStatus_0_RcvHdrLenErr_LSB … #define QIB_7322_ErrStatus_0_RcvHdrLenErr_MSB … #define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvBadTidErr_LSB … #define QIB_7322_ErrStatus_0_RcvBadTidErr_MSB … #define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK … #define QIB_7322_ErrStatus_0_RcvBadVersionErr_LSB … #define QIB_7322_ErrStatus_0_RcvBadVersionErr_MSB … #define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK … #define QIB_7322_ErrStatus_0_RcvIBFlowErr_LSB … #define QIB_7322_ErrStatus_0_RcvIBFlowErr_MSB … #define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK … #define QIB_7322_ErrStatus_0_RcvEBPErr_LSB … #define QIB_7322_ErrStatus_0_RcvEBPErr_MSB … #define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK … #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB … #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB … #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK … #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_LSB … #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_MSB … #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK … #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_LSB … #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_MSB … #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_LSB … #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_MSB … #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_LSB … #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_MSB … #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_LSB … #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_MSB … #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK … #define QIB_7322_ErrStatus_0_RcvICRCErr_LSB … #define QIB_7322_ErrStatus_0_RcvICRCErr_MSB … #define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK … #define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB … #define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB … #define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK … #define QIB_7322_ErrStatus_0_RcvFormatErr_LSB … #define QIB_7322_ErrStatus_0_RcvFormatErr_MSB … #define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK … #define QIB_7322_ErrClear_0_OFFS … #define QIB_7322_ErrClear_0_DEF … #define QIB_7322_ErrClear_0_IBStatusChangedClear_LSB … #define QIB_7322_ErrClear_0_IBStatusChangedClear_MSB … #define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK … #define QIB_7322_ErrClear_0_SHeadersErrClear_LSB … #define QIB_7322_ErrClear_0_SHeadersErrClear_MSB … #define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK … #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_LSB … #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_MSB … #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaHaltErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaHaltErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK … #define QIB_7322_ErrClear_0_SDma1stDescErrClear_LSB … #define QIB_7322_ErrClear_0_SDma1stDescErrClear_MSB … #define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaBaseErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaBaseErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK … #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_LSB … #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_MSB … #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK … #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_LSB … #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_MSB … #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK … #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_LSB … #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_MSB … #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK … #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_LSB … #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_MSB … #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK … #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_LSB … #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_MSB … #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK … #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_LSB … #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_MSB … #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK … #define QIB_7322_ErrClear_0_SendPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_SendPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_SendUnderRunErrClear_LSB … #define QIB_7322_ErrClear_0_SendUnderRunErrClear_MSB … #define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK … #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_LSB … #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_MSB … #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvHdrErrClear_LSB … #define QIB_7322_ErrClear_0_RcvHdrErrClear_MSB … #define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_LSB … #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_MSB … #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvBadTidErrClear_LSB … #define QIB_7322_ErrClear_0_RcvBadTidErrClear_MSB … #define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_LSB … #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_MSB … #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_LSB … #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_MSB … #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvEBPErrClear_LSB … #define QIB_7322_ErrClear_0_RcvEBPErrClear_MSB … #define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB … #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB … #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_LSB … #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_MSB … #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_LSB … #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_MSB … #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvICRCErrClear_LSB … #define QIB_7322_ErrClear_0_RcvICRCErrClear_MSB … #define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB … #define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB … #define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK … #define QIB_7322_ErrClear_0_RcvFormatErrClear_LSB … #define QIB_7322_ErrClear_0_RcvFormatErrClear_MSB … #define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK … #define QIB_7322_TXEStatus_0_OFFS … #define QIB_7322_TXEStatus_0_DEF … #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_LSB … #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_MSB … #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK … #define QIB_7322_TXEStatus_0_RmFifoEmpty_LSB … #define QIB_7322_TXEStatus_0_RmFifoEmpty_MSB … #define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_LSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_MSB … #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK … #define QIB_7322_RcvCtrl_0_OFFS … #define QIB_7322_RcvCtrl_0_DEF … #define QIB_7322_RcvCtrl_0_RcvResetCredit_LSB … #define QIB_7322_RcvCtrl_0_RcvResetCredit_MSB … #define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK … #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_LSB … #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_MSB … #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK … #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_LSB … #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_MSB … #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK … #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_LSB … #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_MSB … #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK … #define QIB_7322_RcvCtrl_0_ContextEnableUser_LSB … #define QIB_7322_RcvCtrl_0_ContextEnableUser_MSB … #define QIB_7322_RcvCtrl_0_ContextEnableUser_RMASK … #define QIB_7322_RcvCtrl_0_ContextEnableKernel_LSB … #define QIB_7322_RcvCtrl_0_ContextEnableKernel_MSB … #define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK … #define QIB_7322_RcvBTHQP_0_OFFS … #define QIB_7322_RcvBTHQP_0_DEF … #define QIB_7322_RcvBTHQP_0_RcvBTHQP_LSB … #define QIB_7322_RcvBTHQP_0_RcvBTHQP_MSB … #define QIB_7322_RcvBTHQP_0_RcvBTHQP_RMASK … #define QIB_7322_RcvQPMapTableA_0_OFFS … #define QIB_7322_RcvQPMapTableA_0_DEF … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_RMASK … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_RMASK … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_RMASK … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_RMASK … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_RMASK … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_LSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_MSB … #define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_RMASK … #define QIB_7322_RcvQPMapTableB_0_OFFS … #define QIB_7322_RcvQPMapTableB_0_DEF … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_RMASK … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_RMASK … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_RMASK … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_RMASK … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_RMASK … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_LSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_MSB … #define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_RMASK … #define QIB_7322_RcvQPMapTableC_0_OFFS … #define QIB_7322_RcvQPMapTableC_0_DEF … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_RMASK … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_RMASK … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_RMASK … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_RMASK … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_RMASK … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_LSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_MSB … #define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_RMASK … #define QIB_7322_RcvQPMapTableD_0_OFFS … #define QIB_7322_RcvQPMapTableD_0_DEF … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_RMASK … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_RMASK … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_RMASK … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_RMASK … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_RMASK … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_LSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_MSB … #define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_RMASK … #define QIB_7322_RcvQPMapTableE_0_OFFS … #define QIB_7322_RcvQPMapTableE_0_DEF … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_RMASK … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_RMASK … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_RMASK … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_RMASK … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_RMASK … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_LSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_MSB … #define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_RMASK … #define QIB_7322_RcvQPMapTableF_0_OFFS … #define QIB_7322_RcvQPMapTableF_0_DEF … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_LSB … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_MSB … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_RMASK … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_LSB … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_MSB … #define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_RMASK … #define QIB_7322_PSStat_0_OFFS … #define QIB_7322_PSStat_0_DEF … #define QIB_7322_PSStart_0_OFFS … #define QIB_7322_PSStart_0_DEF … #define QIB_7322_PSInterval_0_OFFS … #define QIB_7322_PSInterval_0_DEF … #define QIB_7322_RcvStatus_0_OFFS … #define QIB_7322_RcvStatus_0_DEF … #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB … #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_MSB … #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_RMASK … #define QIB_7322_RcvStatus_0_RxPktInProgress_LSB … #define QIB_7322_RcvStatus_0_RxPktInProgress_MSB … #define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK … #define QIB_7322_RcvPartitionKey_0_OFFS … #define QIB_7322_RcvPartitionKey_0_DEF … #define QIB_7322_RcvQPMulticastContext_0_OFFS … #define QIB_7322_RcvQPMulticastContext_0_DEF … #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_LSB … #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_MSB … #define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_RMASK … #define QIB_7322_RcvPktLEDCnt_0_OFFS … #define QIB_7322_RcvPktLEDCnt_0_DEF … #define QIB_7322_RcvPktLEDCnt_0_ONperiod_LSB … #define QIB_7322_RcvPktLEDCnt_0_ONperiod_MSB … #define QIB_7322_RcvPktLEDCnt_0_ONperiod_RMASK … #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_LSB … #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_MSB … #define QIB_7322_RcvPktLEDCnt_0_OFFperiod_RMASK … #define QIB_7322_SendDmaIdleCnt_0_OFFS … #define QIB_7322_SendDmaIdleCnt_0_DEF … #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_LSB … #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_MSB … #define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_RMASK … #define QIB_7322_SendDmaReloadCnt_0_OFFS … #define QIB_7322_SendDmaReloadCnt_0_DEF … #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_LSB … #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_MSB … #define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_RMASK … #define QIB_7322_SendDmaDescCnt_0_OFFS … #define QIB_7322_SendDmaDescCnt_0_DEF … #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_LSB … #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_MSB … #define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_RMASK … #define QIB_7322_SendCtrl_0_OFFS … #define QIB_7322_SendCtrl_0_DEF … #define QIB_7322_SendCtrl_0_IBVLArbiterEn_LSB … #define QIB_7322_SendCtrl_0_IBVLArbiterEn_MSB … #define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK … #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_LSB … #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_MSB … #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK … #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_LSB … #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_MSB … #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK … #define QIB_7322_SendCtrl_0_SDmaHalt_LSB … #define QIB_7322_SendCtrl_0_SDmaHalt_MSB … #define QIB_7322_SendCtrl_0_SDmaHalt_RMASK … #define QIB_7322_SendCtrl_0_SDmaEnable_LSB … #define QIB_7322_SendCtrl_0_SDmaEnable_MSB … #define QIB_7322_SendCtrl_0_SDmaEnable_RMASK … #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_LSB … #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_MSB … #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK … #define QIB_7322_SendCtrl_0_SDmaIntEnable_LSB … #define QIB_7322_SendCtrl_0_SDmaIntEnable_MSB … #define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK … #define QIB_7322_SendCtrl_0_SDmaCleanup_LSB … #define QIB_7322_SendCtrl_0_SDmaCleanup_MSB … #define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK … #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_LSB … #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_MSB … #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK … #define QIB_7322_SendCtrl_0_SendEnable_LSB … #define QIB_7322_SendCtrl_0_SendEnable_MSB … #define QIB_7322_SendCtrl_0_SendEnable_RMASK … #define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB … #define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB … #define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK … #define QIB_7322_SendCtrl_0_TxeAbortIbc_LSB … #define QIB_7322_SendCtrl_0_TxeAbortIbc_MSB … #define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK … #define QIB_7322_SendDmaBase_0_OFFS … #define QIB_7322_SendDmaBase_0_DEF … #define QIB_7322_SendDmaBase_0_SendDmaBase_LSB … #define QIB_7322_SendDmaBase_0_SendDmaBase_MSB … #define QIB_7322_SendDmaBase_0_SendDmaBase_RMASK … #define QIB_7322_SendDmaLenGen_0_OFFS … #define QIB_7322_SendDmaLenGen_0_DEF … #define QIB_7322_SendDmaLenGen_0_Generation_LSB … #define QIB_7322_SendDmaLenGen_0_Generation_MSB … #define QIB_7322_SendDmaLenGen_0_Generation_RMASK … #define QIB_7322_SendDmaLenGen_0_Length_LSB … #define QIB_7322_SendDmaLenGen_0_Length_MSB … #define QIB_7322_SendDmaLenGen_0_Length_RMASK … #define QIB_7322_SendDmaTail_0_OFFS … #define QIB_7322_SendDmaTail_0_DEF … #define QIB_7322_SendDmaTail_0_SendDmaTail_LSB … #define QIB_7322_SendDmaTail_0_SendDmaTail_MSB … #define QIB_7322_SendDmaTail_0_SendDmaTail_RMASK … #define QIB_7322_SendDmaHead_0_OFFS … #define QIB_7322_SendDmaHead_0_DEF … #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_LSB … #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_MSB … #define QIB_7322_SendDmaHead_0_InternalSendDmaHead_RMASK … #define QIB_7322_SendDmaHead_0_SendDmaHead_LSB … #define QIB_7322_SendDmaHead_0_SendDmaHead_MSB … #define QIB_7322_SendDmaHead_0_SendDmaHead_RMASK … #define QIB_7322_SendDmaHeadAddr_0_OFFS … #define QIB_7322_SendDmaHeadAddr_0_DEF … #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_LSB … #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_MSB … #define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_RMASK … #define QIB_7322_SendDmaBufMask0_0_OFFS … #define QIB_7322_SendDmaBufMask0_0_DEF … #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_LSB … #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_MSB … #define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_RMASK … #define QIB_7322_SendDmaStatus_0_OFFS … #define QIB_7322_SendDmaStatus_0_DEF … #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_LSB … #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_MSB … #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK … #define QIB_7322_SendDmaStatus_0_HaltInProg_LSB … #define QIB_7322_SendDmaStatus_0_HaltInProg_MSB … #define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK … #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_LSB … #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_MSB … #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK … #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_LSB … #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_MSB … #define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_RMASK … #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_LSB … #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_MSB … #define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_RMASK … #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_LSB … #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_MSB … #define QIB_7322_SendDmaStatus_0_RpyTag_7_0_RMASK … #define QIB_7322_SendDmaStatus_0_ScbFull_LSB … #define QIB_7322_SendDmaStatus_0_ScbFull_MSB … #define QIB_7322_SendDmaStatus_0_ScbFull_RMASK … #define QIB_7322_SendDmaStatus_0_ScbEmpty_LSB … #define QIB_7322_SendDmaStatus_0_ScbEmpty_MSB … #define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK … #define QIB_7322_SendDmaStatus_0_ScbEntryValid_LSB … #define QIB_7322_SendDmaStatus_0_ScbEntryValid_MSB … #define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK … #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_LSB … #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_MSB … #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoFull_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoFull_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoBufNum_RMASK … #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_LSB … #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_MSB … #define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_RMASK … #define QIB_7322_SendDmaPriorityThld_0_OFFS … #define QIB_7322_SendDmaPriorityThld_0_DEF … #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_LSB … #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_MSB … #define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_RMASK … #define QIB_7322_SendHdrErrSymptom_0_OFFS … #define QIB_7322_SendHdrErrSymptom_0_DEF … #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_LSB … #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_MSB … #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK … #define QIB_7322_SendHdrErrSymptom_0_GRHFail_LSB … #define QIB_7322_SendHdrErrSymptom_0_GRHFail_MSB … #define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK … #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_LSB … #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_MSB … #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK … #define QIB_7322_SendHdrErrSymptom_0_QPFail_LSB … #define QIB_7322_SendHdrErrSymptom_0_QPFail_MSB … #define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK … #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_LSB … #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_MSB … #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK … #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB … #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB … #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK … #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_LSB … #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_MSB … #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK … #define QIB_7322_RxCreditVL0_0_OFFS … #define QIB_7322_RxCreditVL0_0_DEF … #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_LSB … #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_MSB … #define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_RMASK … #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_LSB … #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_MSB … #define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_RMASK … #define QIB_7322_SendDmaBufUsed0_0_OFFS … #define QIB_7322_SendDmaBufUsed0_0_DEF … #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_LSB … #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_MSB … #define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_RMASK … #define QIB_7322_SendCheckControl_0_OFFS … #define QIB_7322_SendCheckControl_0_DEF … #define QIB_7322_SendCheckControl_0_PKey_En_LSB … #define QIB_7322_SendCheckControl_0_PKey_En_MSB … #define QIB_7322_SendCheckControl_0_PKey_En_RMASK … #define QIB_7322_SendCheckControl_0_BTHQP_En_LSB … #define QIB_7322_SendCheckControl_0_BTHQP_En_MSB … #define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK … #define QIB_7322_SendCheckControl_0_SLID_En_LSB … #define QIB_7322_SendCheckControl_0_SLID_En_MSB … #define QIB_7322_SendCheckControl_0_SLID_En_RMASK … #define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB … #define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB … #define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK … #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_LSB … #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_MSB … #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK … #define QIB_7322_SendIBSLIDMask_0_OFFS … #define QIB_7322_SendIBSLIDMask_0_DEF … #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_LSB … #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_MSB … #define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK … #define QIB_7322_SendIBSLIDAssign_0_OFFS … #define QIB_7322_SendIBSLIDAssign_0_DEF … #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_LSB … #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_MSB … #define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK … #define QIB_7322_IBCStatusA_0_OFFS … #define QIB_7322_IBCStatusA_0_DEF … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_LSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_MSB … #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK … #define QIB_7322_IBCStatusA_0_TxReady_LSB … #define QIB_7322_IBCStatusA_0_TxReady_MSB … #define QIB_7322_IBCStatusA_0_TxReady_RMASK … #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_LSB … #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_MSB … #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK … #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_LSB … #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_MSB … #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK … #define QIB_7322_IBCStatusA_0_ScrambleEn_LSB … #define QIB_7322_IBCStatusA_0_ScrambleEn_MSB … #define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK … #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_LSB … #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_MSB … #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK … #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_LSB … #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_MSB … #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK … #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_LSB … #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_MSB … #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK … #define QIB_7322_IBCStatusA_0_LinkWidthActive_LSB … #define QIB_7322_IBCStatusA_0_LinkWidthActive_MSB … #define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK … #define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB … #define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB … #define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK … #define QIB_7322_IBCStatusA_0_LinkState_LSB … #define QIB_7322_IBCStatusA_0_LinkState_MSB … #define QIB_7322_IBCStatusA_0_LinkState_RMASK … #define QIB_7322_IBCStatusA_0_LinkTrainingState_LSB … #define QIB_7322_IBCStatusA_0_LinkTrainingState_MSB … #define QIB_7322_IBCStatusA_0_LinkTrainingState_RMASK … #define QIB_7322_IBCStatusB_0_OFFS … #define QIB_7322_IBCStatusB_0_DEF … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_LSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_MSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_LSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_MSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_LSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_MSB … #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK … #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_LSB … #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_MSB … #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK … #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_LSB … #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_MSB … #define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_RMASK … #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_LSB … #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_MSB … #define QIB_7322_IBCStatusB_0_RxEqLocalDevice_RMASK … #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_LSB … #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_MSB … #define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_RMASK … #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_LSB … #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_MSB … #define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_RMASK … #define QIB_7322_IBCCtrlA_0_OFFS … #define QIB_7322_IBCCtrlA_0_DEF … #define QIB_7322_IBCCtrlA_0_Loopback_LSB … #define QIB_7322_IBCCtrlA_0_Loopback_MSB … #define QIB_7322_IBCCtrlA_0_Loopback_RMASK … #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_LSB … #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_MSB … #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK … #define QIB_7322_IBCCtrlA_0_IBLinkEn_LSB … #define QIB_7322_IBCCtrlA_0_IBLinkEn_MSB … #define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK … #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_LSB … #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_MSB … #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK … #define QIB_7322_IBCCtrlA_0_NumVLane_LSB … #define QIB_7322_IBCCtrlA_0_NumVLane_MSB … #define QIB_7322_IBCCtrlA_0_NumVLane_RMASK … #define QIB_7322_IBCCtrlA_0_OverrunThreshold_LSB … #define QIB_7322_IBCCtrlA_0_OverrunThreshold_MSB … #define QIB_7322_IBCCtrlA_0_OverrunThreshold_RMASK … #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_LSB … #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_MSB … #define QIB_7322_IBCCtrlA_0_PhyerrThreshold_RMASK … #define QIB_7322_IBCCtrlA_0_MaxPktLen_LSB … #define QIB_7322_IBCCtrlA_0_MaxPktLen_MSB … #define QIB_7322_IBCCtrlA_0_MaxPktLen_RMASK … #define QIB_7322_IBCCtrlA_0_LinkCmd_LSB … #define QIB_7322_IBCCtrlA_0_LinkCmd_MSB … #define QIB_7322_IBCCtrlA_0_LinkCmd_RMASK … #define QIB_7322_IBCCtrlA_0_LinkInitCmd_LSB … #define QIB_7322_IBCCtrlA_0_LinkInitCmd_MSB … #define QIB_7322_IBCCtrlA_0_LinkInitCmd_RMASK … #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB … #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_MSB … #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_RMASK … #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_LSB … #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_MSB … #define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_RMASK … #define QIB_7322_IBCCtrlB_0_OFFS … #define QIB_7322_IBCCtrlB_0_DEF … #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_LSB … #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_MSB … #define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK … #define QIB_7322_IBCCtrlB_0_IB_DLID_LSB … #define QIB_7322_IBCCtrlB_0_IB_DLID_MSB … #define QIB_7322_IBCCtrlB_0_IB_DLID_RMASK … #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_LSB … #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_MSB … #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK … #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_LSB … #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_MSB … #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK … #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_LSB … #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_MSB … #define QIB_7322_IBCCtrlB_0_HRTBT_PORT_RMASK … #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_LSB … #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_MSB … #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK … #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_LSB … #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_MSB … #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK … #define QIB_7322_IBCCtrlB_0_SD_DDS_LSB … #define QIB_7322_IBCCtrlB_0_SD_DDS_MSB … #define QIB_7322_IBCCtrlB_0_SD_DDS_RMASK … #define QIB_7322_IBCCtrlB_0_SD_DDSV_LSB … #define QIB_7322_IBCCtrlB_0_SD_DDSV_MSB … #define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK … #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_LSB … #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_MSB … #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK … #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_LSB … #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_MSB … #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK … #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB … #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB … #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK … #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_LSB … #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_MSB … #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK … #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_LSB … #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_MSB … #define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_RMASK … #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_LSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_MSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK … #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_LSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_MSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK … #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_LSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_MSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK … #define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB … #define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK … #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_LSB … #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_MSB … #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK … #define QIB_7322_IBCCtrlC_0_OFFS … #define QIB_7322_IBCCtrlC_0_DEF … #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_LSB … #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_MSB … #define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_RMASK … #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_LSB … #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_MSB … #define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_RMASK … #define QIB_7322_HRTBT_GUID_0_OFFS … #define QIB_7322_HRTBT_GUID_0_DEF … #define QIB_7322_IB_SDTEST_IF_TX_0_OFFS … #define QIB_7322_IB_SDTEST_IF_TX_0_DEF … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_LSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_MSB … #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_OFFS … #define QIB_7322_IB_SDTEST_IF_RX_0_DEF … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_LSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_MSB … #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK … #define QIB_7322_IBNCModeCtrl_0_OFFS … #define QIB_7322_IBNCModeCtrl_0_DEF … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_LSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_MSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_LSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_MSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_LSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_MSB … #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_LSB … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_MSB … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_RMASK … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_MSB … #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_RMASK … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_LSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_MSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_LSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_MSB … #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK … #define QIB_7322_IBSerdesStatus_0_OFFS … #define QIB_7322_IBSerdesStatus_0_DEF … #define QIB_7322_IBPCSConfig_0_OFFS … #define QIB_7322_IBPCSConfig_0_DEF … #define QIB_7322_IBPCSConfig_0_link_sync_mask_LSB … #define QIB_7322_IBPCSConfig_0_link_sync_mask_MSB … #define QIB_7322_IBPCSConfig_0_link_sync_mask_RMASK … #define QIB_7322_IBPCSConfig_0_xcv_rreset_LSB … #define QIB_7322_IBPCSConfig_0_xcv_rreset_MSB … #define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK … #define QIB_7322_IBPCSConfig_0_xcv_treset_LSB … #define QIB_7322_IBPCSConfig_0_xcv_treset_MSB … #define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK … #define QIB_7322_IBPCSConfig_0_tx_rx_reset_LSB … #define QIB_7322_IBPCSConfig_0_tx_rx_reset_MSB … #define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK … #define QIB_7322_IBSerdesCtrl_0_OFFS … #define QIB_7322_IBSerdesCtrl_0_DEF … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_LSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_MSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_LSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_MSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_LSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_MSB … #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK … #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_LSB … #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_MSB … #define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_RMASK … #define QIB_7322_IBSerdesCtrl_0_CGMODE_LSB … #define QIB_7322_IBSerdesCtrl_0_CGMODE_MSB … #define QIB_7322_IBSerdesCtrl_0_CGMODE_RMASK … #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_LSB … #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_MSB … #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK … #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_LSB … #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_MSB … #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK … #define QIB_7322_IBSerdesCtrl_0_LPEN_LSB … #define QIB_7322_IBSerdesCtrl_0_LPEN_MSB … #define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK … #define QIB_7322_IBSerdesCtrl_0_PLLPD_LSB … #define QIB_7322_IBSerdesCtrl_0_PLLPD_MSB … #define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK … #define QIB_7322_IBSerdesCtrl_0_TXPD_LSB … #define QIB_7322_IBSerdesCtrl_0_TXPD_MSB … #define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK … #define QIB_7322_IBSerdesCtrl_0_RXPD_LSB … #define QIB_7322_IBSerdesCtrl_0_RXPD_MSB … #define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK … #define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB … #define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB … #define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK … #define QIB_7322_IBSerdesCtrl_0_CMODE_LSB … #define QIB_7322_IBSerdesCtrl_0_CMODE_MSB … #define QIB_7322_IBSerdesCtrl_0_CMODE_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_OFFS … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_DEF … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_RMASK … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_LSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_MSB … #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_OFFS … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_DEF … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_RMASK … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_LSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_MSB … #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_RMASK … #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_OFFS … #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_DEF … #define QIB_7322_HighPriorityLimit_0_OFFS … #define QIB_7322_HighPriorityLimit_0_DEF … #define QIB_7322_HighPriorityLimit_0_Limit_LSB … #define QIB_7322_HighPriorityLimit_0_Limit_MSB … #define QIB_7322_HighPriorityLimit_0_Limit_RMASK … #define QIB_7322_LowPriority0_0_OFFS … #define QIB_7322_LowPriority0_0_DEF … #define QIB_7322_LowPriority0_0_VirtualLane_LSB … #define QIB_7322_LowPriority0_0_VirtualLane_MSB … #define QIB_7322_LowPriority0_0_VirtualLane_RMASK … #define QIB_7322_LowPriority0_0_Weight_LSB … #define QIB_7322_LowPriority0_0_Weight_MSB … #define QIB_7322_LowPriority0_0_Weight_RMASK … #define QIB_7322_HighPriority0_0_OFFS … #define QIB_7322_HighPriority0_0_DEF … #define QIB_7322_HighPriority0_0_VirtualLane_LSB … #define QIB_7322_HighPriority0_0_VirtualLane_MSB … #define QIB_7322_HighPriority0_0_VirtualLane_RMASK … #define QIB_7322_HighPriority0_0_Weight_LSB … #define QIB_7322_HighPriority0_0_Weight_MSB … #define QIB_7322_HighPriority0_0_Weight_RMASK … #define QIB_7322_CntrRegBase_1_OFFS … #define QIB_7322_CntrRegBase_1_DEF … #define QIB_7322_RcvQPMulticastContext_1_OFFS … #define QIB_7322_SendCtrl_1_OFFS … #define QIB_7322_SendBufAvail0_OFFS … #define QIB_7322_SendBufAvail0_DEF … #define QIB_7322_SendBufAvail0_SendBuf_31_0_LSB … #define QIB_7322_SendBufAvail0_SendBuf_31_0_MSB … #define QIB_7322_SendBufAvail0_SendBuf_31_0_RMASK … #define QIB_7322_MsixTable_OFFS … #define QIB_7322_MsixTable_DEF … #define QIB_7322_MsixPba_OFFS … #define QIB_7322_MsixPba_DEF … #define QIB_7322_LAMemory_OFFS … #define QIB_7322_LAMemory_DEF … #define QIB_7322_LBIntCnt_OFFS … #define QIB_7322_LBIntCnt_DEF … #define QIB_7322_LBFlowStallCnt_OFFS … #define QIB_7322_LBFlowStallCnt_DEF … #define QIB_7322_RxTIDFullErrCnt_OFFS … #define QIB_7322_RxTIDFullErrCnt_DEF … #define QIB_7322_RxTIDValidErrCnt_OFFS … #define QIB_7322_RxTIDValidErrCnt_DEF … #define QIB_7322_RxP0HdrEgrOvflCnt_OFFS … #define QIB_7322_RxP0HdrEgrOvflCnt_DEF … #define QIB_7322_PcieRetryBufDiagQwordCnt_OFFS … #define QIB_7322_PcieRetryBufDiagQwordCnt_DEF … #define QIB_7322_RxTidFlowDropCnt_OFFS … #define QIB_7322_RxTidFlowDropCnt_DEF … #define QIB_7322_LBIntCnt_0_OFFS … #define QIB_7322_LBIntCnt_0_DEF … #define QIB_7322_TxCreditUpToDateTimeOut_0_OFFS … #define QIB_7322_TxCreditUpToDateTimeOut_0_DEF … #define QIB_7322_TxSDmaDescCnt_0_OFFS … #define QIB_7322_TxSDmaDescCnt_0_DEF … #define QIB_7322_TxUnsupVLErrCnt_0_OFFS … #define QIB_7322_TxUnsupVLErrCnt_0_DEF … #define QIB_7322_TxDataPktCnt_0_OFFS … #define QIB_7322_TxDataPktCnt_0_DEF … #define QIB_7322_TxFlowPktCnt_0_OFFS … #define QIB_7322_TxFlowPktCnt_0_DEF … #define QIB_7322_TxDwordCnt_0_OFFS … #define QIB_7322_TxDwordCnt_0_DEF … #define QIB_7322_TxLenErrCnt_0_OFFS … #define QIB_7322_TxLenErrCnt_0_DEF … #define QIB_7322_TxMaxMinLenErrCnt_0_OFFS … #define QIB_7322_TxMaxMinLenErrCnt_0_DEF … #define QIB_7322_TxUnderrunCnt_0_OFFS … #define QIB_7322_TxUnderrunCnt_0_DEF … #define QIB_7322_TxFlowStallCnt_0_OFFS … #define QIB_7322_TxFlowStallCnt_0_DEF … #define QIB_7322_TxDroppedPktCnt_0_OFFS … #define QIB_7322_TxDroppedPktCnt_0_DEF … #define QIB_7322_RxDroppedPktCnt_0_OFFS … #define QIB_7322_RxDroppedPktCnt_0_DEF … #define QIB_7322_RxDataPktCnt_0_OFFS … #define QIB_7322_RxDataPktCnt_0_DEF … #define QIB_7322_RxFlowPktCnt_0_OFFS … #define QIB_7322_RxFlowPktCnt_0_DEF … #define QIB_7322_RxDwordCnt_0_OFFS … #define QIB_7322_RxDwordCnt_0_DEF … #define QIB_7322_RxLenErrCnt_0_OFFS … #define QIB_7322_RxLenErrCnt_0_DEF … #define QIB_7322_RxMaxMinLenErrCnt_0_OFFS … #define QIB_7322_RxMaxMinLenErrCnt_0_DEF … #define QIB_7322_RxICRCErrCnt_0_OFFS … #define QIB_7322_RxICRCErrCnt_0_DEF … #define QIB_7322_RxVCRCErrCnt_0_OFFS … #define QIB_7322_RxVCRCErrCnt_0_DEF … #define QIB_7322_RxFlowCtrlViolCnt_0_OFFS … #define QIB_7322_RxFlowCtrlViolCnt_0_DEF … #define QIB_7322_RxVersionErrCnt_0_OFFS … #define QIB_7322_RxVersionErrCnt_0_DEF … #define QIB_7322_RxLinkMalformCnt_0_OFFS … #define QIB_7322_RxLinkMalformCnt_0_DEF … #define QIB_7322_RxEBPCnt_0_OFFS … #define QIB_7322_RxEBPCnt_0_DEF … #define QIB_7322_RxLPCRCErrCnt_0_OFFS … #define QIB_7322_RxLPCRCErrCnt_0_DEF … #define QIB_7322_RxBufOvflCnt_0_OFFS … #define QIB_7322_RxBufOvflCnt_0_DEF … #define QIB_7322_RxLenTruncateCnt_0_OFFS … #define QIB_7322_RxLenTruncateCnt_0_DEF … #define QIB_7322_RxPKeyMismatchCnt_0_OFFS … #define QIB_7322_RxPKeyMismatchCnt_0_DEF … #define QIB_7322_IBLinkDownedCnt_0_OFFS … #define QIB_7322_IBLinkDownedCnt_0_DEF … #define QIB_7322_IBSymbolErrCnt_0_OFFS … #define QIB_7322_IBSymbolErrCnt_0_DEF … #define QIB_7322_IBStatusChangeCnt_0_OFFS … #define QIB_7322_IBStatusChangeCnt_0_DEF … #define QIB_7322_IBLinkErrRecoveryCnt_0_OFFS … #define QIB_7322_IBLinkErrRecoveryCnt_0_DEF … #define QIB_7322_ExcessBufferOvflCnt_0_OFFS … #define QIB_7322_ExcessBufferOvflCnt_0_DEF … #define QIB_7322_LocalLinkIntegrityErrCnt_0_OFFS … #define QIB_7322_LocalLinkIntegrityErrCnt_0_DEF … #define QIB_7322_RxVlErrCnt_0_OFFS … #define QIB_7322_RxVlErrCnt_0_DEF … #define QIB_7322_RxDlidFltrCnt_0_OFFS … #define QIB_7322_RxDlidFltrCnt_0_DEF … #define QIB_7322_RxVL15DroppedPktCnt_0_OFFS … #define QIB_7322_RxVL15DroppedPktCnt_0_DEF … #define QIB_7322_RxOtherLocalPhyErrCnt_0_OFFS … #define QIB_7322_RxOtherLocalPhyErrCnt_0_DEF … #define QIB_7322_RxQPInvalidContextCnt_0_OFFS … #define QIB_7322_RxQPInvalidContextCnt_0_DEF … #define QIB_7322_TxHeadersErrCnt_0_OFFS … #define QIB_7322_TxHeadersErrCnt_0_DEF … #define QIB_7322_PSRcvDataCount_0_OFFS … #define QIB_7322_PSRcvDataCount_0_DEF … #define QIB_7322_PSRcvPktsCount_0_OFFS … #define QIB_7322_PSRcvPktsCount_0_DEF … #define QIB_7322_PSXmitDataCount_0_OFFS … #define QIB_7322_PSXmitDataCount_0_DEF … #define QIB_7322_PSXmitPktsCount_0_OFFS … #define QIB_7322_PSXmitPktsCount_0_DEF … #define QIB_7322_PSXmitWaitCount_0_OFFS … #define QIB_7322_PSXmitWaitCount_0_DEF … #define QIB_7322_LBIntCnt_1_OFFS … #define QIB_7322_LBIntCnt_1_DEF … #define QIB_7322_TxCreditUpToDateTimeOut_1_OFFS … #define QIB_7322_TxCreditUpToDateTimeOut_1_DEF … #define QIB_7322_TxSDmaDescCnt_1_OFFS … #define QIB_7322_TxSDmaDescCnt_1_DEF … #define QIB_7322_TxUnsupVLErrCnt_1_OFFS … #define QIB_7322_TxUnsupVLErrCnt_1_DEF … #define QIB_7322_TxDataPktCnt_1_OFFS … #define QIB_7322_TxDataPktCnt_1_DEF … #define QIB_7322_TxFlowPktCnt_1_OFFS … #define QIB_7322_TxFlowPktCnt_1_DEF … #define QIB_7322_TxDwordCnt_1_OFFS … #define QIB_7322_TxDwordCnt_1_DEF … #define QIB_7322_TxLenErrCnt_1_OFFS … #define QIB_7322_TxLenErrCnt_1_DEF … #define QIB_7322_TxMaxMinLenErrCnt_1_OFFS … #define QIB_7322_TxMaxMinLenErrCnt_1_DEF … #define QIB_7322_TxUnderrunCnt_1_OFFS … #define QIB_7322_TxUnderrunCnt_1_DEF … #define QIB_7322_TxFlowStallCnt_1_OFFS … #define QIB_7322_TxFlowStallCnt_1_DEF … #define QIB_7322_TxDroppedPktCnt_1_OFFS … #define QIB_7322_TxDroppedPktCnt_1_DEF … #define QIB_7322_RxDroppedPktCnt_1_OFFS … #define QIB_7322_RxDroppedPktCnt_1_DEF … #define QIB_7322_RxDataPktCnt_1_OFFS … #define QIB_7322_RxDataPktCnt_1_DEF … #define QIB_7322_RxFlowPktCnt_1_OFFS … #define QIB_7322_RxFlowPktCnt_1_DEF … #define QIB_7322_RxDwordCnt_1_OFFS … #define QIB_7322_RxDwordCnt_1_DEF … #define QIB_7322_RxLenErrCnt_1_OFFS … #define QIB_7322_RxLenErrCnt_1_DEF … #define QIB_7322_RxMaxMinLenErrCnt_1_OFFS … #define QIB_7322_RxMaxMinLenErrCnt_1_DEF … #define QIB_7322_RxICRCErrCnt_1_OFFS … #define QIB_7322_RxICRCErrCnt_1_DEF … #define QIB_7322_RxVCRCErrCnt_1_OFFS … #define QIB_7322_RxVCRCErrCnt_1_DEF … #define QIB_7322_RxFlowCtrlViolCnt_1_OFFS … #define QIB_7322_RxFlowCtrlViolCnt_1_DEF … #define QIB_7322_RxVersionErrCnt_1_OFFS … #define QIB_7322_RxVersionErrCnt_1_DEF … #define QIB_7322_RxLinkMalformCnt_1_OFFS … #define QIB_7322_RxLinkMalformCnt_1_DEF … #define QIB_7322_RxEBPCnt_1_OFFS … #define QIB_7322_RxEBPCnt_1_DEF … #define QIB_7322_RxLPCRCErrCnt_1_OFFS … #define QIB_7322_RxLPCRCErrCnt_1_DEF … #define QIB_7322_RxBufOvflCnt_1_OFFS … #define QIB_7322_RxBufOvflCnt_1_DEF … #define QIB_7322_RxLenTruncateCnt_1_OFFS … #define QIB_7322_RxLenTruncateCnt_1_DEF … #define QIB_7322_RxPKeyMismatchCnt_1_OFFS … #define QIB_7322_RxPKeyMismatchCnt_1_DEF … #define QIB_7322_IBLinkDownedCnt_1_OFFS … #define QIB_7322_IBLinkDownedCnt_1_DEF … #define QIB_7322_IBSymbolErrCnt_1_OFFS … #define QIB_7322_IBSymbolErrCnt_1_DEF … #define QIB_7322_IBStatusChangeCnt_1_OFFS … #define QIB_7322_IBStatusChangeCnt_1_DEF … #define QIB_7322_IBLinkErrRecoveryCnt_1_OFFS … #define QIB_7322_IBLinkErrRecoveryCnt_1_DEF … #define QIB_7322_ExcessBufferOvflCnt_1_OFFS … #define QIB_7322_ExcessBufferOvflCnt_1_DEF … #define QIB_7322_LocalLinkIntegrityErrCnt_1_OFFS … #define QIB_7322_LocalLinkIntegrityErrCnt_1_DEF … #define QIB_7322_RxVlErrCnt_1_OFFS … #define QIB_7322_RxVlErrCnt_1_DEF … #define QIB_7322_RxDlidFltrCnt_1_OFFS … #define QIB_7322_RxDlidFltrCnt_1_DEF … #define QIB_7322_RxVL15DroppedPktCnt_1_OFFS … #define QIB_7322_RxVL15DroppedPktCnt_1_DEF … #define QIB_7322_RxOtherLocalPhyErrCnt_1_OFFS … #define QIB_7322_RxOtherLocalPhyErrCnt_1_DEF … #define QIB_7322_RxQPInvalidContextCnt_1_OFFS … #define QIB_7322_RxQPInvalidContextCnt_1_DEF … #define QIB_7322_TxHeadersErrCnt_1_OFFS … #define QIB_7322_TxHeadersErrCnt_1_DEF … #define QIB_7322_PSRcvDataCount_1_OFFS … #define QIB_7322_PSRcvDataCount_1_DEF … #define QIB_7322_PSRcvPktsCount_1_OFFS … #define QIB_7322_PSRcvPktsCount_1_DEF … #define QIB_7322_PSXmitDataCount_1_OFFS … #define QIB_7322_PSXmitDataCount_1_DEF … #define QIB_7322_PSXmitPktsCount_1_OFFS … #define QIB_7322_PSXmitPktsCount_1_DEF … #define QIB_7322_PSXmitWaitCount_1_OFFS … #define QIB_7322_PSXmitWaitCount_1_DEF … #define QIB_7322_RcvEgrArray_OFFS … #define QIB_7322_RcvEgrArray_DEF … #define QIB_7322_RcvEgrArray_RT_BufSize_LSB … #define QIB_7322_RcvEgrArray_RT_BufSize_MSB … #define QIB_7322_RcvEgrArray_RT_BufSize_RMASK … #define QIB_7322_RcvEgrArray_RT_Addr_LSB … #define QIB_7322_RcvEgrArray_RT_Addr_MSB … #define QIB_7322_RcvEgrArray_RT_Addr_RMASK … #define QIB_7322_RcvTIDArray0_OFFS … #define QIB_7322_RcvTIDArray0_DEF … #define QIB_7322_RcvTIDArray0_RT_BufSize_LSB … #define QIB_7322_RcvTIDArray0_RT_BufSize_MSB … #define QIB_7322_RcvTIDArray0_RT_BufSize_RMASK … #define QIB_7322_RcvTIDArray0_RT_Addr_LSB … #define QIB_7322_RcvTIDArray0_RT_Addr_MSB … #define QIB_7322_RcvTIDArray0_RT_Addr_RMASK … #define QIB_7322_IBSD_DDS_MAP_TABLE_0_OFFS … #define QIB_7322_IBSD_DDS_MAP_TABLE_0_DEF … #define QIB_7322_RcvHdrTail0_OFFS … #define QIB_7322_RcvHdrTail0_DEF … #define QIB_7322_RcvHdrHead0_OFFS … #define QIB_7322_RcvHdrHead0_DEF … #define QIB_7322_RcvHdrHead0_counter_LSB … #define QIB_7322_RcvHdrHead0_counter_MSB … #define QIB_7322_RcvHdrHead0_counter_RMASK … #define QIB_7322_RcvHdrHead0_RcvHeadPointer_LSB … #define QIB_7322_RcvHdrHead0_RcvHeadPointer_MSB … #define QIB_7322_RcvHdrHead0_RcvHeadPointer_RMASK … #define QIB_7322_RcvEgrIndexTail0_OFFS … #define QIB_7322_RcvEgrIndexTail0_DEF … #define QIB_7322_RcvEgrIndexHead0_OFFS … #define QIB_7322_RcvEgrIndexHead0_DEF … #define QIB_7322_RcvTIDFlowTable0_OFFS … #define QIB_7322_RcvTIDFlowTable0_DEF … #define QIB_7322_RcvTIDFlowTable0_GenMismatch_LSB … #define QIB_7322_RcvTIDFlowTable0_GenMismatch_MSB … #define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK … #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_LSB … #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_MSB … #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK … #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_LSB … #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_MSB … #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK … #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_LSB … #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_MSB … #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK … #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_LSB … #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_MSB … #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK … #define QIB_7322_RcvTIDFlowTable0_FlowValid_LSB … #define QIB_7322_RcvTIDFlowTable0_FlowValid_MSB … #define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK … #define QIB_7322_RcvTIDFlowTable0_GenVal_LSB … #define QIB_7322_RcvTIDFlowTable0_GenVal_MSB … #define QIB_7322_RcvTIDFlowTable0_GenVal_RMASK … #define QIB_7322_RcvTIDFlowTable0_SeqNum_LSB … #define QIB_7322_RcvTIDFlowTable0_SeqNum_MSB … #define QIB_7322_RcvTIDFlowTable0_SeqNum_RMASK …
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