/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ /* * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. * Copyright (c) 2020, Intel Corporation. All rights reserved. */ #ifndef MLX5_IB_H #define MLX5_IB_H #include <linux/kernel.h> #include <linux/sched.h> #include <rdma/ib_verbs.h> #include <rdma/ib_umem.h> #include <rdma/ib_smi.h> #include <linux/mlx5/driver.h> #include <linux/mlx5/cq.h> #include <linux/mlx5/fs.h> #include <linux/mlx5/qp.h> #include <linux/types.h> #include <linux/mlx5/transobj.h> #include <rdma/ib_user_verbs.h> #include <rdma/mlx5-abi.h> #include <rdma/uverbs_ioctl.h> #include <rdma/mlx5_user_ioctl_cmds.h> #include <rdma/mlx5_user_ioctl_verbs.h> #include "srq.h" #include "qp.h" #include "macsec.h" #define mlx5_ib_dbg(_dev, format, arg...) … #define mlx5_ib_err(_dev, format, arg...) … #define mlx5_ib_warn(_dev, format, arg...) … #define mlx5_ib_log(lvl, _dev, format, arg...) … #define MLX5_IB_DEFAULT_UIDX … #define MLX5_USER_ASSIGNED_UIDX_MASK … static __always_inline unsigned long __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, unsigned int pgsz_shift) { … } static __always_inline unsigned long __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, unsigned int offset_shift) { … } /* * QP/CQ/WQ/etc type commands take a page offset that satisifies: * page_offset_quantized * (page_size/scale) = page_offset * Which restricts allowed page sizes to ones that satisify the above. */ unsigned long __mlx5_umem_find_best_quantized_pgoff( struct ib_umem *umem, unsigned long pgsz_bitmap, unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, unsigned int *page_offset_quantized); #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ pgsz_shift, page_offset_fld, \ scale, page_offset_quantized) … #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ pgsz_shift, page_offset_fld, \ scale, page_offset_quantized) … static inline unsigned long mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf) { … } enum { … }; enum { … }; enum { … }; enum mlx5_ib_mad_ifc_flags { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; enum mlx5_ib_mmap_type { … }; struct mlx5_bfreg_info { … }; struct mlx5_ib_ucontext { … }; static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) { … } struct mlx5_ib_pd { … }; enum { … }; #define MLX5_IB_FLOW_MCAST_PRIO … #define MLX5_IB_FLOW_LAST_PRIO … #if (MLX5_IB_FLOW_LAST_PRIO <= 0) #error "Invalid number of bypass priorities" #endif #define MLX5_IB_FLOW_LEFTOVERS_PRIO … #define MLX5_IB_NUM_FLOW_FT … #define MLX5_IB_NUM_SNIFFER_FTS … #define MLX5_IB_NUM_EGRESS_FTS … #define MLX5_IB_NUM_FDB_FTS … struct mlx5_ib_anchor { … }; struct mlx5_ib_flow_prio { … }; struct mlx5_ib_flow_handler { … }; struct mlx5_ib_flow_matcher { … }; struct mlx5_ib_steering_anchor { … }; struct mlx5_ib_pp { … }; enum mlx5_ib_optional_counter_type { … }; struct mlx5_ib_flow_db { … }; /* Use macros here so that don't have to duplicate * enum ib_qp_type for low-level driver */ #define MLX5_IB_QPT_REG_UMR … /* * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI * creates the actual hardware QP. */ #define MLX5_IB_QPT_HW_GSI … #define MLX5_IB_QPT_DCI … #define MLX5_IB_QPT_DCT … #define MLX5_IB_WR_UMR … #define MLX5_IB_UPD_XLT_ZAP … #define MLX5_IB_UPD_XLT_ENABLE … #define MLX5_IB_UPD_XLT_ATOMIC … #define MLX5_IB_UPD_XLT_ADDR … #define MLX5_IB_UPD_XLT_PD … #define MLX5_IB_UPD_XLT_ACCESS … #define MLX5_IB_UPD_XLT_INDIRECT … /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. * * These flags are intended for internal use by the mlx5_ib driver, and they * rely on the range reserved for that use in the ib_qp_create_flags enum. */ #define MLX5_IB_QP_CREATE_SQPN_QP1 … struct wr_list { … }; enum mlx5_ib_rq_flags { … }; struct mlx5_ib_wq { … }; enum mlx5_ib_wq_flags { … }; #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES … #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES … #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES … #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES … #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES … struct mlx5_ib_rwq { … }; struct mlx5_ib_rwq_ind_table { … }; struct mlx5_ib_ubuffer { … }; struct mlx5_ib_qp_base { … }; struct mlx5_ib_qp_trans { … }; struct mlx5_ib_rss_qp { … }; struct mlx5_ib_rq { … }; struct mlx5_ib_sq { … }; struct mlx5_ib_raw_packet_qp { … }; struct mlx5_bf { … }; struct mlx5_ib_dct { … }; struct mlx5_ib_gsi_qp { … }; struct mlx5_ib_qp { … }; struct mlx5_ib_cq_buf { … }; enum mlx5_ib_cq_pr_flags { … }; struct mlx5_ib_cq { … }; struct mlx5_ib_wc { … }; struct mlx5_ib_srq { … }; struct mlx5_ib_xrcd { … }; enum mlx5_ib_mtt_access_flags { … }; struct mlx5_user_mmap_entry { … }; enum mlx5_mkey_type { … }; struct mlx5r_cache_rb_key { … }; struct mlx5_ib_mkey { … }; #define MLX5_IB_MTT_PRESENT … #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS … #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS … #define mlx5_update_odp_stats(mr, counter_name, value) … struct mlx5_ib_mr { … }; static inline bool is_odp_mr(struct mlx5_ib_mr *mr) { … } static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) { … } struct mlx5_ib_mw { … }; struct mlx5_ib_umr_context { … }; enum { … }; struct umr_common { … }; #define NUM_MKEYS_PER_PAGE … struct mlx5_mkeys_page { … }; static_assert(…); struct mlx5_mkeys_queue { … }; struct mlx5_cache_ent { … }; struct mlx5r_async_create_mkey { … }; struct mlx5_mkey_cache { … }; struct mlx5_ib_port_resources { … }; struct mlx5_data_direct_resources { … }; struct mlx5_ib_resources { … }; #define MAX_OPFC_RULES … struct mlx5_ib_op_fc { … }; struct mlx5_ib_counters { … }; int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, struct mlx5_ib_op_fc *opfc, enum mlx5_ib_optional_counter_type type); void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, struct mlx5_ib_op_fc *opfc, enum mlx5_ib_optional_counter_type type); struct mlx5_ib_multiport_info; struct mlx5_ib_multiport { … }; struct mlx5_roce { … }; struct mlx5_ib_port { … }; struct mlx5_ib_dbg_param { … }; enum mlx5_ib_dbg_cc_types { … }; struct mlx5_ib_dbg_cc_params { … }; enum { … }; struct mlx5_ib_delay_drop { … }; enum mlx5_ib_stages { … }; struct mlx5_ib_stage { … }; #define STAGE_CREATE(_stage, _init, _cleanup) … struct mlx5_ib_profile { … }; struct mlx5_ib_multiport_info { … }; struct mlx5_ib_flow_action { … }; struct mlx5_dm { … }; struct mlx5_read_counters_attr { … }; enum mlx5_ib_counters_type { … }; struct mlx5_ib_mcounters { … }; static inline struct mlx5_ib_mcounters * to_mcounters(struct ib_counters *ibcntrs) { … } int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, bool is_egress, struct mlx5_flow_act *action); struct mlx5_ib_lb_state { … }; struct mlx5_ib_pf_eq { … }; struct mlx5_devx_event_table { … }; struct mlx5_var_table { … }; struct mlx5_port_caps { … }; struct mlx5_special_mkeys { … }; struct mlx5_macsec { … }; struct mlx5_ib_dev { … }; static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) { … } static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) { … } static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) { … } static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) { … } static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) { … } static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) { … } static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) { … } static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) { … } static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) { … } static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) { … } static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) { … } static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) { … } static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) { … } static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) { … } static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) { … } static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) { … } static inline struct mlx5_ib_flow_action * to_mflow_act(struct ib_flow_action *ibact) { … } static inline struct mlx5_user_mmap_entry * to_mmmap(struct rdma_user_mmap_entry *rdma_entry) { … } int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev); int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev); int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, struct mlx5_db *db); void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, struct ib_udata *udata); int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) { … } int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, struct ib_udata *udata); int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr); int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, struct ib_udata *udata); int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata); int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); void mlx5_ib_drain_sq(struct ib_qp *qp); void mlx5_ib_drain_rq(struct ib_qp *qp); int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, size_t buflen, size_t *bc); int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, size_t buflen, size_t *bc); int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, size_t buflen, size_t *bc); int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, struct uverbs_attr_bundle *attrs); int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64 virt_addr, int access_flags, struct ib_udata *udata); struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, u64 length, u64 virt_addr, int fd, int access_flags, struct uverbs_attr_bundle *attrs); int mlx5_ib_advise_mr(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice, u32 flags, struct ib_sge *sg_list, u32 num_sge, struct uverbs_attr_bundle *attrs); int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); int mlx5_ib_dealloc_mw(struct ib_mw *mw); struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, int access_flags); void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, u64 length, u64 virt_addr, int access_flags, struct ib_pd *pd, struct ib_udata *udata); int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, u32 max_num_sg); struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, u32 max_num_sg, u32 max_num_meta_sg); int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, unsigned int *sg_offset); int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, int data_sg_nents, unsigned int *data_sg_offset, struct scatterlist *meta_sg, int meta_sg_nents, unsigned int *meta_sg_offset); int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, const struct ib_wc *in_wc, const struct ib_grh *in_grh, const struct ib_mad *in, struct ib_mad *out, size_t *out_mad_size, u16 *out_mad_pkey_index); int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, __be64 *sys_image_guid); int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, u16 *max_pkeys); int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, u32 *vendor_id); int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey); int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, union ib_gid *gid); int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props); int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props); void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, u64 access_flags); int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); struct mlx5_cache_ent * mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, struct mlx5r_cache_rb_key rb_key, bool persistent_entry); struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int access_flags, int access_mode, int ndescs); int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, struct ib_mr_status *mr_status); struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, struct ib_wq_init_attr *init_attr, struct ib_udata *udata); int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, u32 wq_attr_mask, struct ib_udata *udata); int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, struct ib_rwq_ind_table_init_attr *init_attr, struct ib_udata *udata); int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, struct ib_dm_mr_attr *attr, struct uverbs_attr_bundle *attrs); void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, struct mlx5_data_direct_dev *dev); void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev); void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev); #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); int __init mlx5_ib_odp_init(void); void mlx5_ib_odp_cleanup(void); int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, struct mlx5_ib_mr *mr, int flags); int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice, u32 flags, struct ib_sge *sg_list, u32 num_sge); int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq) { return 0; } static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} static inline int mlx5_ib_odp_init(void) { return 0; } static inline void mlx5_ib_odp_cleanup(void) {} static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) { return 0; } static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, struct mlx5_ib_mr *mr, int flags) {} static inline int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice, u32 flags, struct ib_sge *sg_list, u32 num_sge) { return -EOPNOTSUPP; } static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) { return -EOPNOTSUPP; } static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) { return -EOPNOTSUPP; } #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ extern const struct mmu_interval_notifier_ops mlx5_mn_ops; /* Needed for rep profile */ void __mlx5_ib_remove(struct mlx5_ib_dev *dev, const struct mlx5_ib_profile *profile, int stage); int __mlx5_ib_add(struct mlx5_ib_dev *dev, const struct mlx5_ib_profile *profile); int mlx5_ib_get_vf_config(struct ib_device *device, int vf, u32 port, struct ifla_vf_info *info); int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, u32 port, int state); int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, u32 port, struct ifla_vf_stats *stats); int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, struct ifla_vf_guid *node_guid, struct ifla_vf_guid *port_guid); int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, u64 guid, int type); __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, const struct ib_gid_attr *attr); void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); /* GSI QP helper functions */ int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, struct ib_qp_init_attr *attr); int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, int attr_mask); int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr); int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr); void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn); struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, u32 ib_port_num, u32 *native_port_num); void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, u32 port_num); extern const struct uapi_definition mlx5_ib_devx_defs[]; extern const struct uapi_definition mlx5_ib_flow_defs[]; extern const struct uapi_definition mlx5_ib_qos_defs[]; extern const struct uapi_definition mlx5_ib_std_types_defs[]; extern const struct uapi_definition mlx5_ib_create_cq_defs[]; static inline int is_qp1(enum ib_qp_type qp_type) { … } static inline u32 check_cq_create_flags(u32 flags) { … } static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, u32 *user_index) { … } static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, struct mlx5_ib_create_qp *ucmd, int inlen, u32 *user_index) { … } static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, struct mlx5_ib_create_srq *ucmd, int inlen, u32 *user_index) { … } static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) { … } extern void *xlt_emergency_page; int bfregn_to_uar_index(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, u32 bfregn, bool dyn_bfreg); static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mkey *mmkey) { … } /* deref an mkey that can participate in ODP flow */ static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) { … } /* deref an mkey that can participate in ODP flow and wait for relese */ static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) { … } static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) { … } static inline bool rt_supported(int ts_cap) { … } /* * PCI Peer to Peer is a trainwreck. If no switch is present then things * sometimes work, depending on the pci_distance_p2p logic for excluding broken * root complexes. However if a switch is present in the path, then things get * really ugly depending on how the switch is setup. This table assumes that the * root complex is strict and is validating that all req/reps are matches * perfectly - so any scenario where it sees only half the transaction is a * failure. * * CR/RR/DT ATS RO P2P * 00X X X OK * 010 X X fails (request is routed to root but root never sees comp) * 011 0 X fails (request is routed to root but root never sees comp) * 011 1 X OK * 10X X 1 OK * 101 X 0 fails (completion is routed to root but root didn't see req) * 110 X 0 SLOW * 111 0 0 SLOW * 111 1 0 fails (completion is routed to root but root didn't see req) * 111 1 1 OK * * Unfortunately we cannot reliably know if a switch is present or what the * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. * * For now assume if the umem is a dma_buf then it is P2P. */ static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, struct ib_umem *umem, int access_flags) { … } int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, unsigned int index, const union ib_gid *gid, const struct ib_gid_attr *attr); static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) { … } /* * For mkc users, instead of a page_offset the command has a start_iova which * specifies both the page_offset and the on-the-wire IOVA */ static __always_inline unsigned long mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, u64 iova) { … } #endif /* MLX5_IB_H */
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