/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Authors: Cheng Xu <[email protected]> */ /* Kai Shen <[email protected]> */ /* Copyright (c) 2020-2022, Alibaba Group. */ #ifndef __ERDMA_HW_H__ #define __ERDMA_HW_H__ #include <linux/kernel.h> #include <linux/types.h> /* PCIe device related definition. */ #define ERDMA_PCI_WIDTH … #define ERDMA_FUNC_BAR … #define ERDMA_MISX_BAR … #define ERDMA_BAR_MASK … /* MSI-X related. */ #define ERDMA_NUM_MSIX_VEC … #define ERDMA_MSIX_VECTOR_CMDQ … /* PCIe Bar0 Registers. */ #define ERDMA_REGS_VERSION_REG … #define ERDMA_REGS_DEV_CTRL_REG … #define ERDMA_REGS_DEV_ST_REG … #define ERDMA_REGS_NETDEV_MAC_L_REG … #define ERDMA_REGS_NETDEV_MAC_H_REG … #define ERDMA_REGS_CMDQ_SQ_ADDR_L_REG … #define ERDMA_REGS_CMDQ_SQ_ADDR_H_REG … #define ERDMA_REGS_CMDQ_CQ_ADDR_L_REG … #define ERDMA_REGS_CMDQ_CQ_ADDR_H_REG … #define ERDMA_REGS_CMDQ_DEPTH_REG … #define ERDMA_REGS_CMDQ_EQ_DEPTH_REG … #define ERDMA_REGS_CMDQ_EQ_ADDR_L_REG … #define ERDMA_REGS_CMDQ_EQ_ADDR_H_REG … #define ERDMA_REGS_AEQ_ADDR_L_REG … #define ERDMA_REGS_AEQ_ADDR_H_REG … #define ERDMA_REGS_AEQ_DEPTH_REG … #define ERDMA_REGS_GRP_NUM_REG … #define ERDMA_REGS_AEQ_DB_REG … #define ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG … #define ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG … #define ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG … #define ERDMA_AEQ_DB_HOST_ADDR_REG … #define ERDMA_REGS_STATS_TSO_IN_PKTS_REG … #define ERDMA_REGS_STATS_TSO_OUT_PKTS_REG … #define ERDMA_REGS_STATS_TSO_OUT_BYTES_REG … #define ERDMA_REGS_STATS_TX_DROP_PKTS_REG … #define ERDMA_REGS_STATS_TX_BPS_METER_DROP_PKTS_REG … #define ERDMA_REGS_STATS_TX_PPS_METER_DROP_PKTS_REG … #define ERDMA_REGS_STATS_RX_PKTS_REG … #define ERDMA_REGS_STATS_RX_BYTES_REG … #define ERDMA_REGS_STATS_RX_DROP_PKTS_REG … #define ERDMA_REGS_STATS_RX_BPS_METER_DROP_PKTS_REG … #define ERDMA_REGS_STATS_RX_PPS_METER_DROP_PKTS_REG … #define ERDMA_REGS_CEQ_DB_BASE_REG … #define ERDMA_CMDQ_SQDB_REG … #define ERDMA_CMDQ_CQDB_REG … /* DEV_CTRL_REG details. */ #define ERDMA_REG_DEV_CTRL_RESET_MASK … #define ERDMA_REG_DEV_CTRL_INIT_MASK … /* DEV_ST_REG details. */ #define ERDMA_REG_DEV_ST_RESET_DONE_MASK … #define ERDMA_REG_DEV_ST_INIT_DONE_MASK … /* eRDMA PCIe DBs definition. */ #define ERDMA_BAR_DB_SPACE_BASE … #define ERDMA_BAR_SQDB_SPACE_OFFSET … #define ERDMA_BAR_SQDB_SPACE_SIZE … #define ERDMA_BAR_RQDB_SPACE_OFFSET … #define ERDMA_BAR_RQDB_SPACE_SIZE … #define ERDMA_BAR_CQDB_SPACE_OFFSET … #define ERDMA_SDB_SHARED_PAGE_INDEX … /* Doorbell related. */ #define ERDMA_DB_SIZE … #define ERDMA_CQDB_IDX_MASK … #define ERDMA_CQDB_CQN_MASK … #define ERDMA_CQDB_ARM_MASK … #define ERDMA_CQDB_SOL_MASK … #define ERDMA_CQDB_CMDSN_MASK … #define ERDMA_CQDB_CI_MASK … #define ERDMA_EQDB_ARM_MASK … #define ERDMA_EQDB_CI_MASK … #define ERDMA_PAGE_SIZE_SUPPORT … /* Hardware page size definition */ #define ERDMA_HW_PAGE_SHIFT … #define ERDMA_HW_PAGE_SIZE … /* WQE related. */ #define EQE_SIZE … #define EQE_SHIFT … #define RQE_SIZE … #define RQE_SHIFT … #define CQE_SIZE … #define CQE_SHIFT … #define SQEBB_SIZE … #define SQEBB_SHIFT … #define SQEBB_MASK … #define SQEBB_ALIGN(size) … #define SQEBB_COUNT(size) … #define ERDMA_MAX_SQE_SIZE … #define ERDMA_MAX_WQEBB_PER_SQE … /* CMDQ related. */ #define ERDMA_CMDQ_MAX_OUTSTANDING … #define ERDMA_CMDQ_SQE_SIZE … /* cmdq sub module definition. */ enum CMDQ_WQE_SUB_MOD { … }; enum CMDQ_RDMA_OPCODE { … }; enum CMDQ_COMMON_OPCODE { … }; /* cmdq-SQE HDR */ #define ERDMA_CMD_HDR_WQEBB_CNT_MASK … #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK … #define ERDMA_CMD_HDR_SUB_MOD_MASK … #define ERDMA_CMD_HDR_OPCODE_MASK … #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK … struct erdma_cmdq_destroy_cq_req { … }; #define ERDMA_EQ_TYPE_AEQ … #define ERDMA_EQ_TYPE_CEQ … struct erdma_cmdq_create_eq_req { … }; struct erdma_cmdq_destroy_eq_req { … }; /* config device cfg */ #define ERDMA_CMD_CONFIG_DEVICE_PS_EN_MASK … #define ERDMA_CMD_CONFIG_DEVICE_PGSHIFT_MASK … struct erdma_cmdq_config_device_req { … }; struct erdma_cmdq_config_mtu_req { … }; /* ext db requests(alloc and free) cfg */ #define ERDMA_CMD_EXT_DB_CQ_EN_MASK … #define ERDMA_CMD_EXT_DB_RQ_EN_MASK … #define ERDMA_CMD_EXT_DB_SQ_EN_MASK … struct erdma_cmdq_ext_db_req { … }; /* alloc db response qword 0 definition */ #define ERDMA_CMD_ALLOC_DB_RESP_RDB_MASK … #define ERDMA_CMD_ALLOC_DB_RESP_CDB_MASK … #define ERDMA_CMD_ALLOC_DB_RESP_SDB_MASK … /* create_cq cfg0 */ #define ERDMA_CMD_CREATE_CQ_DEPTH_MASK … #define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK … #define ERDMA_CMD_CREATE_CQ_CQN_MASK … /* create_cq cfg1 */ #define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK … #define ERDMA_CMD_CREATE_CQ_MTT_LEVEL_MASK … #define ERDMA_CMD_CREATE_CQ_MTT_DB_CFG_MASK … #define ERDMA_CMD_CREATE_CQ_EQN_MASK … /* create_cq cfg2 */ #define ERDMA_CMD_CREATE_CQ_DB_CFG_MASK … struct erdma_cmdq_create_cq_req { … }; /* regmr/deregmr cfg0 */ #define ERDMA_CMD_MR_VALID_MASK … #define ERDMA_CMD_MR_VERSION_MASK … #define ERDMA_CMD_MR_KEY_MASK … #define ERDMA_CMD_MR_MPT_IDX_MASK … /* regmr cfg1 */ #define ERDMA_CMD_REGMR_PD_MASK … #define ERDMA_CMD_REGMR_TYPE_MASK … #define ERDMA_CMD_REGMR_RIGHT_MASK … /* regmr cfg2 */ #define ERDMA_CMD_REGMR_PAGESIZE_MASK … #define ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK … #define ERDMA_CMD_REGMR_MTT_LEVEL_MASK … #define ERDMA_CMD_REGMR_MTT_CNT_MASK … struct erdma_cmdq_reg_mr_req { … }; struct erdma_cmdq_dereg_mr_req { … }; /* modify qp cfg */ #define ERDMA_CMD_MODIFY_QP_STATE_MASK … #define ERDMA_CMD_MODIFY_QP_CC_MASK … #define ERDMA_CMD_MODIFY_QP_QPN_MASK … struct erdma_cmdq_modify_qp_req { … }; /* create qp cfg0 */ #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK … #define ERDMA_CMD_CREATE_QP_QPN_MASK … /* create qp cfg1 */ #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK … #define ERDMA_CMD_CREATE_QP_PD_MASK … /* create qp cqn_mtt_cfg */ #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK … #define ERDMA_CMD_CREATE_QP_DB_CFG_MASK … #define ERDMA_CMD_CREATE_QP_CQN_MASK … /* create qp mtt_cfg */ #define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK … #define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK … #define ERDMA_CMD_CREATE_QP_MTT_LEVEL_MASK … /* create qp db cfg */ #define ERDMA_CMD_CREATE_QP_SQDB_CFG_MASK … #define ERDMA_CMD_CREATE_QP_RQDB_CFG_MASK … #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK … struct erdma_cmdq_create_qp_req { … }; struct erdma_cmdq_destroy_qp_req { … }; struct erdma_cmdq_reflush_req { … }; #define ERDMA_HW_RESP_SIZE … struct erdma_cmdq_query_req { … }; #define ERDMA_HW_RESP_MAGIC … struct erdma_cmdq_query_resp_hdr { … }; struct erdma_cmdq_query_stats_resp { … }; /* cap qword 0 definition */ #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK … #define ERDMA_CMD_DEV_CAP_FLAGS_MASK … #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK … #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK … /* cap qword 1 definition */ #define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK … #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK … #define ERDMA_CMD_DEV_CAP_QBLOCK_MASK … #define ERDMA_CMD_DEV_CAP_MAX_MW_MASK … #define ERDMA_NQP_PER_QBLOCK … enum { … }; #define ERDMA_CMD_INFO0_FW_VER_MASK … /* CQE hdr */ #define ERDMA_CQE_HDR_OWNER_MASK … #define ERDMA_CQE_HDR_OPCODE_MASK … #define ERDMA_CQE_HDR_QTYPE_MASK … #define ERDMA_CQE_HDR_SYNDROME_MASK … #define ERDMA_CQE_QTYPE_SQ … #define ERDMA_CQE_QTYPE_RQ … #define ERDMA_CQE_QTYPE_CMDQ … struct erdma_cqe { … }; struct erdma_sge { … }; /* Receive Queue Element */ struct erdma_rqe { … }; /* SQE */ #define ERDMA_SQE_HDR_SGL_LEN_MASK … #define ERDMA_SQE_HDR_WQEBB_CNT_MASK … #define ERDMA_SQE_HDR_QPN_MASK … #define ERDMA_SQE_HDR_OPCODE_MASK … #define ERDMA_SQE_HDR_DWQE_MASK … #define ERDMA_SQE_HDR_INLINE_MASK … #define ERDMA_SQE_HDR_FENCE_MASK … #define ERDMA_SQE_HDR_SE_MASK … #define ERDMA_SQE_HDR_CE_MASK … #define ERDMA_SQE_HDR_WQEBB_INDEX_MASK … /* REG MR attrs */ #define ERDMA_SQE_MR_ACCESS_MASK … #define ERDMA_SQE_MR_MTT_TYPE_MASK … #define ERDMA_SQE_MR_MTT_CNT_MASK … struct erdma_write_sqe { … }; struct erdma_send_sqe { … }; struct erdma_readreq_sqe { … }; struct erdma_atomic_sqe { … }; struct erdma_reg_mr_sqe { … }; /* EQ related. */ #define ERDMA_DEFAULT_EQ_DEPTH … /* ceqe */ #define ERDMA_CEQE_HDR_DB_MASK … #define ERDMA_CEQE_HDR_PI_MASK … #define ERDMA_CEQE_HDR_O_MASK … #define ERDMA_CEQE_HDR_CQN_MASK … /* aeqe */ #define ERDMA_AEQE_HDR_O_MASK … #define ERDMA_AEQE_HDR_TYPE_MASK … #define ERDMA_AEQE_HDR_SUBTYPE_MASK … #define ERDMA_AE_TYPE_QP_FATAL_EVENT … #define ERDMA_AE_TYPE_QP_ERQ_ERR_EVENT … #define ERDMA_AE_TYPE_ACC_ERR_EVENT … #define ERDMA_AE_TYPE_CQ_ERR … #define ERDMA_AE_TYPE_OTHER_ERROR … struct erdma_aeqe { … }; enum erdma_opcode { … }; enum erdma_wc_status { … }; enum erdma_vendor_err { … }; #endif
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