linux/drivers/crypto/aspeed/aspeed-hace.h

/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASPEED_HACE_H__
#define __ASPEED_HACE_H__

#include <crypto/aes.h>
#include <crypto/engine.h>
#include <crypto/hash.h>
#include <crypto/sha2.h>
#include <linux/bits.h>
#include <linux/compiler_attributes.h>
#include <linux/interrupt.h>
#include <linux/types.h>

/*****************************
 *                           *
 * HACE register definitions *
 *                           *
 * ***************************/
#define ASPEED_HACE_SRC
#define ASPEED_HACE_DEST
#define ASPEED_HACE_CONTEXT
#define ASPEED_HACE_DATA_LEN
#define ASPEED_HACE_CMD

/* G5 */
#define ASPEED_HACE_TAG
/* G6 */
#define ASPEED_HACE_GCM_ADD_LEN
#define ASPEED_HACE_GCM_TAG_BASE_ADDR

#define ASPEED_HACE_STS

#define ASPEED_HACE_HASH_SRC
#define ASPEED_HACE_HASH_DIGEST_BUFF
#define ASPEED_HACE_HASH_KEY_BUFF
#define ASPEED_HACE_HASH_DATA_LEN
#define ASPEED_HACE_HASH_CMD

/* crypto cmd */
#define HACE_CMD_SINGLE_DES
#define HACE_CMD_TRIPLE_DES
#define HACE_CMD_AES_SELECT
#define HACE_CMD_DES_SELECT
#define HACE_CMD_ISR_EN
#define HACE_CMD_CONTEXT_SAVE_ENABLE
#define HACE_CMD_CONTEXT_SAVE_DISABLE
#define HACE_CMD_AES
#define HACE_CMD_DES
#define HACE_CMD_RC4
#define HACE_CMD_DECRYPT
#define HACE_CMD_ENCRYPT

#define HACE_CMD_ECB
#define HACE_CMD_CBC
#define HACE_CMD_CFB
#define HACE_CMD_OFB
#define HACE_CMD_CTR
#define HACE_CMD_OP_MODE_MASK

#define HACE_CMD_AES128
#define HACE_CMD_AES192
#define HACE_CMD_AES256
#define HACE_CMD_OP_CASCADE
#define HACE_CMD_OP_INDEPENDENT

/* G5 */
#define HACE_CMD_RI_WO_DATA_ENABLE
#define HACE_CMD_RI_WO_DATA_DISABLE
#define HACE_CMD_CONTEXT_LOAD_ENABLE
#define HACE_CMD_CONTEXT_LOAD_DISABLE
/* G6 */
#define HACE_CMD_AES_KEY_FROM_OTP
#define HACE_CMD_GHASH_TAG_XOR_EN
#define HACE_CMD_GHASH_PAD_LEN_INV
#define HACE_CMD_GCM_TAG_ADDR_SEL
#define HACE_CMD_MBUS_REQ_SYNC_EN
#define HACE_CMD_DES_SG_CTRL
#define HACE_CMD_SRC_SG_CTRL
#define HACE_CMD_CTR_IV_AES_96
#define HACE_CMD_CTR_IV_DES_32
#define HACE_CMD_CTR_IV_AES_64
#define HACE_CMD_CTR_IV_AES_32
#define HACE_CMD_AES_KEY_HW_EXP
#define HACE_CMD_GCM

/* interrupt status reg */
#define HACE_CRYPTO_ISR
#define HACE_HASH_ISR
#define HACE_HASH_BUSY

/* hash cmd reg */
#define HASH_CMD_MBUS_REQ_SYNC_EN
#define HASH_CMD_HASH_SRC_SG_CTRL
#define HASH_CMD_SHA512_224
#define HASH_CMD_SHA512_256
#define HASH_CMD_SHA384
#define HASH_CMD_SHA512
#define HASH_CMD_INT_ENABLE
#define HASH_CMD_HMAC
#define HASH_CMD_ACC_MODE
#define HASH_CMD_HMAC_KEY
#define HASH_CMD_SHA1
#define HASH_CMD_SHA224
#define HASH_CMD_SHA256
#define HASH_CMD_SHA512_SER
#define HASH_CMD_SHA_SWAP

#define HASH_SG_LAST_LIST

#define CRYPTO_FLAGS_BUSY

#define SHA_OP_UPDATE
#define SHA_OP_FINAL

#define SHA_FLAGS_SHA1
#define SHA_FLAGS_SHA224
#define SHA_FLAGS_SHA256
#define SHA_FLAGS_SHA384
#define SHA_FLAGS_SHA512
#define SHA_FLAGS_SHA512_224
#define SHA_FLAGS_SHA512_256
#define SHA_FLAGS_HMAC
#define SHA_FLAGS_FINUP
#define SHA_FLAGS_MASK

#define ASPEED_CRYPTO_SRC_DMA_BUF_LEN
#define ASPEED_CRYPTO_DST_DMA_BUF_LEN
#define ASPEED_CRYPTO_GCM_TAG_OFFSET
#define ASPEED_HASH_SRC_DMA_BUF_LEN
#define ASPEED_HASH_QUEUE_LENGTH

#define HACE_CMD_IV_REQUIRE

struct aspeed_hace_dev;
struct scatterlist;

aspeed_hace_fn_t;

struct aspeed_sg_list {};

struct aspeed_engine_hash {};

struct aspeed_sha_hmac_ctx {};

struct aspeed_sham_ctx {};

struct aspeed_sham_reqctx {};

struct aspeed_engine_crypto {};

struct aspeed_cipher_ctx {};

struct aspeed_cipher_reqctx {};

struct aspeed_hace_dev {};

struct aspeed_hace_alg {};

enum aspeed_version {};

#define ast_hace_write(hace, val, offset)
#define ast_hace_read(hace, offset)

void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);

#endif