/* SPDX-License-Identifier: GPL-2.0-only */ /* * AMD Cryptographic Coprocessor (CCP) driver * * Copyright (C) 2013,2017 Advanced Micro Devices, Inc. * * Author: Tom Lendacky <[email protected]> * Author: Gary R Hook <[email protected]> */ #ifndef __CCP_DEV_H__ #define __CCP_DEV_H__ #include <linux/device.h> #include <linux/spinlock.h> #include <linux/mutex.h> #include <linux/list.h> #include <linux/wait.h> #include <linux/dma-direction.h> #include <linux/dmapool.h> #include <linux/hw_random.h> #include <linux/bitops.h> #include <linux/interrupt.h> #include <linux/irqreturn.h> #include <linux/dmaengine.h> #include "sp-dev.h" #define MAX_CCP_NAME_LEN … #define MAX_DMAPOOL_NAME_LEN … #define MAX_HW_QUEUES … #define MAX_CMD_QLEN … #define TRNG_RETRIES … #define CACHE_NONE … #define CACHE_WB_NO_ALLOC … /****** Register Mappings ******/ #define Q_MASK_REG … #define TRNG_OUT_REG … #define IRQ_MASK_REG … #define IRQ_STATUS_REG … #define DEL_CMD_Q_JOB … #define DEL_Q_ACTIVE … #define DEL_Q_ID_SHIFT … #define CMD_REQ0 … #define CMD_REQ_INCR … #define CMD_Q_STATUS_BASE … #define CMD_Q_INT_STATUS_BASE … #define CMD_Q_STATUS_INCR … #define CMD_Q_CACHE_BASE … #define CMD_Q_CACHE_INC … #define CMD_Q_ERROR(__qs) … #define CMD_Q_DEPTH(__qs) … /* ------------------------ CCP Version 5 Specifics ------------------------ */ #define CMD5_QUEUE_MASK_OFFSET … #define CMD5_QUEUE_PRIO_OFFSET … #define CMD5_REQID_CONFIG_OFFSET … #define CMD5_CMD_TIMEOUT_OFFSET … #define LSB_PUBLIC_MASK_LO_OFFSET … #define LSB_PUBLIC_MASK_HI_OFFSET … #define LSB_PRIVATE_MASK_LO_OFFSET … #define LSB_PRIVATE_MASK_HI_OFFSET … #define CMD5_PSP_CCP_VERSION … #define CMD5_Q_CONTROL_BASE … #define CMD5_Q_TAIL_LO_BASE … #define CMD5_Q_HEAD_LO_BASE … #define CMD5_Q_INT_ENABLE_BASE … #define CMD5_Q_INTERRUPT_STATUS_BASE … #define CMD5_Q_STATUS_BASE … #define CMD5_Q_INT_STATUS_BASE … #define CMD5_Q_DMA_STATUS_BASE … #define CMD5_Q_DMA_READ_STATUS_BASE … #define CMD5_Q_DMA_WRITE_STATUS_BASE … #define CMD5_Q_ABORT_BASE … #define CMD5_Q_AX_CACHE_BASE … #define CMD5_CONFIG_0_OFFSET … #define CMD5_TRNG_CTL_OFFSET … #define CMD5_AES_MASK_OFFSET … #define CMD5_CLK_GATE_CTL_OFFSET … /* Address offset between two virtual queue registers */ #define CMD5_Q_STATUS_INCR … /* Bit masks */ #define CMD5_Q_RUN … #define CMD5_Q_HALT … #define CMD5_Q_MEM_LOCATION … #define CMD5_Q_SIZE … #define CMD5_Q_SHIFT … #define COMMANDS_PER_QUEUE … #define QUEUE_SIZE_VAL … #define Q_PTR_MASK … #define Q_DESC_SIZE … #define Q_SIZE(n) … #define INT_COMPLETION … #define INT_ERROR … #define INT_QUEUE_STOPPED … #define INT_EMPTY_QUEUE … #define SUPPORTED_INTERRUPTS … #define LSB_REGION_WIDTH … #define MAX_LSB_CNT … #define LSB_SIZE … #define LSB_ITEM_SIZE … #define PLSB_MAP_SIZE … #define SLSB_MAP_SIZE … #define LSB_ENTRY_NUMBER(LSB_ADDR) … /* ------------------------ CCP Version 3 Specifics ------------------------ */ #define REQ0_WAIT_FOR_WRITE … #define REQ0_INT_ON_COMPLETE … #define REQ0_STOP_ON_COMPLETE … #define REQ0_CMD_Q_SHIFT … #define REQ0_JOBID_SHIFT … /****** REQ1 Related Values ******/ #define REQ1_PROTECT_SHIFT … #define REQ1_ENGINE_SHIFT … #define REQ1_KEY_KSB_SHIFT … #define REQ1_EOM … #define REQ1_INIT … /* AES Related Values */ #define REQ1_AES_TYPE_SHIFT … #define REQ1_AES_MODE_SHIFT … #define REQ1_AES_ACTION_SHIFT … #define REQ1_AES_CFB_SIZE_SHIFT … /* XTS-AES Related Values */ #define REQ1_XTS_AES_SIZE_SHIFT … /* SHA Related Values */ #define REQ1_SHA_TYPE_SHIFT … /* RSA Related Values */ #define REQ1_RSA_MOD_SIZE_SHIFT … /* Pass-Through Related Values */ #define REQ1_PT_BW_SHIFT … #define REQ1_PT_BS_SHIFT … /* ECC Related Values */ #define REQ1_ECC_AFFINE_CONVERT … #define REQ1_ECC_FUNCTION_SHIFT … /****** REQ4 Related Values ******/ #define REQ4_KSB_SHIFT … #define REQ4_MEMTYPE_SHIFT … /****** REQ6 Related Values ******/ #define REQ6_MEMTYPE_SHIFT … /****** Key Storage Block ******/ #define KSB_START … #define KSB_END … #define KSB_COUNT … #define CCP_SB_BITS … #define CCP_JOBID_MASK … /* ------------------------ General CCP Defines ------------------------ */ #define CCP_DMA_DFLT … #define CCP_DMA_PRIV … #define CCP_DMA_PUB … #define CCP_DMAPOOL_MAX_SIZE … #define CCP_DMAPOOL_ALIGN … #define CCP_REVERSE_BUF_SIZE … #define CCP_AES_KEY_SB_COUNT … #define CCP_AES_CTX_SB_COUNT … #define CCP_XTS_AES_KEY_SB_COUNT … #define CCP5_XTS_AES_KEY_SB_COUNT … #define CCP_XTS_AES_CTX_SB_COUNT … #define CCP_DES3_KEY_SB_COUNT … #define CCP_DES3_CTX_SB_COUNT … #define CCP_SHA_SB_COUNT … #define CCP_RSA_MAX_WIDTH … #define CCP5_RSA_MAX_WIDTH … #define CCP_PASSTHRU_BLOCKSIZE … #define CCP_PASSTHRU_MASKSIZE … #define CCP_PASSTHRU_SB_COUNT … #define CCP_ECC_MODULUS_BYTES … #define CCP_ECC_MAX_OPERANDS … #define CCP_ECC_MAX_OUTPUTS … #define CCP_ECC_SRC_BUF_SIZE … #define CCP_ECC_DST_BUF_SIZE … #define CCP_ECC_OPERAND_SIZE … #define CCP_ECC_OUTPUT_SIZE … #define CCP_ECC_RESULT_OFFSET … #define CCP_ECC_RESULT_SUCCESS … #define CCP_SB_BYTES … struct ccp_op; struct ccp_device; struct ccp_cmd; struct ccp_fns; struct ccp_dma_cmd { … }; struct ccp_dma_desc { … }; struct ccp_dma_chan { … }; struct ccp_cmd_queue { … } ____cacheline_aligned; struct ccp_device { … }; enum ccp_memtype { … }; #define CCP_MEMTYPE_LSB … struct ccp_dma_info { … } __packed __aligned(…); struct ccp_dm_workarea { … }; struct ccp_sg_workarea { … }; struct ccp_data { … }; struct ccp_mem { … }; struct ccp_aes_op { … }; struct ccp_xts_aes_op { … }; struct ccp_des3_op { … }; struct ccp_sha_op { … }; struct ccp_rsa_op { … }; struct ccp_passthru_op { … }; struct ccp_ecc_op { … }; struct ccp_op { … }; static inline u32 ccp_addr_lo(struct ccp_dma_info *info) { … } static inline u32 ccp_addr_hi(struct ccp_dma_info *info) { … } /** * descriptor for version 5 CPP commands * 8 32-bit words: * word 0: function; engine; control bits * word 1: length of source data * word 2: low 32 bits of source pointer * word 3: upper 16 bits of source pointer; source memory type * word 4: low 32 bits of destination pointer * word 5: upper 16 bits of destination pointer; destination memory type * word 6: low 32 bits of key pointer * word 7: upper 16 bits of key pointer; key memory type */ struct dword0 { … }; struct dword3 { … }; dword4; dword5; struct dword7 { … }; struct ccp5_desc { … }; void ccp_add_device(struct ccp_device *ccp); void ccp_del_device(struct ccp_device *ccp); extern void ccp_log_error(struct ccp_device *, unsigned int); struct ccp_device *ccp_alloc_struct(struct sp_device *sp); bool ccp_queues_suspended(struct ccp_device *ccp); int ccp_cmd_queue_thread(void *data); int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait); int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd); int ccp_register_rng(struct ccp_device *ccp); void ccp_unregister_rng(struct ccp_device *ccp); int ccp_dmaengine_register(struct ccp_device *ccp); void ccp_dmaengine_unregister(struct ccp_device *ccp); void ccp5_debugfs_setup(struct ccp_device *ccp); void ccp5_debugfs_destroy(void); /* Structure for computation functions that are device-specific */ struct ccp_actions { … }; extern const struct ccp_vdata ccpv3_platform; extern const struct ccp_vdata ccpv3; extern const struct ccp_vdata ccpv5a; extern const struct ccp_vdata ccpv5b; #endif
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