linux/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

/* SPDX-License-Identifier: GPL-2.0-only
 * Copyright (C) 2020 Marvell.
 */

#ifndef __OTX2_CPT_COMMON_H
#define __OTX2_CPT_COMMON_H

#include <linux/pci.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/crypto.h>
#include <net/devlink.h>
#include "otx2_cpt_hw_types.h"
#include "rvu.h"
#include "mbox.h"

#define OTX2_CPT_MAX_VFS_NUM …
#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) …
#define OTX2_CPT_RVU_PFFUNC(pf, func) …

#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP …
#define OTX2_CPT_NAME_LENGTH …
#define OTX2_CPT_DMA_MINALIGN …

/* HW capability flags */
#define CN10K_MBOX …
#define CN10K_LMTST …

#define BAD_OTX2_CPT_ENG_TYPE …

enum otx2_cpt_eng_type { … };

/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
#define MBOX_MSG_RX_INLINE_IPSEC_LF_CFG …
#define MBOX_MSG_GET_ENG_GRP_NUM …
#define MBOX_MSG_GET_CAPS …
#define MBOX_MSG_GET_KVF_LIMITS …

/*
 * Message request to config cpt lf for inline inbound ipsec.
 * This message is only used between CPT PF <-> CPT VF
 */
struct otx2_cpt_rx_inline_lf_cfg { … };

/*
 * Message request and response to get engine group number
 * which has attached a given type of engines (SE, AE, IE)
 * This messages are only used between CPT PF <=> CPT VF
 */
struct otx2_cpt_egrp_num_msg { … };

struct otx2_cpt_egrp_num_rsp { … };

/*
 * Message request and response to get kernel crypto limits
 * This messages are only used between CPT PF <-> CPT VF
 */
struct otx2_cpt_kvf_limits_msg { … };

struct otx2_cpt_kvf_limits_rsp { … };

/* CPT HW capabilities */
otx2_cpt_eng_caps;

/*
 * Message request and response to get HW capabilities for each
 * engine type (SE, IE, AE).
 * This messages are only used between CPT PF <=> CPT VF
 */
struct otx2_cpt_caps_msg { … };

struct otx2_cpt_caps_rsp { … };

static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
				    u64 offs, u64 val)
{ … }

static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
				  u64 offs)
{ … }

static inline bool is_dev_otx2(struct pci_dev *pdev)
{ … }

static inline bool is_dev_cn10ka(struct pci_dev *pdev)
{ … }

static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev)
{ … }

static inline bool is_dev_cn10kb(struct pci_dev *pdev)
{ … }

static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
{ … }

static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
					unsigned long *cap_flag)
{ … }

static inline bool cpt_is_errata_38550_exists(struct pci_dev *pdev)
{ … }

static inline bool cpt_feature_sgv2(struct pci_dev *pdev)
{ … }

int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);

int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,
				  struct pci_dev *pdev);
int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
			      u64 reg, u64 val, int blkaddr);
int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
			 u64 reg, u64 *val, int blkaddr);
int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
			  u64 reg, u64 val, int blkaddr);
struct otx2_cptlfs_info;
int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);
int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);

#endif /* __OTX2_CPT_COMMON_H */