linux/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h

/* SPDX-License-Identifier: GPL-2.0-only
 * Copyright (C) 2020 Marvell.
 */

#ifndef __OTX2_CPT_REQMGR_H
#define __OTX2_CPT_REQMGR_H

#include "otx2_cpt_common.h"

/* Completion code size and initial value */
#define OTX2_CPT_COMPLETION_CODE_SIZE
#define OTX2_CPT_COMPLETION_CODE_INIT
/*
 * Maximum total number of SG buffers is 100, we divide it equally
 * between input and output
 */
#define OTX2_CPT_MAX_SG_IN_CNT
#define OTX2_CPT_MAX_SG_OUT_CNT

/* DMA mode direct or SG */
#define OTX2_CPT_DMA_MODE_DIRECT
#define OTX2_CPT_DMA_MODE_SG

/* Context source CPTR or DPTR */
#define OTX2_CPT_FROM_CPTR
#define OTX2_CPT_FROM_DPTR

#define OTX2_CPT_MAX_REQ_SIZE

#define SG_COMPS_MAX
#define SGV2_COMPS_MAX

#define SG_COMP_3
#define SG_COMP_2
#define SG_COMP_1

otx2_cpt_opcode;

struct otx2_cptvf_request {};

/*
 * CPT_INST_S software command definitions
 * Words EI (0-3)
 */
otx2_cpt_iq_cmd_word0;

otx2_cpt_iq_cmd_word3;

struct otx2_cpt_iq_command {};

struct otx2_cpt_pending_entry {};

struct otx2_cpt_pending_queue {};

struct otx2_cpt_buf_ptr {};

otx2_cpt_ctrl_info;

struct otx2_cpt_req_info {};

struct otx2_cpt_inst_info {};

struct otx2_cpt_sglist_component {};

struct cn10kb_cpt_sglist_component {};

static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,
					 struct otx2_cpt_inst_info *info)
{}

static inline int setup_sgio_components(struct pci_dev *pdev,
					struct otx2_cpt_buf_ptr *list,
					int buf_count, u8 *buffer)
{}

static inline int sgv2io_components_setup(struct pci_dev *pdev,
					  struct otx2_cpt_buf_ptr *list,
					  int buf_count, u8 *buffer)
{}

static inline struct otx2_cpt_inst_info *
cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
		       gfp_t gfp)
{}

/* SG list header size in bytes */
#define SG_LIST_HDR_SIZE
static inline struct otx2_cpt_inst_info *
otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
		    gfp_t gfp)
{}

struct otx2_cptlf_wqe;
int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
			int cpu_num);
void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe);
int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev);

#endif /* __OTX2_CPT_REQMGR_H */