/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ /* Copyright(c) 2014 - 2020 Intel Corporation */ #ifndef ADF_ACCEL_DEVICES_H_ #define ADF_ACCEL_DEVICES_H_ #include <linux/interrupt.h> #include <linux/module.h> #include <linux/list.h> #include <linux/io.h> #include <linux/pci.h> #include <linux/ratelimit.h> #include <linux/types.h> #include <linux/qat/qat_mig_dev.h> #include "adf_cfg_common.h" #include "adf_rl.h" #include "adf_telemetry.h" #include "adf_pfvf_msg.h" #include "icp_qat_hw.h" #define ADF_DH895XCC_DEVICE_NAME … #define ADF_DH895XCCVF_DEVICE_NAME … #define ADF_C62X_DEVICE_NAME … #define ADF_C62XVF_DEVICE_NAME … #define ADF_C3XXX_DEVICE_NAME … #define ADF_C3XXXVF_DEVICE_NAME … #define ADF_4XXX_DEVICE_NAME … #define ADF_420XX_DEVICE_NAME … #define ADF_4XXX_PCI_DEVICE_ID … #define ADF_4XXXIOV_PCI_DEVICE_ID … #define ADF_401XX_PCI_DEVICE_ID … #define ADF_401XXIOV_PCI_DEVICE_ID … #define ADF_402XX_PCI_DEVICE_ID … #define ADF_402XXIOV_PCI_DEVICE_ID … #define ADF_420XX_PCI_DEVICE_ID … #define ADF_420XXIOV_PCI_DEVICE_ID … #define ADF_DEVICE_FUSECTL_OFFSET … #define ADF_DEVICE_LEGFUSE_OFFSET … #define ADF_DEVICE_FUSECTL_MASK … #define ADF_PCI_MAX_BARS … #define ADF_DEVICE_NAME_LENGTH … #define ADF_ETR_MAX_RINGS_PER_BANK … #define ADF_MAX_MSIX_VECTOR_NAME … #define ADF_DEVICE_NAME_PREFIX … enum adf_accel_capabilities { … }; struct adf_bar { … }; struct adf_irq { … }; struct adf_accel_msix { … }; struct adf_accel_pci { … }; enum dev_state { … }; enum dev_sku_info { … }; enum ras_errors { … }; struct adf_error_counters { … }; static inline const char *get_sku_info(enum dev_sku_info info) { … } struct adf_hw_device_class { … }; struct arb_info { … }; struct admin_info { … }; struct ring_config { … }; struct bank_state { … }; struct adf_hw_csr_ops { … }; struct adf_cfg_device_data; struct adf_accel_dev; struct adf_etr_data; struct adf_etr_ring_data; struct adf_ras_ops { … }; struct adf_pfvf_ops { … }; struct adf_dc_ops { … }; struct qat_migdev_ops { … }; struct adf_dev_err_mask { … }; struct adf_hw_device_data { … }; /* CSR write macro */ #define ADF_CSR_WR(csr_base, csr_offset, val) … /* CSR read macro */ #define ADF_CSR_RD(csr_base, csr_offset) … #define ADF_CFG_NUM_SERVICES … #define ADF_SRV_TYPE_BIT_LEN … #define ADF_SRV_TYPE_MASK … #define ADF_AE_ADMIN_THREAD … #define ADF_NUM_THREADS_PER_AE … #define ADF_NUM_PKE_STRAND … #define ADF_AE_STRAND0_THREAD … #define ADF_AE_STRAND1_THREAD … #define GET_DEV(accel_dev) … #define GET_BARS(accel_dev) … #define GET_HW_DATA(accel_dev) … #define GET_MAX_BANKS(accel_dev) … #define GET_NUM_RINGS_PER_BANK(accel_dev) … #define GET_SRV_TYPE(accel_dev, idx) … #define GET_ERR_MASK(accel_dev) … #define GET_MAX_ACCELENGINES(accel_dev) … #define GET_CSR_OPS(accel_dev) … #define GET_PFVF_OPS(accel_dev) … #define GET_DC_OPS(accel_dev) … #define GET_VFMIG_OPS(accel_dev) … #define GET_TL_DATA(accel_dev) … #define accel_to_pci_dev(accel_ptr) … struct adf_admin_comms; struct icp_qat_fw_loader_handle; struct adf_fw_loader_data { … }; struct adf_accel_vf_info { … }; struct adf_dc_data { … }; struct adf_pm { … }; struct adf_sysfs { … }; struct adf_accel_dev { … }; #endif
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