linux/drivers/crypto/intel/qat/qat_common/adf_gen4_pm.h

/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
/* Copyright(c) 2022 Intel Corporation */
#ifndef ADF_GEN4_PM_H
#define ADF_GEN4_PM_H

#include <linux/bits.h>

struct adf_accel_dev;

enum qat_pm_host_msg { … };

/* Power management registers */
#define ADF_GEN4_PM_HOST_MSG …

/* Power management */
#define ADF_GEN4_PM_POLL_DELAY_US …
#define ADF_GEN4_PM_POLL_TIMEOUT_US …
#define ADF_GEN4_PM_MSG_POLL_DELAY_US …
#define ADF_GEN4_PM_STATUS …
#define ADF_GEN4_PM_INTERRUPT …

/* Power management source in ERRSOU2 and ERRMSK2 */
#define ADF_GEN4_PM_SOU …

#define ADF_GEN4_PM_IDLE_INT_EN …
#define ADF_GEN4_PM_THROTTLE_INT_EN …
#define ADF_GEN4_PM_DRV_ACTIVE …
#define ADF_GEN4_PM_INIT_STATE …
#define ADF_GEN4_PM_INT_EN_DEFAULT …

#define ADF_GEN4_PM_THR_STS …
#define ADF_GEN4_PM_IDLE_STS …
#define ADF_GEN4_PM_FW_INT_STS …
#define ADF_GEN4_PM_INT_STS_MASK …

#define ADF_GEN4_PM_MSG_PENDING …
#define ADF_GEN4_PM_MSG_PAYLOAD_BIT_MASK …

#define ADF_GEN4_PM_DEFAULT_IDLE_FILTER …
#define ADF_GEN4_PM_MAX_IDLE_FILTER …
#define ADF_GEN4_PM_DEFAULT_IDLE_SUPPORT …

/* PM CSRs fields masks */
#define ADF_GEN4_PM_DOMAIN_POWER_GATED_MASK …
#define ADF_GEN4_PM_SSM_PM_ENABLE_MASK …
#define ADF_GEN4_PM_IDLE_FILTER_MASK …
#define ADF_GEN4_PM_IDLE_ENABLE_MASK …
#define ADF_GEN4_PM_ENABLE_PM_MASK …
#define ADF_GEN4_PM_ENABLE_PM_IDLE_MASK …
#define ADF_GEN4_PM_ENABLE_DEEP_PM_IDLE_MASK …
#define ADF_GEN4_PM_CURRENT_WP_MASK …
#define ADF_GEN4_PM_CPM_PM_STATE_MASK …
#define ADF_GEN4_PM_PENDING_WP_MASK …
#define ADF_GEN4_PM_THR_VALUE_MASK …
#define ADF_GEN4_PM_MIN_PWR_ACK_MASK …
#define ADF_GEN4_PM_MIN_PWR_ACK_PENDING_MASK …
#define ADF_GEN4_PM_CPR_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_CPR_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_XLT_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_XLT_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_DCPR_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_DCPR_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_PKE_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_PKE_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_WAT_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_WAT_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_WCP_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_WCP_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_UCS_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_UCS_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_CPH_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_CPH_MANAGED_COUNT_MASK …
#define ADF_GEN4_PM_ATH_ACTIVE_COUNT_MASK …
#define ADF_GEN4_PM_ATH_MANAGED_COUNT_MASK …

int adf_gen4_enable_pm(struct adf_accel_dev *accel_dev);
bool adf_gen4_handle_pm_interrupt(struct adf_accel_dev *accel_dev);

#ifdef CONFIG_DEBUG_FS
void adf_gen4_init_dev_pm_data(struct adf_accel_dev *accel_dev);
#else
static inline void adf_gen4_init_dev_pm_data(struct adf_accel_dev *accel_dev)
{
}
#endif /* CONFIG_DEBUG_FS */

#endif