/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2021 MediaTek Inc. * Author: Sam Shih <sam.shih@mediatek.com> */ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL … #define CLK_APMIXED_NET2PLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_SGMPLL … #define CLK_APMIXED_WEDMCUPLL … #define CLK_APMIXED_NET1PLL … #define CLK_APMIXED_MPLL … #define CLK_APMIXED_APLL2 … /* TOPCKGEN */ #define CLK_TOP_XTAL … #define CLK_TOP_XTAL_D2 … #define CLK_TOP_RTC_32K … #define CLK_TOP_RTC_32P7K … #define CLK_TOP_MPLL_D2 … #define CLK_TOP_MPLL_D4 … #define CLK_TOP_MPLL_D8 … #define CLK_TOP_MPLL_D8_D2 … #define CLK_TOP_MPLL_D3_D2 … #define CLK_TOP_MMPLL_D2 … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D8 … #define CLK_TOP_MMPLL_D8_D2 … #define CLK_TOP_MMPLL_D3_D8 … #define CLK_TOP_MMPLL_U2PHY … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_NET1PLL_D4 … #define CLK_TOP_NET1PLL_D5 … #define CLK_TOP_NET1PLL_D5_D2 … #define CLK_TOP_NET1PLL_D5_D4 … #define CLK_TOP_NET1PLL_D8_D2 … #define CLK_TOP_NET1PLL_D8_D4 … #define CLK_TOP_NET2PLL_D4 … #define CLK_TOP_NET2PLL_D4_D2 … #define CLK_TOP_NET2PLL_D3_D2 … #define CLK_TOP_WEDMCUPLL_D5_D2 … #define CLK_TOP_NFI1X_SEL … #define CLK_TOP_SPINFI_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_SPIM_MST_SEL … #define CLK_TOP_UART_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_I2C_SEL … #define CLK_TOP_PEXTP_TL_SEL … #define CLK_TOP_EMMC_250M_SEL … #define CLK_TOP_EMMC_416M_SEL … #define CLK_TOP_F_26M_ADC_SEL … #define CLK_TOP_DRAMC_SEL … #define CLK_TOP_DRAMC_MD32_SEL … #define CLK_TOP_SYSAXI_SEL … #define CLK_TOP_SYSAPB_SEL … #define CLK_TOP_ARM_DB_MAIN_SEL … #define CLK_TOP_ARM_DB_JTSEL … #define CLK_TOP_NETSYS_SEL … #define CLK_TOP_NETSYS_500M_SEL … #define CLK_TOP_NETSYS_MCU_SEL … #define CLK_TOP_NETSYS_2X_SEL … #define CLK_TOP_SGM_325M_SEL … #define CLK_TOP_SGM_REG_SEL … #define CLK_TOP_A1SYS_SEL … #define CLK_TOP_CONN_MCUSYS_SEL … #define CLK_TOP_EIP_B_SEL … #define CLK_TOP_PCIE_PHY_SEL … #define CLK_TOP_USB3_PHY_SEL … #define CLK_TOP_F26M_SEL … #define CLK_TOP_AUD_L_SEL … #define CLK_TOP_A_TUNER_SEL … #define CLK_TOP_U2U3_SEL … #define CLK_TOP_U2U3_SYS_SEL … #define CLK_TOP_U2U3_XHCI_SEL … #define CLK_TOP_DA_U2_REFSEL … #define CLK_TOP_DA_U2_CK_1P_SEL … #define CLK_TOP_AP2CNN_HOST_SEL … #define CLK_TOP_JTAG … /* INFRACFG */ #define CLK_INFRA_SYSAXI_D2 … #define CLK_INFRA_UART0_SEL … #define CLK_INFRA_UART1_SEL … #define CLK_INFRA_UART2_SEL … #define CLK_INFRA_SPI0_SEL … #define CLK_INFRA_SPI1_SEL … #define CLK_INFRA_PWM1_SEL … #define CLK_INFRA_PWM2_SEL … #define CLK_INFRA_PWM_BSEL … #define CLK_INFRA_PCIE_SEL … #define CLK_INFRA_GPT_STA … #define CLK_INFRA_PWM_HCK … #define CLK_INFRA_PWM_STA … #define CLK_INFRA_PWM1_CK … #define CLK_INFRA_PWM2_CK … #define CLK_INFRA_CQ_DMA_CK … #define CLK_INFRA_EIP97_CK … #define CLK_INFRA_AUD_BUS_CK … #define CLK_INFRA_AUD_26M_CK … #define CLK_INFRA_AUD_L_CK … #define CLK_INFRA_AUD_AUD_CK … #define CLK_INFRA_AUD_EG2_CK … #define CLK_INFRA_DRAMC_26M_CK … #define CLK_INFRA_DBG_CK … #define CLK_INFRA_AP_DMA_CK … #define CLK_INFRA_SEJ_CK … #define CLK_INFRA_SEJ_13M_CK … #define CLK_INFRA_THERM_CK … #define CLK_INFRA_I2C0_CK … #define CLK_INFRA_UART0_CK … #define CLK_INFRA_UART1_CK … #define CLK_INFRA_UART2_CK … #define CLK_INFRA_NFI1_CK … #define CLK_INFRA_SPINFI1_CK … #define CLK_INFRA_NFI_HCK_CK … #define CLK_INFRA_SPI0_CK … #define CLK_INFRA_SPI1_CK … #define CLK_INFRA_SPI0_HCK_CK … #define CLK_INFRA_SPI1_HCK_CK … #define CLK_INFRA_FRTC_CK … #define CLK_INFRA_MSDC_CK … #define CLK_INFRA_MSDC_HCK_CK … #define CLK_INFRA_MSDC_133M_CK … #define CLK_INFRA_MSDC_66M_CK … #define CLK_INFRA_ADC_26M_CK … #define CLK_INFRA_ADC_FRC_CK … #define CLK_INFRA_FBIST2FPC_CK … #define CLK_INFRA_IUSB_133_CK … #define CLK_INFRA_IUSB_66M_CK … #define CLK_INFRA_IUSB_SYS_CK … #define CLK_INFRA_IUSB_CK … #define CLK_INFRA_IPCIE_CK … #define CLK_INFRA_IPCIE_PIPE_CK … #define CLK_INFRA_IPCIER_CK … #define CLK_INFRA_IPCIEB_CK … #define CLK_INFRA_TRNG_CK … /* SGMIISYS_0 */ #define CLK_SGMII0_TX250M_EN … #define CLK_SGMII0_RX250M_EN … #define CLK_SGMII0_CDR_REF … #define CLK_SGMII0_CDR_FB … /* SGMIISYS_1 */ #define CLK_SGMII1_TX250M_EN … #define CLK_SGMII1_RX250M_EN … #define CLK_SGMII1_CDR_REF … #define CLK_SGMII1_CDR_FB … /* ETHSYS */ #define CLK_ETH_FE_EN … #define CLK_ETH_GP2_EN … #define CLK_ETH_GP1_EN … #define CLK_ETH_WOCPU1_EN … #define CLK_ETH_WOCPU0_EN … #endif /* _DT_BINDINGS_CLK_MT7986_H */
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