/* SPDX-License-Identifier: GPL-2.0 */ /* * Stuff for AMCC S5933 PCI Controller * * Author: Michal Dobes <[email protected]> * * Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver * made by Andrea Cisternino <[email protected]> * and as result of espionage from MITE code made by David A. Schleef. * Thanks to AMCC for their on-line documentation and bus master DMA * example. */ #ifndef _AMCC_S5933_H_ #define _AMCC_S5933_H_ /****************************************************************************/ /* AMCC Operation Register Offsets - PCI */ /****************************************************************************/ #define AMCC_OP_REG_OMB1 … #define AMCC_OP_REG_OMB2 … #define AMCC_OP_REG_OMB3 … #define AMCC_OP_REG_OMB4 … #define AMCC_OP_REG_IMB1 … #define AMCC_OP_REG_IMB2 … #define AMCC_OP_REG_IMB3 … #define AMCC_OP_REG_IMB4 … #define AMCC_OP_REG_FIFO … #define AMCC_OP_REG_MWAR … #define AMCC_OP_REG_MWTC … #define AMCC_OP_REG_MRAR … #define AMCC_OP_REG_MRTC … #define AMCC_OP_REG_MBEF … #define AMCC_OP_REG_INTCSR … #define AMCC_OP_REG_INTCSR_SRC … #define AMCC_OP_REG_INTCSR_FEC … #define AMCC_OP_REG_MCSR … #define AMCC_OP_REG_MCSR_NVDATA … #define AMCC_OP_REG_MCSR_NVCMD … #define AMCC_FIFO_DEPTH_DWORD … #define AMCC_FIFO_DEPTH_BYTES … /****************************************************************************/ /* AMCC - PCI Interrupt Control/Status Register */ /****************************************************************************/ #define INTCSR_OUTBOX_BYTE(x) … #define INTCSR_OUTBOX_SELECT(x) … #define INTCSR_OUTBOX_EMPTY_INT … #define INTCSR_INBOX_BYTE(x) … #define INTCSR_INBOX_SELECT(x) … #define INTCSR_INBOX_FULL_INT … /* read, or write clear inbox full interrupt */ #define INTCSR_INBOX_INTR_STATUS … /* read only, interrupt asserted */ #define INTCSR_INTR_ASSERTED … /****************************************************************************/ /* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */ /****************************************************************************/ #define MCSR_NV_LOAD_LOW_ADDR … #define MCSR_NV_LOAD_HIGH_ADDR … #define MCSR_NV_WRITE … #define MCSR_NV_READ … #define MCSR_NV_MASK … #define MCSR_NV_ENABLE … #define MCSR_NV_BUSY … /****************************************************************************/ /* AMCC Operation Registers Size - PCI */ /****************************************************************************/ #define AMCC_OP_REG_SIZE … /****************************************************************************/ /* AMCC Operation Register Offsets - Add-on */ /****************************************************************************/ #define AMCC_OP_REG_AIMB1 … #define AMCC_OP_REG_AIMB2 … #define AMCC_OP_REG_AIMB3 … #define AMCC_OP_REG_AIMB4 … #define AMCC_OP_REG_AOMB1 … #define AMCC_OP_REG_AOMB2 … #define AMCC_OP_REG_AOMB3 … #define AMCC_OP_REG_AOMB4 … #define AMCC_OP_REG_AFIFO … #define AMCC_OP_REG_AMWAR … #define AMCC_OP_REG_APTA … #define AMCC_OP_REG_APTD … #define AMCC_OP_REG_AMRAR … #define AMCC_OP_REG_AMBEF … #define AMCC_OP_REG_AINT … #define AMCC_OP_REG_AGCSTS … #define AMCC_OP_REG_AMWTC … #define AMCC_OP_REG_AMRTC … /****************************************************************************/ /* AMCC - Add-on General Control/Status Register */ /****************************************************************************/ #define AGCSTS_CONTROL_MASK … #define AGCSTS_NV_ACC_MASK … #define AGCSTS_RESET_MASK … #define AGCSTS_NV_DA_MASK … #define AGCSTS_BIST_MASK … #define AGCSTS_STATUS_MASK … #define AGCSTS_TCZERO_MASK … #define AGCSTS_FIFO_ST_MASK … #define AGCSTS_TC_ENABLE … #define AGCSTS_RESET_MBFLAGS … #define AGCSTS_RESET_P2A_FIFO … #define AGCSTS_RESET_A2P_FIFO … #define AGCSTS_RESET_FIFOS … #define AGCSTS_A2P_TCOUNT … #define AGCSTS_P2A_TCOUNT … #define AGCSTS_FS_P2A_EMPTY … #define AGCSTS_FS_P2A_HALF … #define AGCSTS_FS_P2A_FULL … #define AGCSTS_FS_A2P_EMPTY … #define AGCSTS_FS_A2P_HALF … #define AGCSTS_FS_A2P_FULL … /****************************************************************************/ /* AMCC - Add-on Interrupt Control/Status Register */ /****************************************************************************/ #define AINT_INT_MASK … #define AINT_SEL_MASK … #define AINT_IS_ENSEL_MASK … #define AINT_INT_ASSERTED … #define AINT_BM_ERROR … #define AINT_BIST_INT … #define AINT_RT_COMPLETE … #define AINT_WT_COMPLETE … #define AINT_OUT_MB_INT … #define AINT_IN_MB_INT … #define AINT_READ_COMPL … #define AINT_WRITE_COMPL … #define AINT_OMB_ENABLE … #define AINT_OMB_SELECT … #define AINT_OMB_BYTE … #define AINT_IMB_ENABLE … #define AINT_IMB_SELECT … #define AINT_IMB_BYTE … /* these are bits from various different registers, needs cleanup XXX */ /* Enable Bus Mastering */ #define EN_A2P_TRANSFERS … /* FIFO Flag Reset */ #define RESET_A2P_FLAGS … /* FIFO Relative Priority */ #define A2P_HI_PRIORITY … /* Identify Interrupt Sources */ #define ANY_S593X_INT … #define READ_TC_INT … #define WRITE_TC_INT … #define IN_MB_INT … #define MASTER_ABORT_INT … #define TARGET_ABORT_INT … #define BUS_MASTER_INT … #endif
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