/* SPDX-License-Identifier: GPL-2.0+ */ /* * plx9080.h * * Copyright (C) 2002,2003 Frank Mori Hess <[email protected]> * ******************************************************************** * * Copyright (C) 1999 RG Studio s.c. * Written by Krzysztof Halasa <[email protected]> * * Portions (C) SBE Inc., used by permission. */ #ifndef __COMEDI_PLX9080_H #define __COMEDI_PLX9080_H #include <linux/compiler.h> #include <linux/types.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/io.h> /** * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080 * @pci_start_addr: PCI Bus address for transfer (DMAPADR). * @local_start_addr: Local Bus address for transfer (DMALADR). * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ). * @next: Address of next descriptor + flags (DMADPR). * * Describes the format of a scatter-gather DMA descriptor for the PLX * PCI 9080. All members are raw, little-endian register values that * will be transferred by the DMA engine from local or PCI memory into * corresponding registers for the DMA channel. * * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0 * of @next contain flags describing the address space of the next * descriptor (local or PCI), an "end of chain" marker, an "interrupt on * terminal count" bit, and a data transfer direction. */ struct plx_dma_desc { … }; /* * Register Offsets and Bit Definitions */ /* Local Address Space 0 Range Register */ #define PLX_REG_LAS0RR … /* Local Address Space 1 Range Register */ #define PLX_REG_LAS1RR … #define PLX_LASRR_IO … #define PLX_LASRR_MLOC_ANY32 … #define PLX_LASRR_MLOC_LT1MB … #define PLX_LASRR_MLOC_ANY64 … #define PLX_LASRR_MLOC_MASK … #define PLX_LASRR_PREFETCH … /* bits that specify range for memory space decode bits */ #define PLX_LASRR_MEM_MASK … /* bits that specify range for i/o space decode bits */ #define PLX_LASRR_IO_MASK … /* Local Address Space 0 Local Base Address (Remap) Register */ #define PLX_REG_LAS0BA … /* Local Address Space 1 Local Base Address (Remap) Register */ #define PLX_REG_LAS1BA … #define PLX_LASBA_EN … /* bits that specify local base address for memory space */ #define PLX_LASBA_MEM_MASK … /* bits that specify local base address for i/o space */ #define PLX_LASBA_IO_MASK … /* Mode/Arbitration Register */ #define PLX_REG_MARBR … /* DMA Arbitration Register (alias of MARBR). */ #define PLX_REG_DMAARB … /* Local Bus Latency Timer */ #define PLX_MARBR_LT(x) … #define PLX_MARBR_LT_MASK … #define PLX_MARBR_TO_LT(r) … /* Local Bus Pause Timer */ #define PLX_MARBR_PT(x) … #define PLX_MARBR_PT_MASK … #define PLX_MARBR_TO_PT(r) … /* Local Bus Latency Timer Enable */ #define PLX_MARBR_LTEN … /* Local Bus Pause Timer Enable */ #define PLX_MARBR_PTEN … /* Local Bus BREQ Enable */ #define PLX_MARBR_BREQEN … /* DMA Channel Priority */ #define PLX_MARBR_PRIO_ROT … #define PLX_MARBR_PRIO_DMA0 … #define PLX_MARBR_PRIO_DMA1 … #define PLX_MARBR_PRIO_MASK … /* Local Bus Direct Slave Give Up Bus Mode */ #define PLX_MARBR_DSGUBM … /* Direct Slace LLOCKo# Enable */ #define PLX_MARBR_DSLLOCKOEN … /* PCI Request Mode */ #define PLX_MARBR_PCIREQM … /* PCI Specification v2.1 Mode */ #define PLX_MARBR_PCIV21M … /* PCI Read No Write Mode */ #define PLX_MARBR_PCIRNWM … /* PCI Read with Write Flush Mode */ #define PLX_MARBR_PCIRWFM … /* Gate Local Bus Latency Timer with BREQ */ #define PLX_MARBR_GLTBREQ … /* PCI Read No Flush Mode */ #define PLX_MARBR_PCIRNFM … /* * Make reads from PCI Configuration register 0 return Subsystem ID and * Subsystem Vendor ID instead of Device ID and Vendor ID */ #define PLX_MARBR_SUBSYSIDS … /* Big/Little Endian Descriptor Register */ #define PLX_REG_BIGEND … /* Configuration Register Big Endian Mode */ #define PLX_BIGEND_CONFIG … /* Direct Master Big Endian Mode */ #define PLX_BIGEND_DM … /* Direct Slave Address Space 0 Big Endian Mode */ #define PLX_BIGEND_DSAS0 … /* Direct Slave Expansion ROM Big Endian Mode */ #define PLX_BIGEND_EROM … /* Big Endian Byte Lane Mode - use most significant byte lanes */ #define PLX_BIGEND_BEBLM … /* Direct Slave Address Space 1 Big Endian Mode */ #define PLX_BIGEND_DSAS1 … /* DMA Channel 1 Big Endian Mode */ #define PLX_BIGEND_DMA1 … /* DMA Channel 0 Big Endian Mode */ #define PLX_BIGEND_DMA0 … /* DMA Channel N Big Endian Mode (N <= 1) */ #define PLX_BIGEND_DMA(n) … /* * Note: The Expansion ROM stuff is only relevant to the PC environment. * This expansion ROM code is executed by the host CPU at boot time. * For this reason no bit definitions are provided here. */ /* Expansion ROM Range Register */ #define PLX_REG_EROMRR … /* Expansion ROM Local Base Address (Remap) Register */ #define PLX_REG_EROMBA … /* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */ #define PLX_REG_LBRD0 … /* Local Address Space 1 Bus Region Descriptor Register */ #define PLX_REG_LBRD1 … /* Memory Space Local Bus Width */ #define PLX_LBRD_MSWIDTH_8 … #define PLX_LBRD_MSWIDTH_16 … #define PLX_LBRD_MSWIDTH_32 … #define PLX_LBRD_MSWIDTH_32A … #define PLX_LBRD_MSWIDTH_MASK … /* Memory Space Internal Wait States */ #define PLX_LBRD_MSIWS(x) … #define PLX_LBRD_MSIWS_MASK … #define PLX_LBRD_TO_MSIWS(r) … /* Memory Space Ready Input Enable */ #define PLX_LBRD_MSREADYIEN … /* Memory Space BTERM# Input Enable */ #define PLX_LBRD_MSBTERMIEN … /* Memory Space 0 Prefetch Disable (LBRD0 only) */ #define PLX_LBRD0_MSPREDIS … /* Memory Space 1 Burst Enable (LBRD1 only) */ #define PLX_LBRD1_MSBURSTEN … /* Expansion ROM Space Prefetch Disable (LBRD0 only) */ #define PLX_LBRD0_EROMPREDIS … /* Memory Space 1 Prefetch Disable (LBRD1 only) */ #define PLX_LBRD1_MSPREDIS … /* Read Prefetch Count Enable */ #define PLX_LBRD_RPFCOUNTEN … /* Prefetch Counter */ #define PLX_LBRD_PFCOUNT(x) … #define PLX_LBRD_PFCOUNT_MASK … #define PLX_LBRD_TO_PFCOUNT(r) … /* Expansion ROM Space Local Bus Width (LBRD0 only) */ #define PLX_LBRD0_EROMWIDTH_8 … #define PLX_LBRD0_EROMWIDTH_16 … #define PLX_LBRD0_EROMWIDTH_32 … #define PLX_LBRD0_EROMWIDTH_32A … #define PLX_LBRD0_EROMWIDTH_MASK … /* Expansion ROM Space Internal Wait States (LBRD0 only) */ #define PLX_LBRD0_EROMIWS(x) … #define PLX_LBRD0_EROMIWS_MASK … #define PLX_LBRD0_TO_EROMIWS(r) … /* Expansion ROM Space Ready Input Enable (LBDR0 only) */ #define PLX_LBRD0_EROMREADYIEN … /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */ #define PLX_LBRD0_EROMBTERMIEN … /* Memory Space 0 Burst Enable (LBRD0 only) */ #define PLX_LBRD0_MSBURSTEN … /* Extra Long Load From Serial EEPROM (LBRD0 only) */ #define PLX_LBRD0_EELONGLOAD … /* Expansion ROM Space Burst Enable (LBRD0 only) */ #define PLX_LBRD0_EROMBURSTEN … /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */ #define PLX_LBRD0_DSWMTRDY … /* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */ #define PLX_LBRD0_TRDELAY(x) … #define PLX_LBRD0_TRDELAY_MASK … #define PLX_LBRD0_TO_TRDELAY(r) … /* Local Range Register for Direct Master to PCI */ #define PLX_REG_DMRR … /* Local Bus Base Address Register for Direct Master to PCI Memory */ #define PLX_REG_DMLBAM … /* Local Base Address Register for Direct Master to PCI IO/CFG */ #define PLX_REG_DMLBAI … /* PCI Base Address (Remap) Register for Direct Master to PCI Memory */ #define PLX_REG_DMPBAM … /* Direct Master Memory Access Enable */ #define PLX_DMPBAM_MEMACCEN … /* Direct Master I/O Access Enable */ #define PLX_DMPBAM_IOACCEN … /* LLOCK# Input Enable */ #define PLX_DMPBAM_LLOCKIEN … /* Direct Master Read Prefetch Size Control (bits 12, 3) */ #define PLX_DMPBAM_RPSIZE_CONT … #define PLX_DMPBAM_RPSIZE_4 … #define PLX_DMPBAM_RPSIZE_8 … #define PLX_DMPBAM_RPSIZE_16 … #define PLX_DMPBAM_RPSIZE_MASK … /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */ #define PLX_DMPBAM_RMIRDY … /* Programmable Almost Full Level (bits 10, 8:5) */ #define PLX_DMPBAM_PAFL(x) … #define PLX_DMPBAM_TO_PAFL(v) … #define PLX_DMPBAM_PAFL_MASK … /* Write And Invalidate Mode */ #define PLX_DMPBAM_WIM … /* Direct Master Prefetch Limit */ #define PLX_DBPBAM_PFLIMIT … /* I/O Remap Select */ #define PLX_DMPBAM_IOREMAPSEL … /* Direct Master Write Delay */ #define PLX_DMPBAM_WDELAY_NONE … #define PLX_DMPBAM_WDELAY_4 … #define PLX_DMPBAM_WDELAY_8 … #define PLX_DMPBAM_WDELAY_16 … #define PLX_DMPBAM_WDELAY_MASK … /* Remap of Local-to-PCI Space Into PCI Address Space */ #define PLX_DMPBAM_REMAP_MASK … /* PCI Configuration Address Register for Direct Master to PCI IO/CFG */ #define PLX_REG_DMCFGA … /* Congiguration Type */ #define PLX_DMCFGA_TYPE0 … #define PLX_DMCFGA_TYPE1 … #define PLX_DMCFGA_TYPE_MASK … /* Register Number */ #define PLX_DMCFGA_REGNUM(x) … #define PLX_DMCFGA_REGNUM_MASK … #define PLX_DMCFGA_TO_REGNUM(r) … /* Function Number */ #define PLX_DMCFGA_FUNCNUM(x) … #define PLX_DMCFGA_FUNCNUM_MASK … #define PLX_DMCFGA_TO_FUNCNUM(r) … /* Device Number */ #define PLX_DMCFGA_DEVNUM(x) … #define PLX_DMCFGA_DEVNUM_MASK … #define PLX_DMCFGA_TO_DEVNUM(r) … /* Bus Number */ #define PLX_DMCFGA_BUSNUM(x) … #define PLX_DMCFGA_BUSNUM_MASK … #define PLX_DMCFGA_TO_BUSNUM(r) … /* Configuration Enable */ #define PLX_DMCFGA_CONFIGEN … /* * Mailbox Register N (N <= 7) * * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0 * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always * accessible at alternative offsets if the I2O feature is enabled. */ #define PLX_REG_MBOX(n) … #define PLX_REG_MBOX0 … #define PLX_REG_MBOX1 … #define PLX_REG_MBOX2 … #define PLX_REG_MBOX3 … #define PLX_REG_MBOX4 … #define PLX_REG_MBOX5 … #define PLX_REG_MBOX6 … #define PLX_REG_MBOX7 … /* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */ #define PLX_REG_ALT_MBOX(n) … #define PLX_REG_ALT_MBOX0 … #define PLX_REG_ALT_MBOX1 … /* PCI-to-Local Doorbell Register */ #define PLX_REG_P2LDBELL … /* Local-to-PCI Doorbell Register */ #define PLX_REG_L2PDBELL … /* Interrupt Control/Status Register */ #define PLX_REG_INTCSR … /* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */ #define PLX_INTCSR_LSEABORTEN … /* Enable Local Bus LSERR# when PCI parity error occurs */ #define PLX_INTCSR_LSEPARITYEN … /* Generate PCI Bus SERR# when set to 1 */ #define PLX_INTCSR_GENSERR … /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */ #define PLX_INTCSR_MBIEN … /* PCI Interrupt Enable */ #define PLX_INTCSR_PIEN … /* PCI Doorbell Interrupt Enable */ #define PLX_INTCSR_PDBIEN … /* PCI Abort Interrupt Enable */ #define PLX_INTCSR_PABORTIEN … /* PCI Local Interrupt Enable */ #define PLX_INTCSR_PLIEN … /* Retry Abort Enable (for diagnostic purposes only) */ #define PLX_INTCSR_RAEN … /* PCI Doorbell Interrupt Active (read-only) */ #define PLX_INTCSR_PDBIA … /* PCI Abort Interrupt Active (read-only) */ #define PLX_INTCSR_PABORTIA … /* Local Interrupt (LINTi#) Active (read-only) */ #define PLX_INTCSR_PLIA … /* Local Interrupt Output (LINTo#) Enable */ #define PLX_INTCSR_LIOEN … /* Local Doorbell Interrupt Enable */ #define PLX_INTCSR_LDBIEN … /* DMA Channel 0 Interrupt Enable */ #define PLX_INTCSR_DMA0IEN … /* DMA Channel 1 Interrupt Enable */ #define PLX_INTCSR_DMA1IEN … /* DMA Channel N Interrupt Enable (N <= 1) */ #define PLX_INTCSR_DMAIEN(n) … /* Local Doorbell Interrupt Active (read-only) */ #define PLX_INTCSR_LDBIA … /* DMA Channel 0 Interrupt Active (read-only) */ #define PLX_INTCSR_DMA0IA … /* DMA Channel 1 Interrupt Active (read-only) */ #define PLX_INTCSR_DMA1IA … /* DMA Channel N Interrupt Active (N <= 1) (read-only) */ #define PLX_INTCSR_DMAIA(n) … /* BIST Interrupt Active (read-only) */ #define PLX_INTCSR_BISTIA … /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */ #define PLX_INTCSR_ABNOTDM … /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */ #define PLX_INTCSR_ABNOTDMA0 … /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */ #define PLX_INTCSR_ABNOTDMA1 … /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */ #define PLX_INTCSR_ABNOTDMA(n) … /* Target Abort Not Generated After 256 Master Retries (read-only) */ #define PLX_INTCSR_ABNOTRETRY … /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */ #define PLX_INTCSR_MB0IA … /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */ #define PLX_INTCSR_MB1IA … /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */ #define PLX_INTCSR_MB2IA … /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */ #define PLX_INTCSR_MB3IA … /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */ #define PLX_INTCSR_MBIA(n) … /* * Serial EEPROM Control, PCI Command Codes, User I/O Control, * Init Control Register */ #define PLX_REG_CNTRL … /* PCI Read Command Code For DMA */ #define PLX_CNTRL_CCRDMA(x) … #define PLX_CNTRL_CCRDMA_MASK … #define PLX_CNTRL_TO_CCRDMA(r) … #define PLX_CNTRL_CCRDMA_NORMAL … /* PCI Write Command Code For DMA 0 */ #define PLX_CNTRL_CCWDMA(x) … #define PLX_CNTRL_CCWDMA_MASK … #define PLX_CNTRL_TO_CCWDMA(r) … #define PLX_CNTRL_CCWDMA_NORMAL … /* PCI Memory Read Command Code For Direct Master */ #define PLX_CNTRL_CCRDM(x) … #define PLX_CNTRL_CCRDM_MASK … #define PLX_CNTRL_TO_CCRDM(r) … #define PLX_CNTRL_CCRDM_NORMAL … /* PCI Memory Write Command Code For Direct Master */ #define PLX_CNTRL_CCWDM(x) … #define PLX_CNTRL_CCWDM_MASK … #define PLX_CNTRL_TO_CCWDM(r) … #define PLX_CNTRL_CCWDM_NORMAL … /* General Purpose Output (USERO) */ #define PLX_CNTRL_USERO … /* General Purpose Input (USERI) (read-only) */ #define PLX_CNTRL_USERI … /* Serial EEPROM Clock Output (EESK) */ #define PLX_CNTRL_EESK … /* Serial EEPROM Chip Select Output (EECS) */ #define PLX_CNTRL_EECS … /* Serial EEPROM Data Write Bit (EEDI (sic)) */ #define PLX_CNTRL_EEWB … /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */ #define PLX_CNTRL_EERB … /* Serial EEPROM Present (read-only) */ #define PLX_CNTRL_EEPRESENT … /* Reload Configuration Registers from EEPROM */ #define PLX_CNTRL_EERELOAD … /* PCI Adapter Software Reset (asserts LRESETo#) */ #define PLX_CNTRL_RESET … /* Local Init Status (read-only) */ #define PLX_CNTRL_INITDONE … /* * Combined command code stuff for convenience. */ #define PLX_CNTRL_CC_MASK … #define PLX_CNTRL_CC_NORMAL … /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */ #define PLX_REG_PCIHIDR … /* Hard-coded ID for PLX PCI 9080 */ #define PLX_PCIHIDR_9080 … /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */ #define PLX_REG_PCIHREV … /* DMA Channel N Mode Register (N <= 1) */ #define PLX_REG_DMAMODE(n) … #define PLX_REG_DMAMODE0 … #define PLX_REG_DMAMODE1 … /* Local Bus Width */ #define PLX_DMAMODE_WIDTH_8 … #define PLX_DMAMODE_WIDTH_16 … #define PLX_DMAMODE_WIDTH_32 … #define PLX_DMAMODE_WIDTH_32A … #define PLX_DMAMODE_WIDTH_MASK … /* Internal Wait States */ #define PLX_DMAMODE_IWS(x) … #define PLX_DMAMODE_IWS_MASK … #define PLX_DMAMODE_TO_IWS(r) … /* Ready Input Enable */ #define PLX_DMAMODE_READYIEN … /* BTERM# Input Enable */ #define PLX_DMAMODE_BTERMIEN … /* Local Burst Enable */ #define PLX_DMAMODE_BURSTEN … /* Chaining Enable */ #define PLX_DMAMODE_CHAINEN … /* Done Interrupt Enable */ #define PLX_DMAMODE_DONEIEN … /* Hold Local Address Constant */ #define PLX_DMAMODE_LACONST … /* Demand Mode */ #define PLX_DMAMODE_DEMAND … /* Write And Invalidate Mode */ #define PLX_DMAMODE_WINVALIDATE … /* DMA EOT Enable - enables EOT0# or EOT1# input pin */ #define PLX_DMAMODE_EOTEN … /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */ #define PLX_DMAMODE_STOP … /* DMA Clear Count Mode - count in descriptor cleared on completion */ #define PLX_DMAMODE_CLRCOUNT … /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */ #define PLX_DMAMODE_INTRPCI … /* DMA Channel N PCI Address Register (N <= 1) */ #define PLX_REG_DMAPADR(n) … #define PLX_REG_DMAPADR0 … #define PLX_REG_DMAPADR1 … /* DMA Channel N Local Address Register (N <= 1) */ #define PLX_REG_DMALADR(n) … #define PLX_REG_DMALADR0 … #define PLX_REG_DMALADR1 … /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */ #define PLX_REG_DMASIZ(n) … #define PLX_REG_DMASIZ0 … #define PLX_REG_DMASIZ1 … /* DMA Channel N Descriptor Pointer Register (N <= 1) */ #define PLX_REG_DMADPR(n) … #define PLX_REG_DMADPR0 … #define PLX_REG_DMADPR1 … /* Descriptor Located In PCI Address Space (not local address space) */ #define PLX_DMADPR_DESCPCI … /* End Of Chain */ #define PLX_DMADPR_CHAINEND … /* Interrupt After Terminal Count */ #define PLX_DMADPR_TCINTR … /* Direction Of Transfer Local Bus To PCI (not PCI to local) */ #define PLX_DMADPR_XFERL2P … /* Next Descriptor Address Bits 31:4 (16 byte boundary) */ #define PLX_DMADPR_NEXT_MASK … /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */ #define PLX_REG_DMACSR(n) … #define PLX_REG_DMACSR0 … #define PLX_REG_DMACSR1 … /* Channel Enable */ #define PLX_DMACSR_ENABLE … /* Channel Start - write 1 to start transfer (write-only) */ #define PLX_DMACSR_START … /* Channel Abort - write 1 to abort transfer (write-only) */ #define PLX_DMACSR_ABORT … /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */ #define PLX_DMACSR_CLEARINTR … /* Channel Done - transfer complete/inactive (read-only) */ #define PLX_DMACSR_DONE … /* DMA Threshold Register */ #define PLX_REG_DMATHR … /* * DMA Threshold constraints: * (C0PLAF + 1) + (C0PLAE + 1) <= 32 * (C0LPAF + 1) + (C0LPAE + 1) <= 32 * (C1PLAF + 1) + (C1PLAE + 1) <= 16 * (C1LPAF + 1) + (C1LPAE + 1) <= 16 */ /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C0PLAF(x) … #define PLX_DMATHR_C0PLAF_MASK … #define PLX_DMATHR_TO_C0PLAF(r) … /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C0LPAE(x) … #define PLX_DMATHR_C0LPAE_MASK … #define PLX_DMATHR_TO_C0LPAE(r) … /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C0LPAF(x) … #define PLX_DMATHR_C0LPAF_MASK … #define PLX_DMATHR_TO_C0LPAF(r) … /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C0PLAE(x) … #define PLX_DMATHR_C0PLAE_MASK … #define PLX_DMATHR_TO_C0PLAE(r) … /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C1PLAF(x) … #define PLX_DMATHR_C1PLAF_MASK … #define PLX_DMATHR_TO_C1PLAF(r) … /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C1LPAE(x) … #define PLX_DMATHR_C1LPAE_MASK … #define PLX_DMATHR_TO_C1LPAE(r) … /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */ #define PLX_DMATHR_C1LPAF(x) … #define PLX_DMATHR_C1LPAF_MASK … #define PLX_DMATHR_TO_C1LPAF(r) … /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */ #define PLX_DMATHR_C1PLAE(x) … #define PLX_DMATHR_C1PLAE_MASK … #define PLX_DMATHR_TO_C1PLAE(r) … /* * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR, * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted. * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and * MBOX1 are accessible via alternative offsets. */ /* Queue Status/Control Register */ #define PLX_REG_QSR … /* Value of QSR after reset - disables I2O feature completely. */ #define PLX_QSR_VALUE_AFTER_RESET … /* * Accesses near the end of memory can cause the PLX chip * to pre-fetch data off of end-of-ram. Limit the size of * memory so host-side accesses cannot occur. */ #define PLX_PREFETCH … /** * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer * @iobase: Remapped base address of configuration registers. * @channel: DMA channel number (0 or 1). * * Aborts the DMA transfer on the channel, which must have been enabled * and started beforehand. * * Return: * %0 on success. * -%ETIMEDOUT if timed out waiting for abort to complete. */ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) { … } #endif /* __COMEDI_PLX9080_H */
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