/* SPDX-License-Identifier: GPL-2.0+ */ /* * comedi/drivers/s626.h * Sensoray s626 Comedi driver, header file * * COMEDI - Linux Control and Measurement Device Interface * Copyright (C) 2000 David A. Schleef <[email protected]> * * Based on Sensoray Model 626 Linux driver Version 0.2 * Copyright (C) 2002-2004 Sensoray Co., Inc. */ #ifndef S626_H_INCLUDED #define S626_H_INCLUDED #define S626_DMABUF_SIZE … #define S626_ADC_CHANNELS … #define S626_DAC_CHANNELS … #define S626_ENCODER_CHANNELS … #define S626_DIO_CHANNELS … #define S626_DIO_BANKS … #define S626_DIO_EXTCHANS … #define S626_NUM_TRIMDACS … /* PCI bus interface types. */ #define S626_INTEL … #define S626_MOTOROLA … #define S626_PLATFORM … #define S626_RANGE_5V … #define S626_RANGE_10V … #define S626_EOPL … #define S626_GSEL_BIPOLAR5V … #define S626_GSEL_BIPOLAR10V … /* Error codes that must be visible to this base class. */ #define S626_ERR_ILLEGAL_PARM … #define S626_ERR_I2C … #define S626_ERR_COUNTERSETUP … #define S626_ERR_DEBI_TIMEOUT … /* * Organization (physical order) and size (in DWORDs) of logical DMA buffers * contained by ANA_DMABUF. */ #define S626_ADC_DMABUF_DWORDS … #define S626_DAC_WDMABUF_DWORDS … /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ /* Address offsets, in DWORDS, from base of DMA buffer. */ #define S626_DAC_WDMABUF_OS … /* Interrupt enable bit in ISR and IER. */ #define S626_IRQ_GPIO3 … #define S626_IRQ_RPS1 … #define S626_ISR_AFOU … /* Audio fifo under/overflow detected. */ #define S626_IRQ_COINT1A … #define S626_IRQ_COINT1B … #define S626_IRQ_COINT2A … #define S626_IRQ_COINT2B … #define S626_IRQ_COINT3A … #define S626_IRQ_COINT3B … /* RPS command codes. */ #define S626_RPS_CLRSIGNAL … #define S626_RPS_SETSIGNAL … #define S626_RPS_NOP … #define S626_RPS_PAUSE … #define S626_RPS_UPLOAD … #define S626_RPS_JUMP … #define S626_RPS_LDREG … #define S626_RPS_STREG … #define S626_RPS_STOP … #define S626_RPS_IRQ … #define S626_RPS_LOGICAL_OR … #define S626_RPS_INVERT … #define S626_RPS_DEBI … #define S626_RPS_SIG0 … #define S626_RPS_SIG1 … #define S626_RPS_SIG2 … #define S626_RPS_GPIO2 … #define S626_RPS_GPIO3 … #define S626_RPS_SIGADC … #define S626_RPS_SIGDAC … /* RPS clock parameters. */ #define S626_RPSCLK_SCALAR … #define S626_RPSCLK_PER_US … /* * Number of RPS clocks in one * microsecond. */ /* Event counter source addresses. */ #define S626_SBA_RPS_A0 … /* GPIO constants. */ #define S626_GPIO_BASE … #define S626_GPIO1_LO … #define S626_GPIO1_HI … /* Primary Status Register (PSR) constants. */ #define S626_PSR_DEBI_E … #define S626_PSR_DEBI_S … #define S626_PSR_A2_IN … #define S626_PSR_AFOU … #define S626_PSR_GPIO2 … #define S626_PSR_EC0S … /* Secondary Status Register (SSR) constants. */ #define S626_SSR_AF2_OUT … /* Master Control Register 1 (MC1) constants. */ #define S626_MC1_SOFT_RESET … #define S626_MC1_SHUTDOWN … #define S626_MC1_ERPS1 … #define S626_MC1_ERPS0 … #define S626_MC1_DEBI … #define S626_MC1_AUDIO … #define S626_MC1_I2C … #define S626_MC1_A2OUT … #define S626_MC1_A2IN … #define S626_MC1_A1IN … /* Master Control Register 2 (MC2) constants. */ #define S626_MC2_UPLD_DEBI … #define S626_MC2_UPLD_IIC … #define S626_MC2_RPSSIG2 … #define S626_MC2_RPSSIG1 … #define S626_MC2_RPSSIG0 … #define S626_MC2_ADC_RPS … #define S626_MC2_DAC_RPS … /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ #define S626_P_PCI_BT_A … #define S626_P_DEBICFG … #define S626_P_DEBICMD … #define S626_P_DEBIPAGE … #define S626_P_DEBIAD … #define S626_P_I2CCTRL … #define S626_P_I2CSTAT … #define S626_P_BASEA2_IN … #define S626_P_PROTA2_IN … #define S626_P_PAGEA2_IN … #define S626_P_BASEA2_OUT … #define S626_P_PROTA2_OUT … #define S626_P_PAGEA2_OUT … #define S626_P_RPSPAGE0 … #define S626_P_RPSPAGE1 … #define S626_P_RPS0_TOUT … #define S626_P_RPS1_TOUT … #define S626_P_IER … #define S626_P_GPIO … #define S626_P_EC1SSR … #define S626_P_ECT1R … #define S626_P_ACON1 … #define S626_P_ACON2 … #define S626_P_MC1 … #define S626_P_MC2 … #define S626_P_RPSADDR0 … #define S626_P_RPSADDR1 … #define S626_P_ISR … #define S626_P_PSR … #define S626_P_SSR … #define S626_P_EC1R … #define S626_P_ADP4 … #define S626_P_FB_BUFFER1 … #define S626_P_FB_BUFFER2 … #define S626_P_TSL1 … #define S626_P_TSL2 … /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ /* Analog I/O registers: */ #define S626_LP_DACPOL … #define S626_LP_GSEL … #define S626_LP_ISEL … /* Digital I/O registers */ #define S626_LP_RDDIN(x) … #define S626_LP_WRINTSEL(x) … #define S626_LP_WREDGSEL(x) … #define S626_LP_WRCAPSEL(x) … #define S626_LP_RDCAPFLG(x) … #define S626_LP_WRDOUT(x) … #define S626_LP_RDINTSEL(x) … #define S626_LP_RDEDGSEL(x) … #define S626_LP_RDCAPSEL(x) … /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */ #define S626_LP_CRA(x) … #define S626_LP_CRB(x) … /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */ #define S626_LP_CNTR(x) … /* Miscellaneous Registers (read/write): */ #define S626_LP_MISC1 … #define S626_LP_WRMISC2 … #define S626_LP_RDMISC2 … /* Bit masks for MISC1 register that are the same for reads and writes. */ #define S626_MISC1_WENABLE … #define S626_MISC1_WDISABLE … #define S626_MISC1_EDCAP … #define S626_MISC1_NOEDCAP … /* Bit masks for MISC1 register reads. */ #define S626_RDMISC1_WDTIMEOUT … /* Bit masks for MISC2 register writes. */ #define S626_WRMISC2_WDCLEAR … #define S626_WRMISC2_CHARGE_ENABLE … /* Bit masks for MISC2 register that are the same for reads and writes. */ #define S626_MISC2_BATT_ENABLE … #define S626_MISC2_WDENABLE … #define S626_MISC2_WDPERIOD_MASK … /* Bit masks for ACON1 register. */ #define S626_A2_RUN … #define S626_A1_RUN … #define S626_A1_SWAP … #define S626_A2_SWAP … #define S626_WS_MODES … #if (S626_PLATFORM == S626_INTEL) /* * Base ACON1 config: always run * A1 based on TSL1. */ #define S626_ACON1_BASE … #elif S626_PLATFORM == S626_MOTOROLA #define S626_ACON1_BASE … #endif #define S626_ACON1_ADCSTART … #define S626_ACON1_DACSTART … /* Start transmit to DAC: run A2 based on TSL2. */ #define S626_ACON1_DACSTOP … /* Bit masks for ACON2 register. */ #define S626_A1_CLKSRC_BCLK1 … #define S626_A2_CLKSRC_X1 … #define S626_A2_CLKSRC_X2 … #define S626_A2_CLKSRC_X4 … #define S626_INVERT_BCLK2 … #define S626_BCLK2_OE … #define S626_ACON2_XORMASK … #define S626_ACON2_INIT … /* Bit masks for timeslot records. */ #define S626_WS1 … #define S626_WS2 … #define S626_WS3 … #define S626_WS4 … #define S626_RSD1 … #define S626_SDW_A1 … #define S626_SIB_A1 … #define S626_SF_A1 … /* Select parallel-to-serial converter's data source: */ #define S626_XFIFO_0 … #define S626_XFIFO_1 … #define S626_XFIFO_2 … #define S626_XFIFO_3 … #define S626_XFB0 … #define S626_XFB1 … #define S626_XFB2 … #define S626_XFB3 … #define S626_SIB_A2 … #define S626_SF_A2 … #define S626_LF_A2 … #define S626_XSD2 … #define S626_RSD3 … #define S626_RSD2 … #define S626_LOW_A2 … #define S626_EOS … /* I2C configuration constants. */ #define S626_I2C_CLKSEL … #define S626_I2C_BITRATE … #define S626_I2C_WRTIME … /* I2C manifest constants. */ /* Max retries to wait for EEPROM write. */ #define S626_I2C_RETRIES … #define S626_I2C_ERR … #define S626_I2C_BUSY … #define S626_I2C_ABORT … #define S626_I2C_ATTRSTART … #define S626_I2C_ATTRCONT … #define S626_I2C_ATTRSTOP … #define S626_I2C_ATTRNOP … /* Code macros used for constructing I2C command bytes. */ #define S626_I2C_B2(ATTR, VAL) … #define S626_I2C_B1(ATTR, VAL) … #define S626_I2C_B0(ATTR, VAL) … /* DEBI command constants. */ #define S626_DEBI_CMD_SIZE16 … #define S626_DEBI_CMD_READ … #define S626_DEBI_CMD_WRITE … /* Read immediate 2 bytes. */ #define S626_DEBI_CMD_RDWORD … /* Write immediate 2 bytes. */ #define S626_DEBI_CMD_WRWORD … /* DEBI configuration constants. */ #define S626_DEBI_CFG_XIRQ_EN … #define S626_DEBI_CFG_XRESUME … /* * Transfer when XIRQ * deasserted. */ #define S626_DEBI_CFG_TOQ … #define S626_DEBI_CFG_FAST … /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ #define S626_DEBI_CFG_TOUT_BIT … /* 2-bit field that specifies Endian byte lane steering: */ #define S626_DEBI_CFG_SWAP_NONE … #define S626_DEBI_CFG_SWAP_2 … #define S626_DEBI_CFG_SWAP_4 … #define S626_DEBI_CFG_SLAVE16 … #define S626_DEBI_CFG_INC … #define S626_DEBI_CFG_INTEL … #define S626_DEBI_CFG_TIMEROFF … #if S626_PLATFORM == S626_INTEL #define S626_DEBI_TOUT … /* Intel byte lane steering (pass through all byte lanes). */ #define S626_DEBI_SWAP … #elif S626_PLATFORM == S626_MOTOROLA #define S626_DEBI_TOUT … /* Motorola byte lane steering. */ #define S626_DEBI_SWAP … #endif /* DEBI page table constants. */ #define S626_DEBI_PAGE_DISABLE … /* ******* EXTRA FROM OTHER SENSORAY * .h ******* */ /* LoadSrc values: */ #define S626_LOADSRC_INDX … #define S626_LOADSRC_OVER … #define S626_LOADSRCB_OVERA … #define S626_LOADSRC_NONE … /* IntSrc values: */ #define S626_INTSRC_NONE … #define S626_INTSRC_OVER … #define S626_INTSRC_INDX … #define S626_INTSRC_BOTH … /* LatchSrc values: */ #define S626_LATCHSRC_AB_READ … #define S626_LATCHSRC_A_INDXA … #define S626_LATCHSRC_B_INDXB … #define S626_LATCHSRC_B_OVERA … /* IndxSrc values: */ #define S626_INDXSRC_ENCODER … #define S626_INDXSRC_DIGIN … #define S626_INDXSRC_SOFT … #define S626_INDXSRC_DISABLED … /* IndxPol values: */ #define S626_INDXPOL_POS … #define S626_INDXPOL_NEG … /* Logical encoder mode values: */ #define S626_ENCMODE_COUNTER … #define S626_ENCMODE_TIMER … #define S626_ENCMODE_EXTENDER … /* Physical CntSrc values (for Counter A source and Counter B source): */ #define S626_CNTSRC_ENCODER … #define S626_CNTSRC_DIGIN … #define S626_CNTSRC_SYSCLK … #define S626_CNTSRC_SYSCLK_DOWN … /* ClkPol values: */ #define S626_CLKPOL_POS … #define S626_CLKPOL_NEG … #define S626_CNTDIR_UP … #define S626_CNTDIR_DOWN … /* ClkEnab values: */ #define S626_CLKENAB_ALWAYS … #define S626_CLKENAB_INDEX … /* ClkMult values: */ #define S626_CLKMULT_4X … #define S626_CLKMULT_2X … #define S626_CLKMULT_1X … #define S626_CLKMULT_SPECIAL … /* Sanity-check limits for parameters. */ #define S626_NUM_COUNTERS … #define S626_NUM_INTSOURCES … #define S626_NUM_LATCHSOURCES … #define S626_NUM_CLKMULTS … #define S626_NUM_CLKSOURCES … #define S626_NUM_CLKPOLS … #define S626_NUM_INDEXPOLS … #define S626_NUM_INDEXSOURCES … #define S626_NUM_LOADTRIGS … /* General macros for manipulating bitfields: */ #define S626_MAKE(x, w, p) … #define S626_UNMAKE(v, w, p) … /* Bit field positions in CRA: */ #define S626_CRABIT_INDXSRC_B … #define S626_CRABIT_CNTSRC_B … #define S626_CRABIT_INDXPOL_A … #define S626_CRABIT_LOADSRC_A … #define S626_CRABIT_CLKMULT_A … #define S626_CRABIT_INTSRC_A … #define S626_CRABIT_CLKPOL_A … #define S626_CRABIT_INDXSRC_A … #define S626_CRABIT_CNTSRC_A … /* Bit field widths in CRA: */ #define S626_CRAWID_INDXSRC_B … #define S626_CRAWID_CNTSRC_B … #define S626_CRAWID_INDXPOL_A … #define S626_CRAWID_LOADSRC_A … #define S626_CRAWID_CLKMULT_A … #define S626_CRAWID_INTSRC_A … #define S626_CRAWID_CLKPOL_A … #define S626_CRAWID_INDXSRC_A … #define S626_CRAWID_CNTSRC_A … /* Bit field masks for CRA: */ #define S626_CRAMSK_INDXSRC_B … #define S626_CRAMSK_CNTSRC_B … #define S626_CRAMSK_INDXPOL_A … #define S626_CRAMSK_LOADSRC_A … #define S626_CRAMSK_CLKMULT_A … #define S626_CRAMSK_INTSRC_A … #define S626_CRAMSK_CLKPOL_A … #define S626_CRAMSK_INDXSRC_A … #define S626_CRAMSK_CNTSRC_A … /* Construct parts of the CRA value: */ #define S626_SET_CRA_INDXSRC_B(x) … #define S626_SET_CRA_CNTSRC_B(x) … #define S626_SET_CRA_INDXPOL_A(x) … #define S626_SET_CRA_LOADSRC_A(x) … #define S626_SET_CRA_CLKMULT_A(x) … #define S626_SET_CRA_INTSRC_A(x) … #define S626_SET_CRA_CLKPOL_A(x) … #define S626_SET_CRA_INDXSRC_A(x) … #define S626_SET_CRA_CNTSRC_A(x) … /* Extract parts of the CRA value: */ #define S626_GET_CRA_INDXSRC_B(v) … #define S626_GET_CRA_CNTSRC_B(v) … #define S626_GET_CRA_INDXPOL_A(v) … #define S626_GET_CRA_LOADSRC_A(v) … #define S626_GET_CRA_CLKMULT_A(v) … #define S626_GET_CRA_INTSRC_A(v) … #define S626_GET_CRA_CLKPOL_A(v) … #define S626_GET_CRA_INDXSRC_A(v) … #define S626_GET_CRA_CNTSRC_A(v) … /* Bit field positions in CRB: */ #define S626_CRBBIT_INTRESETCMD … #define S626_CRBBIT_CNTDIR_B … #define S626_CRBBIT_INTRESET_B … #define S626_CRBBIT_OVERDO_A … #define S626_CRBBIT_INTRESET_A … #define S626_CRBBIT_OVERDO_B … #define S626_CRBBIT_CLKENAB_A … #define S626_CRBBIT_INTSRC_B … #define S626_CRBBIT_LATCHSRC … #define S626_CRBBIT_LOADSRC_B … #define S626_CRBBIT_CLEAR_B … #define S626_CRBBIT_CLKMULT_B … #define S626_CRBBIT_CLKENAB_B … #define S626_CRBBIT_INDXPOL_B … #define S626_CRBBIT_CLKPOL_B … /* Bit field widths in CRB: */ #define S626_CRBWID_INTRESETCMD … #define S626_CRBWID_CNTDIR_B … #define S626_CRBWID_INTRESET_B … #define S626_CRBWID_OVERDO_A … #define S626_CRBWID_INTRESET_A … #define S626_CRBWID_OVERDO_B … #define S626_CRBWID_CLKENAB_A … #define S626_CRBWID_INTSRC_B … #define S626_CRBWID_LATCHSRC … #define S626_CRBWID_LOADSRC_B … #define S626_CRBWID_CLEAR_B … #define S626_CRBWID_CLKMULT_B … #define S626_CRBWID_CLKENAB_B … #define S626_CRBWID_INDXPOL_B … #define S626_CRBWID_CLKPOL_B … /* Bit field masks for CRB: */ #define S626_CRBMSK_INTRESETCMD … #define S626_CRBMSK_CNTDIR_B … #define S626_CRBMSK_INTRESET_B … #define S626_CRBMSK_OVERDO_A … #define S626_CRBMSK_INTRESET_A … #define S626_CRBMSK_OVERDO_B … #define S626_CRBMSK_CLKENAB_A … #define S626_CRBMSK_INTSRC_B … #define S626_CRBMSK_LATCHSRC … #define S626_CRBMSK_LOADSRC_B … #define S626_CRBMSK_CLEAR_B … #define S626_CRBMSK_CLKMULT_B … #define S626_CRBMSK_CLKENAB_B … #define S626_CRBMSK_INDXPOL_B … #define S626_CRBMSK_CLKPOL_B … /* Interrupt reset control bits. */ #define S626_CRBMSK_INTCTRL … /* Construct parts of the CRB value: */ #define S626_SET_CRB_INTRESETCMD(x) … #define S626_SET_CRB_INTRESET_B(x) … #define S626_SET_CRB_INTRESET_A(x) … #define S626_SET_CRB_CLKENAB_A(x) … #define S626_SET_CRB_INTSRC_B(x) … #define S626_SET_CRB_LATCHSRC(x) … #define S626_SET_CRB_LOADSRC_B(x) … #define S626_SET_CRB_CLEAR_B(x) … #define S626_SET_CRB_CLKMULT_B(x) … #define S626_SET_CRB_CLKENAB_B(x) … #define S626_SET_CRB_INDXPOL_B(x) … #define S626_SET_CRB_CLKPOL_B(x) … /* Extract parts of the CRB value: */ #define S626_GET_CRB_CNTDIR_B(v) … #define S626_GET_CRB_OVERDO_A(v) … #define S626_GET_CRB_OVERDO_B(v) … #define S626_GET_CRB_CLKENAB_A(v) … #define S626_GET_CRB_INTSRC_B(v) … #define S626_GET_CRB_LATCHSRC(v) … #define S626_GET_CRB_LOADSRC_B(v) … #define S626_GET_CRB_CLEAR_B(v) … #define S626_GET_CRB_CLKMULT_B(v) … #define S626_GET_CRB_CLKENAB_B(v) … #define S626_GET_CRB_INDXPOL_B(v) … #define S626_GET_CRB_CLKPOL_B(v) … /* Bit field positions for standardized SETUP structure: */ #define S626_STDBIT_INTSRC … #define S626_STDBIT_LATCHSRC … #define S626_STDBIT_LOADSRC … #define S626_STDBIT_INDXSRC … #define S626_STDBIT_INDXPOL … #define S626_STDBIT_ENCMODE … #define S626_STDBIT_CLKPOL … #define S626_STDBIT_CLKMULT … #define S626_STDBIT_CLKENAB … /* Bit field widths for standardized SETUP structure: */ #define S626_STDWID_INTSRC … #define S626_STDWID_LATCHSRC … #define S626_STDWID_LOADSRC … #define S626_STDWID_INDXSRC … #define S626_STDWID_INDXPOL … #define S626_STDWID_ENCMODE … #define S626_STDWID_CLKPOL … #define S626_STDWID_CLKMULT … #define S626_STDWID_CLKENAB … /* Bit field masks for standardized SETUP structure: */ #define S626_STDMSK_INTSRC … #define S626_STDMSK_LATCHSRC … #define S626_STDMSK_LOADSRC … #define S626_STDMSK_INDXSRC … #define S626_STDMSK_INDXPOL … #define S626_STDMSK_ENCMODE … #define S626_STDMSK_CLKPOL … #define S626_STDMSK_CLKMULT … #define S626_STDMSK_CLKENAB … /* Construct parts of standardized SETUP structure: */ #define S626_SET_STD_INTSRC(x) … #define S626_SET_STD_LATCHSRC(x) … #define S626_SET_STD_LOADSRC(x) … #define S626_SET_STD_INDXSRC(x) … #define S626_SET_STD_INDXPOL(x) … #define S626_SET_STD_ENCMODE(x) … #define S626_SET_STD_CLKPOL(x) … #define S626_SET_STD_CLKMULT(x) … #define S626_SET_STD_CLKENAB(x) … /* Extract parts of standardized SETUP structure: */ #define S626_GET_STD_INTSRC(v) … #define S626_GET_STD_LATCHSRC(v) … #define S626_GET_STD_LOADSRC(v) … #define S626_GET_STD_INDXSRC(v) … #define S626_GET_STD_INDXPOL(v) … #define S626_GET_STD_ENCMODE(v) … #define S626_GET_STD_CLKPOL(v) … #define S626_GET_STD_CLKMULT(v) … #define S626_GET_STD_CLKENAB(v) … #endif
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