// SPDX-License-Identifier: GPL-2.0+ /* * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC. * * Copyright (c) 2012-2017 Mentor Graphics Inc. */ #include <linux/clk.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <media/v4l2-common.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mc.h> #include <media/v4l2-subdev.h> #include "imx-media.h" /* * there must be 5 pads: 1 input pad from sensor, and * the 4 virtual channel output pads */ #define CSI2_SINK_PAD … #define CSI2_NUM_SINK_PADS … #define CSI2_NUM_SRC_PADS … #define CSI2_NUM_PADS … /* * The default maximum bit-rate per lane in Mbps, if the * source subdev does not provide V4L2_CID_LINK_FREQ. */ #define CSI2_DEFAULT_MAX_MBPS … struct csi2_dev { … }; #define DEVICE_NAME … /* Register offsets */ #define CSI2_VERSION … #define CSI2_N_LANES … #define CSI2_PHY_SHUTDOWNZ … #define CSI2_DPHY_RSTZ … #define CSI2_RESETN … #define CSI2_PHY_STATE … #define PHY_STOPSTATEDATA_BIT … #define PHY_STOPSTATEDATA(n) … #define PHY_RXCLKACTIVEHS … #define PHY_RXULPSCLKNOT … #define PHY_STOPSTATECLK … #define CSI2_DATA_IDS_1 … #define CSI2_DATA_IDS_2 … #define CSI2_ERR1 … #define CSI2_ERR2 … #define CSI2_MSK1 … #define CSI2_MSK2 … #define CSI2_PHY_TST_CTRL0 … #define PHY_TESTCLR … #define PHY_TESTCLK … #define CSI2_PHY_TST_CTRL1 … #define PHY_TESTEN … /* * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is * not part of the MIPI CSI-2 core, but its registers fall in the * same register map range. */ #define CSI2IPU_GASKET … #define CSI2IPU_YUV422_YUYV … static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev) { … } static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n) { … } /* * The required sequence of MIPI CSI-2 startup as specified in the i.MX6 * reference manual is as follows: * * 1. Deassert presetn signal (global reset). * It's not clear what this "global reset" signal is (maybe APB * global reset), but in any case this step would be probably * be carried out during driver load in csi2_probe(). * * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state. * This must be carried out by the MIPI sensor's s_power(ON) subdev * op. * * 3. D-PHY initialization. * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ, * deassert PHY_RSTZ, deassert CSI2_RESETN). * 5. Read the PHY status register (PHY_STATE) to confirm that all data and * clock lanes of the D-PHY are in LP-11 state. * 6. Configure the MIPI Camera Sensor to start transmitting a clock on the * D-PHY clock lane. * 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE) * to confirm that the D-PHY is receiving a clock on the D-PHY clock lane. * * All steps 3 through 7 are carried out by csi2_s_stream(ON) here. Step * 6 is accomplished by calling the source subdev's s_stream(ON) between * steps 5 and 7. */ static void csi2_enable(struct csi2_dev *csi2, bool enable) { … } static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes) { … } static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2, u32 test_code, u32 test_data) { … } /* * This table is based on the table documented at * https://community.nxp.com/docs/DOC-94312. It assumes * a 27MHz D-PHY pll reference clock. */ static const struct { … } hsfreq_map[] = …; static int max_mbps_to_hsfreqrange_sel(u32 max_mbps) { … } static int csi2_dphy_init(struct csi2_dev *csi2) { … } /* * Waits for ultra-low-power state on D-PHY clock lane. This is currently * unused and may not be needed at all, but keep around just in case. */ static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2) { … } /* Waits for low-power LP-11 state on data and clock lanes. */ static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes) { … } /* Wait for active clock on the clock lane. */ static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2) { … } /* Setup the i.MX CSI2IPU Gasket */ static void csi2ipu_gasket_init(struct csi2_dev *csi2) { … } static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes) { … } static int csi2_start(struct csi2_dev *csi2) { … } static void csi2_stop(struct csi2_dev *csi2) { … } /* * V4L2 subdev operations. */ static int csi2_s_stream(struct v4l2_subdev *sd, int enable) { … } static int csi2_link_setup(struct media_entity *entity, const struct media_pad *local, const struct media_pad *remote, u32 flags) { … } static struct v4l2_mbus_framefmt * __csi2_get_fmt(struct csi2_dev *csi2, struct v4l2_subdev_state *sd_state, unsigned int pad, enum v4l2_subdev_format_whence which) { … } static int csi2_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *sdformat) { … } static int csi2_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *sdformat) { … } static int csi2_registered(struct v4l2_subdev *sd) { … } /* --------------- CORE OPS --------------- */ static int csi2_log_status(struct v4l2_subdev *sd) { … } static const struct v4l2_subdev_core_ops csi2_core_ops = …; static const struct media_entity_operations csi2_entity_ops = …; static const struct v4l2_subdev_video_ops csi2_video_ops = …; static const struct v4l2_subdev_pad_ops csi2_pad_ops = …; static const struct v4l2_subdev_ops csi2_subdev_ops = …; static const struct v4l2_subdev_internal_ops csi2_internal_ops = …; static int csi2_notify_bound(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, struct v4l2_async_connection *asd) { … } static void csi2_notify_unbind(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, struct v4l2_async_connection *asd) { … } static const struct v4l2_async_notifier_operations csi2_notify_ops = …; static int csi2_async_register(struct csi2_dev *csi2) { … } static int csi2_probe(struct platform_device *pdev) { … } static void csi2_remove(struct platform_device *pdev) { … } static const struct of_device_id csi2_dt_ids[] = …; MODULE_DEVICE_TABLE(of, csi2_dt_ids); static struct platform_driver csi2_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux