/* SPDX-License-Identifier: GPL-2.0+ */ /* * Driver for Realtek PCI-Express card reader * * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. * * Author: * Wei WANG ([email protected]) * Micky Ching ([email protected]) */ #ifndef __REALTEK_RTSX_CHIP_H #define __REALTEK_RTSX_CHIP_H #include "rtsx.h" #define SUPPORT_CPRM #define SUPPORT_OCP #define SUPPORT_SDIO_ASPM #define SUPPORT_MAGIC_GATE #define SUPPORT_MSXC #define SUPPORT_SD_LOCK /* Hardware switch bus_ctl and cd_ctl automatically */ #define HW_AUTO_SWITCH_SD_BUS /* Enable hardware interrupt write clear */ #define HW_INT_WRITE_CLR /* #define LED_AUTO_BLINK */ /* #define DISABLE_CARD_INT */ #ifdef SUPPORT_MAGIC_GATE /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */ #define MG_SET_ICV_SLOW /* HW may miss ERR/CMDNK signal when sampling INT status. */ #define MS_SAMPLE_INT_ERR /* * HW DO NOT support Wait_INT function * during READ_BYTES transfer mode */ #define READ_BYTES_WAIT_INT #endif #ifdef SUPPORT_MSXC #define XC_POWERCLASS #define SUPPORT_PCGL_1P18 #endif #ifndef LED_AUTO_BLINK #define REGULAR_BLINK #endif #define LED_BLINK_SPEED … #define LED_TOGGLE_INTERVAL … #define GPIO_TOGGLE_THRESHOLD … #define LED_GPIO … #define POLLING_INTERVAL … #define TRACE_ITEM_CNT … #ifndef STATUS_SUCCESS #define STATUS_SUCCESS … #endif #ifndef STATUS_FAIL #define STATUS_FAIL … #endif #ifndef STATUS_TIMEDOUT #define STATUS_TIMEDOUT … #endif #ifndef STATUS_NOMEM #define STATUS_NOMEM … #endif #ifndef STATUS_READ_FAIL #define STATUS_READ_FAIL … #endif #ifndef STATUS_WRITE_FAIL #define STATUS_WRITE_FAIL … #endif #ifndef STATUS_ERROR #define STATUS_ERROR … #endif #define PM_S1 … #define PM_S3 … /* * Transport return codes */ #define TRANSPORT_GOOD … #define TRANSPORT_FAILED … #define TRANSPORT_NO_SENSE … #define TRANSPORT_ERROR … /* * Start-Stop-Unit */ #define STOP_MEDIUM … #define MAKE_MEDIUM_READY … #define UNLOAD_MEDIUM … #define LOAD_MEDIUM … /* * STANDARD_INQUIRY */ #define QULIFIRE … #define AENC_FNC … #define TRML_IOP … #define REL_ADR … #define WBUS_32 … #define WBUS_16 … #define SYNC … #define LINKED … #define CMD_QUE … #define SFT_RE … #define VEN_ID_LEN … #define PRDCT_ID_LEN … #define PRDCT_REV_LEN … /* Dynamic flag definitions: used in set_bit() etc. */ /* 0x00040000 transfer is active */ #define RTSX_FLIDX_TRANS_ACTIVE … /* 0x00100000 abort is in progress */ #define RTSX_FLIDX_ABORTING … /* 0x00200000 disconnect in progress */ #define RTSX_FLIDX_DISCONNECTING … #define ABORTING_OR_DISCONNECTING … /* 0x00400000 device reset in progress */ #define RTSX_FLIDX_RESETTING … /* 0x00800000 SCSI midlayer timed out */ #define RTSX_FLIDX_TIMED_OUT … #define DRCT_ACCESS_DEV … #define RMB_DISC … #define ANSI_SCSI2 … #define SCSI … #define WRITE_PROTECTED_MEDIA … /*---- sense key ----*/ #define ILI … #define NO_SENSE … #define RECOVER_ERR … #define NOT_READY … #define MEDIA_ERR … #define HARDWARE_ERR … #define ILGAL_REQ … #define UNIT_ATTENTION … #define DAT_PRTCT … #define BLNC_CHK … /* write to unblank area */ #define CPY_ABRT … #define ABRT_CMD … #define EQUAL … #define VLM_OVRFLW … #define MISCMP … #define READ_ERR … #define WRITE_ERR … #define FIRST_RESET … #define USED_EXIST … /* * SENSE_DATA */ /*---- valid ----*/ #define SENSE_VALID … #define SENSE_INVALID … /*---- error code ----*/ #define CUR_ERR … #define DEF_ERR … /*---- sense key Information ----*/ #define SNSKEYINFO_LEN … #define SKSV … #define CDB_ILLEGAL … #define DAT_ILLEGAL … #define BPV … #define BIT_ILLEGAL0 … #define BIT_ILLEGAL1 … #define BIT_ILLEGAL2 … #define BIT_ILLEGAL3 … #define BIT_ILLEGAL4 … #define BIT_ILLEGAL5 … #define BIT_ILLEGAL6 … #define BIT_ILLEGAL7 … /*---- ASC ----*/ #define ASC_NO_INFO … #define ASC_MISCMP … #define ASC_INVLD_CDB … #define ASC_INVLD_PARA … #define ASC_LU_NOT_READY … #define ASC_WRITE_ERR … #define ASC_READ_ERR … #define ASC_LOAD_EJCT_ERR … #define ASC_MEDIA_NOT_PRESENT … #define ASC_MEDIA_CHANGED … #define ASC_MEDIA_IN_PROCESS … #define ASC_WRITE_PROTECT … #define ASC_LUN_NOT_SUPPORTED … /*---- ASQC ----*/ #define ASCQ_NO_INFO … #define ASCQ_MEDIA_IN_PROCESS … #define ASCQ_MISCMP … #define ASCQ_INVLD_CDB … #define ASCQ_INVLD_PARA … #define ASCQ_LU_NOT_READY … #define ASCQ_WRITE_ERR … #define ASCQ_READ_ERR … #define ASCQ_LOAD_EJCT_ERR … #define ASCQ_WRITE_PROTECT … struct sense_data_t { … }; /* PCI Operation Register Address */ #define RTSX_HCBAR … #define RTSX_HCBCTLR … #define RTSX_HDBAR … #define RTSX_HDBCTLR … #define RTSX_HAIMR … #define RTSX_BIPR … #define RTSX_BIER … /* Host command buffer control register */ #define STOP_CMD … /* Host data buffer control register */ #define SDMA_MODE … #define ADMA_MODE … #define STOP_DMA … #define TRIG_DMA … /* Bus interrupt pending register */ #define CMD_DONE_INT … #define DATA_DONE_INT … #define TRANS_OK_INT … #define TRANS_FAIL_INT … #define XD_INT … #define MS_INT … #define SD_INT … #define GPIO0_INT … #define OC_INT … #define SD_WRITE_PROTECT … #define XD_EXIST … #define MS_EXIST … #define SD_EXIST … #define DELINK_INT … #define MS_OC_INT … #define SD_OC_INT … #define CARD_INT … #define NEED_COMPLETE_INT … #define RTSX_INT … #define CARD_EXIST … /* Bus interrupt enable register */ #define CMD_DONE_INT_EN … #define DATA_DONE_INT_EN … #define TRANS_OK_INT_EN … #define TRANS_FAIL_INT_EN … #define XD_INT_EN … #define MS_INT_EN … #define SD_INT_EN … #define GPIO0_INT_EN … #define OC_INT_EN … #define DELINK_INT_EN … #define MS_OC_INT_EN … #define SD_OC_INT_EN … #define READ_REG_CMD … #define WRITE_REG_CMD … #define CHECK_REG_CMD … #define HOST_TO_DEVICE … #define DEVICE_TO_HOST … #define RTSX_RESV_BUF_LEN … #define HOST_CMDS_BUF_LEN … #define HOST_SG_TBL_BUF_LEN … #define SD_NR … #define MS_NR … #define XD_NR … #define SPI_NR … #define SD_CARD … #define MS_CARD … #define XD_CARD … #define SPI_CARD … #define MAX_ALLOWED_LUN_CNT … #define XD_FREE_TABLE_CNT … #define MS_FREE_TABLE_CNT … /* Bit Operation */ #define SET_BIT(data, idx) … #define CLR_BIT(data, idx) … #define CHK_BIT(data, idx) … /* SG descriptor */ #define RTSX_SG_INT … #define RTSX_SG_END … #define RTSX_SG_VALID … #define RTSX_SG_NO_OP … #define RTSX_SG_TRANS_DATA … #define RTSX_SG_LINK_DESC … struct rtsx_chip; card_rw_func; /* Supported Clock */ enum card_clock { … }; enum RTSX_STAT { … }; enum IC_VER { … }; #define MAX_RESET_CNT … /* For MS Card */ #define MAX_DEFECTIVE_BLOCK … struct zone_entry { … }; #define TYPE_SD … #define TYPE_MMC … /* TYPE_SD */ #define SD_HS … #define SD_SDR50 … #define SD_DDR50 … #define SD_SDR104 … #define SD_HCXC … /* TYPE_MMC */ #define MMC_26M … #define MMC_52M … #define MMC_4BIT … #define MMC_8BIT … #define MMC_SECTOR_MODE … #define MMC_DDR52 … /* SD card */ #define CHK_SD(sd_card) … #define CHK_SD_HS(sd_card) … #define CHK_SD_SDR50(sd_card) … #define CHK_SD_DDR50(sd_card) … #define CHK_SD_SDR104(sd_card) … #define CHK_SD_HCXC(sd_card) … #define CHK_SD_HC(sd_card) … #define CHK_SD_XC(sd_card) … #define CHK_SD30_SPEED(sd_card) … #define SET_SD(sd_card) … #define SET_SD_HS(sd_card) … #define SET_SD_SDR50(sd_card) … #define SET_SD_DDR50(sd_card) … #define SET_SD_SDR104(sd_card) … #define SET_SD_HCXC(sd_card) … #define CLR_SD_HS(sd_card) … #define CLR_SD_SDR50(sd_card) … #define CLR_SD_DDR50(sd_card) … #define CLR_SD_SDR104(sd_card) … #define CLR_SD_HCXC(sd_card) … /* MMC card */ #define CHK_MMC(sd_card) … #define CHK_MMC_26M(sd_card) … #define CHK_MMC_52M(sd_card) … #define CHK_MMC_4BIT(sd_card) … #define CHK_MMC_8BIT(sd_card) … #define CHK_MMC_SECTOR_MODE(sd_card) … #define CHK_MMC_DDR52(sd_card) … #define SET_MMC(sd_card) … #define SET_MMC_26M(sd_card) … #define SET_MMC_52M(sd_card) … #define SET_MMC_4BIT(sd_card) … #define SET_MMC_8BIT(sd_card) … #define SET_MMC_SECTOR_MODE(sd_card) … #define SET_MMC_DDR52(sd_card) … #define CLR_MMC_26M(sd_card) … #define CLR_MMC_52M(sd_card) … #define CLR_MMC_4BIT(sd_card) … #define CLR_MMC_8BIT(sd_card) … #define CLR_MMC_SECTOR_MODE(sd_card) … #define CLR_MMC_DDR52(sd_card) … #define CHK_MMC_HS(sd_card) … #define CLR_MMC_HS(sd_card) … #define SD_SUPPORT_CLASS_TEN … #define SD_SUPPORT_1V8 … #define SD_SET_CLASS_TEN(sd_card) … #define SD_CHK_CLASS_TEN(sd_card) … #define SD_CLR_CLASS_TEN(sd_card) … #define SD_SET_1V8(sd_card) … #define SD_CHK_1V8(sd_card) … #define SD_CLR_1V8(sd_card) … struct sd_info { … }; struct xd_delay_write_tag { … }; struct xd_info { … }; #define MODE_512_SEQ … #define MODE_2K_SEQ … #define TYPE_MS … #define TYPE_MSPRO … #define MS_4BIT … #define MS_8BIT … #define MS_HG … #define MS_XC … #define HG8BIT … #define CHK_MSPRO(ms_card) … #define CHK_HG8BIT(ms_card) … #define CHK_MSXC(ms_card) … #define CHK_MSHG(ms_card) … #define CHK_MS8BIT(ms_card) … #define CHK_MS4BIT(ms_card) … struct ms_delay_write_tag { … }; struct ms_info { … }; struct spi_info { … }; /************/ /* LUN mode */ /************/ /* Single LUN, support xD/SD/MS */ #define DEFAULT_SINGLE … /* 2 LUN mode, support SD/MS */ #define SD_MS_2LUN … /* Single LUN, but only support SD/MS, for Barossa LQFP */ #define SD_MS_1LUN … #define LAST_LUN_MODE … /* Barossa package */ #define QFN … #define LQFP … /******************/ /* sd_ctl bit map */ /******************/ /* SD push point control, bit 0, 1 */ #define SD_PUSH_POINT_CTL_MASK … #define SD_PUSH_POINT_DELAY … #define SD_PUSH_POINT_AUTO … /* SD sample point control, bit 2, 3 */ #define SD_SAMPLE_POINT_CTL_MASK … #define SD_SAMPLE_POINT_DELAY … #define SD_SAMPLE_POINT_AUTO … /* SD DDR Tx phase set by user, bit 4 */ #define SD_DDR_TX_PHASE_SET_BY_USER … /* MMC DDR Tx phase set by user, bit 5 */ #define MMC_DDR_TX_PHASE_SET_BY_USER … /* Support MMC DDR mode, bit 6 */ #define SUPPORT_MMC_DDR_MODE … /* Reset MMC at first */ #define RESET_MMC_FIRST … #define SEQ_START_CRITERIA … /* MS Power Class En */ #define POWER_CLASS_2_EN … #define POWER_CLASS_1_EN … #define MAX_SHOW_CNT … #define MAX_RESET_CNT … #define SDIO_EXIST … #define SDIO_IGNORED … #define CHK_SDIO_EXIST(chip) … #define SET_SDIO_EXIST(chip) … #define CLR_SDIO_EXIST(chip) … #define CHK_SDIO_IGNORED(chip) … #define SET_SDIO_IGNORED(chip) … #define CLR_SDIO_IGNORED(chip) … struct rtsx_chip { … }; static inline struct device *rtsx_dev(const struct rtsx_chip *chip) { … } #define rtsx_set_stat(chip, stat) … #define rtsx_get_stat(chip) … #define rtsx_chk_stat(chip, stat) … #define RTSX_SET_DELINK(chip) … #define RTSX_CLR_DELINK(chip) … #define RTSX_TST_DELINK(chip) … #define CHECK_PID(chip, pid) … #define CHECK_BARO_PKG(chip, pkg) … #define CHECK_LUN_MODE(chip, mode) … /* Power down control */ #define SSC_PDCTL … #define OC_PDCTL … int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl); int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl); void rtsx_enable_card_int(struct rtsx_chip *chip); void rtsx_enable_bus_int(struct rtsx_chip *chip); void rtsx_disable_bus_int(struct rtsx_chip *chip); int rtsx_reset_chip(struct rtsx_chip *chip); int rtsx_init_chip(struct rtsx_chip *chip); void rtsx_release_chip(struct rtsx_chip *chip); void rtsx_polling_func(struct rtsx_chip *chip); void rtsx_stop_cmd(struct rtsx_chip *chip, int card); int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data); int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val); int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len); int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len); int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); void rtsx_enter_ss(struct rtsx_chip *chip); void rtsx_exit_ss(struct rtsx_chip *chip); int rtsx_pre_handle_interrupt(struct rtsx_chip *chip); void rtsx_enter_L1(struct rtsx_chip *chip); void rtsx_exit_L1(struct rtsx_chip *chip); void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat); void rtsx_enable_aspm(struct rtsx_chip *chip); void rtsx_disable_aspm(struct rtsx_chip *chip); int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); int rtsx_check_chip_exist(struct rtsx_chip *chip); #endif /* __REALTEK_RTSX_CHIP_H */
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