/* SPDX-License-Identifier: GPL-2.0+ */ /* * Driver for Realtek PCI-Express card reader * * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. * * Author: * Wei WANG ([email protected]) * Micky Ching ([email protected]) */ #ifndef __REALTEK_RTSX_SD_H #define __REALTEK_RTSX_SD_H #include "rtsx_chip.h" #define SUPPORT_VOLTAGE … /* Error Code */ #define SD_NO_ERROR … #define SD_CRC_ERR … #define SD_TO_ERR … #define SD_NO_CARD … #define SD_BUSY … #define SD_STS_ERR … #define SD_RSP_TIMEOUT … #define SD_IO_ERR … /* Return code for MMC switch bus */ #define SWITCH_SUCCESS … #define SWITCH_ERR … #define SWITCH_FAIL … /* MMC/SD Command Index */ /* Basic command (class 0) */ #define GO_IDLE_STATE … #define SEND_OP_COND … #define ALL_SEND_CID … #define SET_RELATIVE_ADDR … #define SEND_RELATIVE_ADDR … #define SET_DSR … #define IO_SEND_OP_COND … #define SWITCH … #define SELECT_CARD … #define DESELECT_CARD … /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec * while is "SEND_IF_COND" for SD 2.0 */ #define SEND_EXT_CSD … #define SEND_IF_COND … #define SEND_CSD … #define SEND_CID … #define VOLTAGE_SWITCH … #define READ_DAT_UTIL_STOP … #define STOP_TRANSMISSION … #define SEND_STATUS … #define GO_INACTIVE_STATE … #define SET_BLOCKLEN … #define READ_SINGLE_BLOCK … #define READ_MULTIPLE_BLOCK … #define SEND_TUNING_PATTERN … #define BUSTEST_R … #define BUSTEST_W … #define WRITE_BLOCK … #define WRITE_MULTIPLE_BLOCK … #define PROGRAM_CSD … #define ERASE_WR_BLK_START … #define ERASE_WR_BLK_END … #define ERASE_CMD … #define LOCK_UNLOCK … #define IO_RW_DIRECT … #define APP_CMD … #define GEN_CMD … #define SET_BUS_WIDTH … #define SD_STATUS … #define SEND_NUM_WR_BLOCKS … #define SET_WR_BLK_ERASE_COUNT … #define SD_APP_OP_COND … #define SET_CLR_CARD_DETECT … #define SEND_SCR … #define SD_READ_COMPLETE … #define SD_READ_TO … #define SD_READ_ADVENCE … #define SD_CHECK_MODE … #define SD_SWITCH_MODE … #define SD_FUNC_GROUP_1 … #define SD_FUNC_GROUP_2 … #define SD_FUNC_GROUP_3 … #define SD_FUNC_GROUP_4 … #define SD_CHECK_SPEC_V1_1 … #define NO_ARGUMENT … #define CHECK_PATTERN … #define VOLTAGE_SUPPLY_RANGE … #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY … #define SUPPORT_MAX_POWER_PERMANCE … #define SUPPORT_1V8 … #define SWITCH_NO_ERR … #define CARD_NOT_EXIST … #define SPEC_NOT_SUPPORT … #define CHECK_MODE_ERR … #define CHECK_NOT_READY … #define SWITCH_CRC_ERR … #define SWITCH_MODE_ERR … #define SWITCH_PASS … #ifdef SUPPORT_SD_LOCK #define SD_ERASE … #define SD_LOCK … #define SD_UNLOCK … #define SD_CLR_PWD … #define SD_SET_PWD … #define SD_PWD_LEN … #define SD_LOCKED … #define SD_LOCK_1BIT_MODE … #define SD_PWD_EXIST … #define SD_UNLOCK_POW_ON … #define SD_SDR_RST … #define SD_NOT_ERASE … #define SD_UNDER_ERASING … #define SD_COMPLETE_ERASE … #define SD_RW_FORBIDDEN … #endif #define HS_SUPPORT … #define SDR50_SUPPORT … #define SDR104_SUPPORT … #define DDR50_SUPPORT … #define HS_SUPPORT_MASK … #define SDR50_SUPPORT_MASK … #define SDR104_SUPPORT_MASK … #define DDR50_SUPPORT_MASK … #define HS_QUERY_SWITCH_OK … #define SDR50_QUERY_SWITCH_OK … #define SDR104_QUERY_SWITCH_OK … #define DDR50_QUERY_SWITCH_OK … #define HS_SWITCH_BUSY … #define SDR50_SWITCH_BUSY … #define SDR104_SWITCH_BUSY … #define DDR50_SWITCH_BUSY … #define FUNCTION_GROUP1_SUPPORT_OFFSET … #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET … #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET … #define DRIVING_TYPE_A … #define DRIVING_TYPE_B … #define DRIVING_TYPE_C … #define DRIVING_TYPE_D … #define DRIVING_TYPE_A_MASK … #define DRIVING_TYPE_B_MASK … #define DRIVING_TYPE_C_MASK … #define DRIVING_TYPE_D_MASK … #define TYPE_A_QUERY_SWITCH_OK … #define TYPE_B_QUERY_SWITCH_OK … #define TYPE_C_QUERY_SWITCH_OK … #define TYPE_D_QUERY_SWITCH_OK … #define TYPE_A_SWITCH_BUSY … #define TYPE_B_SWITCH_BUSY … #define TYPE_C_SWITCH_BUSY … #define TYPE_D_SWITCH_BUSY … #define FUNCTION_GROUP3_SUPPORT_OFFSET … #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET … #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET … #define CURRENT_LIMIT_200 … #define CURRENT_LIMIT_400 … #define CURRENT_LIMIT_600 … #define CURRENT_LIMIT_800 … #define CURRENT_LIMIT_200_MASK … #define CURRENT_LIMIT_400_MASK … #define CURRENT_LIMIT_600_MASK … #define CURRENT_LIMIT_800_MASK … #define CURRENT_LIMIT_200_QUERY_SWITCH_OK … #define CURRENT_LIMIT_400_QUERY_SWITCH_OK … #define CURRENT_LIMIT_600_QUERY_SWITCH_OK … #define CURRENT_LIMIT_800_QUERY_SWITCH_OK … #define CURRENT_LIMIT_200_SWITCH_BUSY … #define CURRENT_LIMIT_400_SWITCH_BUSY … #define CURRENT_LIMIT_600_SWITCH_BUSY … #define CURRENT_LIMIT_800_SWITCH_BUSY … #define FUNCTION_GROUP4_SUPPORT_OFFSET … #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET … #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET … #define DATA_STRUCTURE_VER_OFFSET … #define MAX_PHASE … #define MMC_8BIT_BUS … #define MMC_4BIT_BUS … #define MMC_SWITCH_ERR … #define SD_IO_3V3 … #define SD_IO_1V8 … #define TUNE_TX … #define TUNE_RX … #define CHANGE_TX … #define CHANGE_RX … #define DCM_HIGH_FREQUENCY_MODE … #define DCM_LOW_FREQUENCY_MODE … #define DCM_HIGH_FREQUENCY_MODE_SET … #define DCM_LOW_FREQUENCY_MODE_SET … #define MULTIPLY_BY_1 … #define MULTIPLY_BY_2 … #define MULTIPLY_BY_3 … #define MULTIPLY_BY_4 … #define MULTIPLY_BY_5 … #define MULTIPLY_BY_6 … #define MULTIPLY_BY_7 … #define MULTIPLY_BY_8 … #define MULTIPLY_BY_9 … #define MULTIPLY_BY_10 … #define DIVIDE_BY_2 … #define DIVIDE_BY_3 … #define DIVIDE_BY_4 … #define DIVIDE_BY_5 … #define DIVIDE_BY_6 … #define DIVIDE_BY_7 … #define DIVIDE_BY_8 … #define DIVIDE_BY_9 … #define DIVIDE_BY_10 … struct timing_phase_path { … }; int sd_select_card(struct rtsx_chip *chip, int select); int sd_pull_ctl_enable(struct rtsx_chip *chip); int reset_sd_card(struct rtsx_chip *chip); int sd_switch_clock(struct rtsx_chip *chip); void sd_stop_seq_mode(struct rtsx_chip *chip); int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt); void sd_cleanup_work(struct rtsx_chip *chip); int sd_power_off_card3v3(struct rtsx_chip *chip); int release_sd_card(struct rtsx_chip *chip); #ifdef SUPPORT_CPRM int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, bool special_check); int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type); int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip); int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip); #endif #endif /* __REALTEK_RTSX_SD_H */
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