/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * tsi148.h * * Support for the Tundra TSI148 VME Bridge chip * * Author: Tom Armistead * Updated and maintained by Ajit Prem * Copyright 2004 Motorola Inc. */ #ifndef TSI148_H #define TSI148_H #ifndef PCI_VENDOR_ID_TUNDRA #define PCI_VENDOR_ID_TUNDRA … #endif #ifndef PCI_DEVICE_ID_TUNDRA_TSI148 #define PCI_DEVICE_ID_TUNDRA_TSI148 … #endif /* * Define the number of each that the Tsi148 supports. */ #define TSI148_MAX_MASTER … #define TSI148_MAX_SLAVE … #define TSI148_MAX_DMA … #define TSI148_MAX_MAILBOX … #define TSI148_MAX_SEMAPHORE … /* Structure used to hold driver specific information */ struct tsi148_driver { … }; /* * Layout of a DMAC Linked-List Descriptor * * Note: This structure is accessed via the chip and therefore must be * correctly laid out - It must also be aligned on 64-bit boundaries. */ struct tsi148_dma_descriptor { … }; struct tsi148_dma_entry { … }; /* * TSI148 ASIC register structure overlays and bit field definitions. * * Note: Tsi148 Register Group (CRG) consists of the following * combination of registers: * PCFS - PCI Configuration Space Registers * LCSR - Local Control and Status Registers * GCSR - Global Control and Status Registers * CR/CSR - Subset of Configuration ROM / * Control and Status Registers */ /* * Command/Status Registers (CRG + $004) */ #define TSI148_PCFS_ID … #define TSI148_PCFS_CSR … #define TSI148_PCFS_CLASS … #define TSI148_PCFS_MISC0 … #define TSI148_PCFS_MBARL … #define TSI148_PCFS_MBARU … #define TSI148_PCFS_SUBID … #define TSI148_PCFS_CAPP … #define TSI148_PCFS_MISC1 … #define TSI148_PCFS_XCAPP … #define TSI148_PCFS_XSTAT … /* * LCSR definitions */ /* * Outbound Translations */ #define TSI148_LCSR_OT0_OTSAU … #define TSI148_LCSR_OT0_OTSAL … #define TSI148_LCSR_OT0_OTEAU … #define TSI148_LCSR_OT0_OTEAL … #define TSI148_LCSR_OT0_OTOFU … #define TSI148_LCSR_OT0_OTOFL … #define TSI148_LCSR_OT0_OTBS … #define TSI148_LCSR_OT0_OTAT … #define TSI148_LCSR_OT1_OTSAU … #define TSI148_LCSR_OT1_OTSAL … #define TSI148_LCSR_OT1_OTEAU … #define TSI148_LCSR_OT1_OTEAL … #define TSI148_LCSR_OT1_OTOFU … #define TSI148_LCSR_OT1_OTOFL … #define TSI148_LCSR_OT1_OTBS … #define TSI148_LCSR_OT1_OTAT … #define TSI148_LCSR_OT2_OTSAU … #define TSI148_LCSR_OT2_OTSAL … #define TSI148_LCSR_OT2_OTEAU … #define TSI148_LCSR_OT2_OTEAL … #define TSI148_LCSR_OT2_OTOFU … #define TSI148_LCSR_OT2_OTOFL … #define TSI148_LCSR_OT2_OTBS … #define TSI148_LCSR_OT2_OTAT … #define TSI148_LCSR_OT3_OTSAU … #define TSI148_LCSR_OT3_OTSAL … #define TSI148_LCSR_OT3_OTEAU … #define TSI148_LCSR_OT3_OTEAL … #define TSI148_LCSR_OT3_OTOFU … #define TSI148_LCSR_OT3_OTOFL … #define TSI148_LCSR_OT3_OTBS … #define TSI148_LCSR_OT3_OTAT … #define TSI148_LCSR_OT4_OTSAU … #define TSI148_LCSR_OT4_OTSAL … #define TSI148_LCSR_OT4_OTEAU … #define TSI148_LCSR_OT4_OTEAL … #define TSI148_LCSR_OT4_OTOFU … #define TSI148_LCSR_OT4_OTOFL … #define TSI148_LCSR_OT4_OTBS … #define TSI148_LCSR_OT4_OTAT … #define TSI148_LCSR_OT5_OTSAU … #define TSI148_LCSR_OT5_OTSAL … #define TSI148_LCSR_OT5_OTEAU … #define TSI148_LCSR_OT5_OTEAL … #define TSI148_LCSR_OT5_OTOFU … #define TSI148_LCSR_OT5_OTOFL … #define TSI148_LCSR_OT5_OTBS … #define TSI148_LCSR_OT5_OTAT … #define TSI148_LCSR_OT6_OTSAU … #define TSI148_LCSR_OT6_OTSAL … #define TSI148_LCSR_OT6_OTEAU … #define TSI148_LCSR_OT6_OTEAL … #define TSI148_LCSR_OT6_OTOFU … #define TSI148_LCSR_OT6_OTOFL … #define TSI148_LCSR_OT6_OTBS … #define TSI148_LCSR_OT6_OTAT … #define TSI148_LCSR_OT7_OTSAU … #define TSI148_LCSR_OT7_OTSAL … #define TSI148_LCSR_OT7_OTEAU … #define TSI148_LCSR_OT7_OTEAL … #define TSI148_LCSR_OT7_OTOFU … #define TSI148_LCSR_OT7_OTOFL … #define TSI148_LCSR_OT7_OTBS … #define TSI148_LCSR_OT7_OTAT … #define TSI148_LCSR_OT0 … #define TSI148_LCSR_OT1 … #define TSI148_LCSR_OT2 … #define TSI148_LCSR_OT3 … #define TSI148_LCSR_OT4 … #define TSI148_LCSR_OT5 … #define TSI148_LCSR_OT6 … #define TSI148_LCSR_OT7 … static const int TSI148_LCSR_OT[8] = …; #define TSI148_LCSR_OFFSET_OTSAU … #define TSI148_LCSR_OFFSET_OTSAL … #define TSI148_LCSR_OFFSET_OTEAU … #define TSI148_LCSR_OFFSET_OTEAL … #define TSI148_LCSR_OFFSET_OTOFU … #define TSI148_LCSR_OFFSET_OTOFL … #define TSI148_LCSR_OFFSET_OTBS … #define TSI148_LCSR_OFFSET_OTAT … /* * VMEbus interrupt ack * offset 0x200 */ #define TSI148_LCSR_VIACK1 … #define TSI148_LCSR_VIACK2 … #define TSI148_LCSR_VIACK3 … #define TSI148_LCSR_VIACK4 … #define TSI148_LCSR_VIACK5 … #define TSI148_LCSR_VIACK6 … #define TSI148_LCSR_VIACK7 … static const int TSI148_LCSR_VIACK[8] = …; /* * RMW * offset 0x220 */ #define TSI148_LCSR_RMWAU … #define TSI148_LCSR_RMWAL … #define TSI148_LCSR_RMWEN … #define TSI148_LCSR_RMWC … #define TSI148_LCSR_RMWS … /* * VMEbus control * offset 0x234 */ #define TSI148_LCSR_VMCTRL … #define TSI148_LCSR_VCTRL … #define TSI148_LCSR_VSTAT … /* * PCI status * offset 0x240 */ #define TSI148_LCSR_PSTAT … /* * VME filter. * offset 0x250 */ #define TSI148_LCSR_VMEFL … /* * VME exception. * offset 0x260 */ #define TSI148_LCSR_VEAU … #define TSI148_LCSR_VEAL … #define TSI148_LCSR_VEAT … /* * PCI error * offset 0x270 */ #define TSI148_LCSR_EDPAU … #define TSI148_LCSR_EDPAL … #define TSI148_LCSR_EDPXA … #define TSI148_LCSR_EDPXS … #define TSI148_LCSR_EDPAT … /* * Inbound Translations * offset 0x300 */ #define TSI148_LCSR_IT0_ITSAU … #define TSI148_LCSR_IT0_ITSAL … #define TSI148_LCSR_IT0_ITEAU … #define TSI148_LCSR_IT0_ITEAL … #define TSI148_LCSR_IT0_ITOFU … #define TSI148_LCSR_IT0_ITOFL … #define TSI148_LCSR_IT0_ITAT … #define TSI148_LCSR_IT1_ITSAU … #define TSI148_LCSR_IT1_ITSAL … #define TSI148_LCSR_IT1_ITEAU … #define TSI148_LCSR_IT1_ITEAL … #define TSI148_LCSR_IT1_ITOFU … #define TSI148_LCSR_IT1_ITOFL … #define TSI148_LCSR_IT1_ITAT … #define TSI148_LCSR_IT2_ITSAU … #define TSI148_LCSR_IT2_ITSAL … #define TSI148_LCSR_IT2_ITEAU … #define TSI148_LCSR_IT2_ITEAL … #define TSI148_LCSR_IT2_ITOFU … #define TSI148_LCSR_IT2_ITOFL … #define TSI148_LCSR_IT2_ITAT … #define TSI148_LCSR_IT3_ITSAU … #define TSI148_LCSR_IT3_ITSAL … #define TSI148_LCSR_IT3_ITEAU … #define TSI148_LCSR_IT3_ITEAL … #define TSI148_LCSR_IT3_ITOFU … #define TSI148_LCSR_IT3_ITOFL … #define TSI148_LCSR_IT3_ITAT … #define TSI148_LCSR_IT4_ITSAU … #define TSI148_LCSR_IT4_ITSAL … #define TSI148_LCSR_IT4_ITEAU … #define TSI148_LCSR_IT4_ITEAL … #define TSI148_LCSR_IT4_ITOFU … #define TSI148_LCSR_IT4_ITOFL … #define TSI148_LCSR_IT4_ITAT … #define TSI148_LCSR_IT5_ITSAU … #define TSI148_LCSR_IT5_ITSAL … #define TSI148_LCSR_IT5_ITEAU … #define TSI148_LCSR_IT5_ITEAL … #define TSI148_LCSR_IT5_ITOFU … #define TSI148_LCSR_IT5_ITOFL … #define TSI148_LCSR_IT5_ITAT … #define TSI148_LCSR_IT6_ITSAU … #define TSI148_LCSR_IT6_ITSAL … #define TSI148_LCSR_IT6_ITEAU … #define TSI148_LCSR_IT6_ITEAL … #define TSI148_LCSR_IT6_ITOFU … #define TSI148_LCSR_IT6_ITOFL … #define TSI148_LCSR_IT6_ITAT … #define TSI148_LCSR_IT7_ITSAU … #define TSI148_LCSR_IT7_ITSAL … #define TSI148_LCSR_IT7_ITEAU … #define TSI148_LCSR_IT7_ITEAL … #define TSI148_LCSR_IT7_ITOFU … #define TSI148_LCSR_IT7_ITOFL … #define TSI148_LCSR_IT7_ITAT … #define TSI148_LCSR_IT0 … #define TSI148_LCSR_IT1 … #define TSI148_LCSR_IT2 … #define TSI148_LCSR_IT3 … #define TSI148_LCSR_IT4 … #define TSI148_LCSR_IT5 … #define TSI148_LCSR_IT6 … #define TSI148_LCSR_IT7 … static const int TSI148_LCSR_IT[8] = …; #define TSI148_LCSR_OFFSET_ITSAU … #define TSI148_LCSR_OFFSET_ITSAL … #define TSI148_LCSR_OFFSET_ITEAU … #define TSI148_LCSR_OFFSET_ITEAL … #define TSI148_LCSR_OFFSET_ITOFU … #define TSI148_LCSR_OFFSET_ITOFL … #define TSI148_LCSR_OFFSET_ITAT … /* * Inbound Translation GCSR * offset 0x400 */ #define TSI148_LCSR_GBAU … #define TSI148_LCSR_GBAL … #define TSI148_LCSR_GCSRAT … /* * Inbound Translation CRG * offset 0x40C */ #define TSI148_LCSR_CBAU … #define TSI148_LCSR_CBAL … #define TSI148_LCSR_CSRAT … /* * Inbound Translation CR/CSR * CRG * offset 0x418 */ #define TSI148_LCSR_CROU … #define TSI148_LCSR_CROL … #define TSI148_LCSR_CRAT … /* * Inbound Translation Location Monitor * offset 0x424 */ #define TSI148_LCSR_LMBAU … #define TSI148_LCSR_LMBAL … #define TSI148_LCSR_LMAT … /* * VMEbus Interrupt Control. * offset 0x430 */ #define TSI148_LCSR_BCU … #define TSI148_LCSR_BCL … #define TSI148_LCSR_BPGTR … #define TSI148_LCSR_BPCTR … #define TSI148_LCSR_VICR … /* * Local Bus Interrupt Control. * offset 0x448 */ #define TSI148_LCSR_INTEN … #define TSI148_LCSR_INTEO … #define TSI148_LCSR_INTS … #define TSI148_LCSR_INTC … #define TSI148_LCSR_INTM1 … #define TSI148_LCSR_INTM2 … /* * DMA Controllers * offset 0x500 */ #define TSI148_LCSR_DCTL0 … #define TSI148_LCSR_DSTA0 … #define TSI148_LCSR_DCSAU0 … #define TSI148_LCSR_DCSAL0 … #define TSI148_LCSR_DCDAU0 … #define TSI148_LCSR_DCDAL0 … #define TSI148_LCSR_DCLAU0 … #define TSI148_LCSR_DCLAL0 … #define TSI148_LCSR_DSAU0 … #define TSI148_LCSR_DSAL0 … #define TSI148_LCSR_DDAU0 … #define TSI148_LCSR_DDAL0 … #define TSI148_LCSR_DSAT0 … #define TSI148_LCSR_DDAT0 … #define TSI148_LCSR_DNLAU0 … #define TSI148_LCSR_DNLAL0 … #define TSI148_LCSR_DCNT0 … #define TSI148_LCSR_DDBS0 … #define TSI148_LCSR_DCTL1 … #define TSI148_LCSR_DSTA1 … #define TSI148_LCSR_DCSAU1 … #define TSI148_LCSR_DCSAL1 … #define TSI148_LCSR_DCDAU1 … #define TSI148_LCSR_DCDAL1 … #define TSI148_LCSR_DCLAU1 … #define TSI148_LCSR_DCLAL1 … #define TSI148_LCSR_DSAU1 … #define TSI148_LCSR_DSAL1 … #define TSI148_LCSR_DDAU1 … #define TSI148_LCSR_DDAL1 … #define TSI148_LCSR_DSAT1 … #define TSI148_LCSR_DDAT1 … #define TSI148_LCSR_DNLAU1 … #define TSI148_LCSR_DNLAL1 … #define TSI148_LCSR_DCNT1 … #define TSI148_LCSR_DDBS1 … #define TSI148_LCSR_DMA0 … #define TSI148_LCSR_DMA1 … static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = …; #define TSI148_LCSR_OFFSET_DCTL … #define TSI148_LCSR_OFFSET_DSTA … #define TSI148_LCSR_OFFSET_DCSAU … #define TSI148_LCSR_OFFSET_DCSAL … #define TSI148_LCSR_OFFSET_DCDAU … #define TSI148_LCSR_OFFSET_DCDAL … #define TSI148_LCSR_OFFSET_DCLAU … #define TSI148_LCSR_OFFSET_DCLAL … #define TSI148_LCSR_OFFSET_DSAU … #define TSI148_LCSR_OFFSET_DSAL … #define TSI148_LCSR_OFFSET_DDAU … #define TSI148_LCSR_OFFSET_DDAL … #define TSI148_LCSR_OFFSET_DSAT … #define TSI148_LCSR_OFFSET_DDAT … #define TSI148_LCSR_OFFSET_DNLAU … #define TSI148_LCSR_OFFSET_DNLAL … #define TSI148_LCSR_OFFSET_DCNT … #define TSI148_LCSR_OFFSET_DDBS … /* * GCSR Register Group */ /* * GCSR CRG * offset 0x00 0x600 - DEVI/VENI * offset 0x04 0x604 - CTRL/GA/REVID * offset 0x08 0x608 - Semaphore3/2/1/0 * offset 0x0C 0x60C - Seamphore7/6/5/4 */ #define TSI148_GCSR_ID … #define TSI148_GCSR_CSR … #define TSI148_GCSR_SEMA0 … #define TSI148_GCSR_SEMA1 … /* * Mail Box * GCSR CRG * offset 0x10 0x610 - Mailbox0 */ #define TSI148_GCSR_MBOX0 … #define TSI148_GCSR_MBOX1 … #define TSI148_GCSR_MBOX2 … #define TSI148_GCSR_MBOX3 … static const int TSI148_GCSR_MBOX[4] = …; /* * CR/CSR */ /* * CR/CSR CRG * offset 0x7FFF4 0xFF4 - CSRBCR * offset 0x7FFF8 0xFF8 - CSRBSR * offset 0x7FFFC 0xFFC - CBAR */ #define TSI148_CSRBCR … #define TSI148_CSRBSR … #define TSI148_CBAR … /* * TSI148 Register Bit Definitions */ /* * PFCS Register Set */ #define TSI148_PCFS_CMMD_SERR … #define TSI148_PCFS_CMMD_PERR … #define TSI148_PCFS_CMMD_MSTR … #define TSI148_PCFS_CMMD_MEMSP … #define TSI148_PCFS_CMMD_IOSP … #define TSI148_PCFS_STAT_RCPVE … #define TSI148_PCFS_STAT_SIGSE … #define TSI148_PCFS_STAT_RCVMA … #define TSI148_PCFS_STAT_RCVTA … #define TSI148_PCFS_STAT_SIGTA … #define TSI148_PCFS_STAT_SELTIM … #define TSI148_PCFS_STAT_DPAR … #define TSI148_PCFS_STAT_FAST … #define TSI148_PCFS_STAT_P66M … #define TSI148_PCFS_STAT_CAPL … /* * Revision ID/Class Code Registers (CRG +$008) */ #define TSI148_PCFS_CLAS_M … #define TSI148_PCFS_SUBCLAS_M … #define TSI148_PCFS_PROGIF_M … #define TSI148_PCFS_REVID_M … /* * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C) */ #define TSI148_PCFS_HEAD_M … #define TSI148_PCFS_MLAT_M … #define TSI148_PCFS_CLSZ_M … /* * Memory Base Address Lower Reg (CRG + $010) */ #define TSI148_PCFS_MBARL_BASEL_M … #define TSI148_PCFS_MBARL_PRE … #define TSI148_PCFS_MBARL_MTYPE_M … #define TSI148_PCFS_MBARL_IOMEM … /* * Message Signaled Interrupt Capabilities Register (CRG + $040) */ #define TSI148_PCFS_MSICAP_64BAC … #define TSI148_PCFS_MSICAP_MME_M … #define TSI148_PCFS_MSICAP_MMC_M … #define TSI148_PCFS_MSICAP_MSIEN … /* * Message Address Lower Register (CRG +$044) */ #define TSI148_PCFS_MSIAL_M … /* * Message Data Register (CRG + 4C) */ #define TSI148_PCFS_MSIMD_M … /* * PCI-X Capabilities Register (CRG + $050) */ #define TSI148_PCFS_PCIXCAP_MOST_M … #define TSI148_PCFS_PCIXCAP_MMRBC_M … #define TSI148_PCFS_PCIXCAP_ERO … #define TSI148_PCFS_PCIXCAP_DPERE … /* * PCI-X Status Register (CRG +$054) */ #define TSI148_PCFS_PCIXSTAT_RSCEM … #define TSI148_PCFS_PCIXSTAT_DMCRS_M … #define TSI148_PCFS_PCIXSTAT_DMOST_M … #define TSI148_PCFS_PCIXSTAT_DMMRC_M … #define TSI148_PCFS_PCIXSTAT_DC … #define TSI148_PCFS_PCIXSTAT_USC … #define TSI148_PCFS_PCIXSTAT_SCD … #define TSI148_PCFS_PCIXSTAT_133C … #define TSI148_PCFS_PCIXSTAT_64D … #define TSI148_PCFS_PCIXSTAT_BN_M … #define TSI148_PCFS_PCIXSTAT_DN_M … #define TSI148_PCFS_PCIXSTAT_FN_M … /* * LCSR Registers */ /* * Outbound Translation Starting Address Lower */ #define TSI148_LCSR_OTSAL_M … /* * Outbound Translation Ending Address Lower */ #define TSI148_LCSR_OTEAL_M … /* * Outbound Translation Offset Lower */ #define TSI148_LCSR_OTOFFL_M … /* * Outbound Translation 2eSST Broadcast Select */ #define TSI148_LCSR_OTBS_M … /* * Outbound Translation Attribute */ #define TSI148_LCSR_OTAT_EN … #define TSI148_LCSR_OTAT_MRPFD … #define TSI148_LCSR_OTAT_PFS_M … #define TSI148_LCSR_OTAT_PFS_2 … #define TSI148_LCSR_OTAT_PFS_4 … #define TSI148_LCSR_OTAT_PFS_8 … #define TSI148_LCSR_OTAT_PFS_16 … #define TSI148_LCSR_OTAT_2eSSTM_M … #define TSI148_LCSR_OTAT_2eSSTM_160 … #define TSI148_LCSR_OTAT_2eSSTM_267 … #define TSI148_LCSR_OTAT_2eSSTM_320 … #define TSI148_LCSR_OTAT_TM_M … #define TSI148_LCSR_OTAT_TM_SCT … #define TSI148_LCSR_OTAT_TM_BLT … #define TSI148_LCSR_OTAT_TM_MBLT … #define TSI148_LCSR_OTAT_TM_2eVME … #define TSI148_LCSR_OTAT_TM_2eSST … #define TSI148_LCSR_OTAT_TM_2eSSTB … #define TSI148_LCSR_OTAT_DBW_M … #define TSI148_LCSR_OTAT_DBW_16 … #define TSI148_LCSR_OTAT_DBW_32 … #define TSI148_LCSR_OTAT_SUP … #define TSI148_LCSR_OTAT_PGM … #define TSI148_LCSR_OTAT_AMODE_M … #define TSI148_LCSR_OTAT_AMODE_A16 … #define TSI148_LCSR_OTAT_AMODE_A24 … #define TSI148_LCSR_OTAT_AMODE_A32 … #define TSI148_LCSR_OTAT_AMODE_A64 … #define TSI148_LCSR_OTAT_AMODE_CRCSR … #define TSI148_LCSR_OTAT_AMODE_USER1 … #define TSI148_LCSR_OTAT_AMODE_USER2 … #define TSI148_LCSR_OTAT_AMODE_USER3 … #define TSI148_LCSR_OTAT_AMODE_USER4 … /* * VME Master Control Register CRG+$234 */ #define TSI148_LCSR_VMCTRL_VSA … #define TSI148_LCSR_VMCTRL_VS … #define TSI148_LCSR_VMCTRL_DHB … #define TSI148_LCSR_VMCTRL_DWB … #define TSI148_LCSR_VMCTRL_RMWEN … #define TSI148_LCSR_VMCTRL_ATO_M … #define TSI148_LCSR_VMCTRL_ATO_32 … #define TSI148_LCSR_VMCTRL_ATO_128 … #define TSI148_LCSR_VMCTRL_ATO_512 … #define TSI148_LCSR_VMCTRL_ATO_2M … #define TSI148_LCSR_VMCTRL_ATO_8M … #define TSI148_LCSR_VMCTRL_ATO_32M … #define TSI148_LCSR_VMCTRL_ATO_128M … #define TSI148_LCSR_VMCTRL_ATO_DIS … #define TSI148_LCSR_VMCTRL_VTOFF_M … #define TSI148_LCSR_VMCTRL_VTOFF_0 … #define TSI148_LCSR_VMCTRL_VTOFF_1 … #define TSI148_LCSR_VMCTRL_VTOFF_2 … #define TSI148_LCSR_VMCTRL_VTOFF_4 … #define TSI148_LCSR_VMCTRL_VTOFF_8 … #define TSI148_LCSR_VMCTRL_VTOFF_16 … #define TSI148_LCSR_VMCTRL_VTOFF_32 … #define TSI148_LCSR_VMCTRL_VTOFF_64 … #define TSI148_LCSR_VMCTRL_VTON_M … #define TSI148_LCSR_VMCTRL_VTON_4 … #define TSI148_LCSR_VMCTRL_VTON_8 … #define TSI148_LCSR_VMCTRL_VTON_16 … #define TSI148_LCSR_VMCTRL_VTON_32 … #define TSI148_LCSR_VMCTRL_VTON_64 … #define TSI148_LCSR_VMCTRL_VTON_128 … #define TSI148_LCSR_VMCTRL_VTON_256 … #define TSI148_LCSR_VMCTRL_VTON_512 … #define TSI148_LCSR_VMCTRL_VREL_M … #define TSI148_LCSR_VMCTRL_VREL_T_D … #define TSI148_LCSR_VMCTRL_VREL_T_R_D … #define TSI148_LCSR_VMCTRL_VREL_T_B_D … #define TSI148_LCSR_VMCTRL_VREL_T_D_R … #define TSI148_LCSR_VMCTRL_VFAIR … #define TSI148_LCSR_VMCTRL_VREQL_M … /* * VMEbus Control Register CRG+$238 */ #define TSI148_LCSR_VCTRL_LRE … #define TSI148_LCSR_VCTRL_DLT_M … #define TSI148_LCSR_VCTRL_DLT_OFF … #define TSI148_LCSR_VCTRL_DLT_16 … #define TSI148_LCSR_VCTRL_DLT_32 … #define TSI148_LCSR_VCTRL_DLT_64 … #define TSI148_LCSR_VCTRL_DLT_128 … #define TSI148_LCSR_VCTRL_DLT_256 … #define TSI148_LCSR_VCTRL_DLT_512 … #define TSI148_LCSR_VCTRL_DLT_1024 … #define TSI148_LCSR_VCTRL_DLT_2048 … #define TSI148_LCSR_VCTRL_DLT_4096 … #define TSI148_LCSR_VCTRL_DLT_8192 … #define TSI148_LCSR_VCTRL_DLT_16384 … #define TSI148_LCSR_VCTRL_DLT_32768 … #define TSI148_LCSR_VCTRL_NERBB … #define TSI148_LCSR_VCTRL_SRESET … #define TSI148_LCSR_VCTRL_LRESET … #define TSI148_LCSR_VCTRL_SFAILAI … #define TSI148_LCSR_VCTRL_BID_M … #define TSI148_LCSR_VCTRL_ATOEN … #define TSI148_LCSR_VCTRL_ROBIN … #define TSI148_LCSR_VCTRL_GTO_M … #define TSI148_LCSR_VCTRL_GTO_8 … #define TSI148_LCSR_VCTRL_GTO_16 … #define TSI148_LCSR_VCTRL_GTO_32 … #define TSI148_LCSR_VCTRL_GTO_64 … #define TSI148_LCSR_VCTRL_GTO_128 … #define TSI148_LCSR_VCTRL_GTO_256 … #define TSI148_LCSR_VCTRL_GTO_512 … #define TSI148_LCSR_VCTRL_GTO_DIS … /* * VMEbus Status Register CRG + $23C */ #define TSI148_LCSR_VSTAT_CPURST … #define TSI148_LCSR_VSTAT_BRDFL … #define TSI148_LCSR_VSTAT_PURSTS … #define TSI148_LCSR_VSTAT_BDFAILS … #define TSI148_LCSR_VSTAT_SYSFAILS … #define TSI148_LCSR_VSTAT_ACFAILS … #define TSI148_LCSR_VSTAT_SCONS … #define TSI148_LCSR_VSTAT_GAP … #define TSI148_LCSR_VSTAT_GA_M … /* * PCI Configuration Status Register CRG+$240 */ #define TSI148_LCSR_PSTAT_REQ64S … #define TSI148_LCSR_PSTAT_M66ENS … #define TSI148_LCSR_PSTAT_FRAMES … #define TSI148_LCSR_PSTAT_IRDYS … #define TSI148_LCSR_PSTAT_DEVSELS … #define TSI148_LCSR_PSTAT_STOPS … #define TSI148_LCSR_PSTAT_TRDYS … /* * VMEbus Exception Attributes Register CRG + $268 */ #define TSI148_LCSR_VEAT_VES … #define TSI148_LCSR_VEAT_VEOF … #define TSI148_LCSR_VEAT_VESCL … #define TSI148_LCSR_VEAT_2EOT … #define TSI148_LCSR_VEAT_2EST … #define TSI148_LCSR_VEAT_BERR … #define TSI148_LCSR_VEAT_LWORD … #define TSI148_LCSR_VEAT_WRITE … #define TSI148_LCSR_VEAT_IACK … #define TSI148_LCSR_VEAT_DS1 … #define TSI148_LCSR_VEAT_DS0 … #define TSI148_LCSR_VEAT_AM_M … #define TSI148_LCSR_VEAT_XAM_M … /* * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280 */ #define TSI148_LCSR_EDPAT_EDPCL … /* * Inbound Translation Starting Address Lower */ #define TSI148_LCSR_ITSAL6432_M … #define TSI148_LCSR_ITSAL24_M … #define TSI148_LCSR_ITSAL16_M … /* * Inbound Translation Ending Address Lower */ #define TSI148_LCSR_ITEAL6432_M … #define TSI148_LCSR_ITEAL24_M … #define TSI148_LCSR_ITEAL16_M … /* * Inbound Translation Offset Lower */ #define TSI148_LCSR_ITOFFL6432_M … #define TSI148_LCSR_ITOFFL24_M … #define TSI148_LCSR_ITOFFL16_M … /* * Inbound Translation Attribute */ #define TSI148_LCSR_ITAT_EN … #define TSI148_LCSR_ITAT_TH … #define TSI148_LCSR_ITAT_VFS_M … #define TSI148_LCSR_ITAT_VFS_64 … #define TSI148_LCSR_ITAT_VFS_128 … #define TSI148_LCSR_ITAT_VFS_256 … #define TSI148_LCSR_ITAT_VFS_512 … #define TSI148_LCSR_ITAT_2eSSTM_M … #define TSI148_LCSR_ITAT_2eSSTM_160 … #define TSI148_LCSR_ITAT_2eSSTM_267 … #define TSI148_LCSR_ITAT_2eSSTM_320 … #define TSI148_LCSR_ITAT_2eSSTB … #define TSI148_LCSR_ITAT_2eSST … #define TSI148_LCSR_ITAT_2eVME … #define TSI148_LCSR_ITAT_MBLT … #define TSI148_LCSR_ITAT_BLT … #define TSI148_LCSR_ITAT_AS_M … #define TSI148_LCSR_ITAT_AS_A16 … #define TSI148_LCSR_ITAT_AS_A24 … #define TSI148_LCSR_ITAT_AS_A32 … #define TSI148_LCSR_ITAT_AS_A64 … #define TSI148_LCSR_ITAT_SUPR … #define TSI148_LCSR_ITAT_NPRIV … #define TSI148_LCSR_ITAT_PGM … #define TSI148_LCSR_ITAT_DATA … /* * GCSR Base Address Lower Address CRG +$404 */ #define TSI148_LCSR_GBAL_M … /* * GCSR Attribute Register CRG + $408 */ #define TSI148_LCSR_GCSRAT_EN … #define TSI148_LCSR_GCSRAT_AS_M … #define TSI148_LCSR_GCSRAT_AS_A16 … #define TSI148_LCSR_GCSRAT_AS_A24 … #define TSI148_LCSR_GCSRAT_AS_A32 … #define TSI148_LCSR_GCSRAT_AS_A64 … #define TSI148_LCSR_GCSRAT_SUPR … #define TSI148_LCSR_GCSRAT_NPRIV … #define TSI148_LCSR_GCSRAT_PGM … #define TSI148_LCSR_GCSRAT_DATA … /* * CRG Base Address Lower Address CRG + $410 */ #define TSI148_LCSR_CBAL_M … /* * CRG Attribute Register CRG + $414 */ #define TSI148_LCSR_CRGAT_EN … #define TSI148_LCSR_CRGAT_AS_M … #define TSI148_LCSR_CRGAT_AS_A16 … #define TSI148_LCSR_CRGAT_AS_A24 … #define TSI148_LCSR_CRGAT_AS_A32 … #define TSI148_LCSR_CRGAT_AS_A64 … #define TSI148_LCSR_CRGAT_SUPR … #define TSI148_LCSR_CRGAT_NPRIV … #define TSI148_LCSR_CRGAT_PGM … #define TSI148_LCSR_CRGAT_DATA … /* * CR/CSR Offset Lower Register CRG + $41C */ #define TSI148_LCSR_CROL_M … /* * CR/CSR Attribute register CRG + $420 */ #define TSI148_LCSR_CRAT_EN … /* * Location Monitor base address lower register CRG + $428 */ #define TSI148_LCSR_LMBAL_M … /* * Location Monitor Attribute Register CRG + $42C */ #define TSI148_LCSR_LMAT_EN … #define TSI148_LCSR_LMAT_AS_M … #define TSI148_LCSR_LMAT_AS_A16 … #define TSI148_LCSR_LMAT_AS_A24 … #define TSI148_LCSR_LMAT_AS_A32 … #define TSI148_LCSR_LMAT_AS_A64 … #define TSI148_LCSR_LMAT_SUPR … #define TSI148_LCSR_LMAT_NPRIV … #define TSI148_LCSR_LMAT_PGM … #define TSI148_LCSR_LMAT_DATA … /* * Broadcast Pulse Generator Timer Register CRG + $438 */ #define TSI148_LCSR_BPGTR_BPGT_M … /* * Broadcast Programmable Clock Timer Register CRG + $43C */ #define TSI148_LCSR_BPCTR_BPCT_M … /* * VMEbus Interrupt Control Register CRG + $43C */ #define TSI148_LCSR_VICR_CNTS_M … #define TSI148_LCSR_VICR_CNTS_DIS … #define TSI148_LCSR_VICR_CNTS_IRQ1 … #define TSI148_LCSR_VICR_CNTS_IRQ2 … #define TSI148_LCSR_VICR_EDGIS_M … #define TSI148_LCSR_VICR_EDGIS_DIS … #define TSI148_LCSR_VICR_EDGIS_IRQ1 … #define TSI148_LCSR_VICR_EDGIS_IRQ2 … #define TSI148_LCSR_VICR_IRQIF_M … #define TSI148_LCSR_VICR_IRQIF_NORM … #define TSI148_LCSR_VICR_IRQIF_PULSE … #define TSI148_LCSR_VICR_IRQIF_PROG … #define TSI148_LCSR_VICR_IRQIF_1U … #define TSI148_LCSR_VICR_IRQ2F_M … #define TSI148_LCSR_VICR_IRQ2F_NORM … #define TSI148_LCSR_VICR_IRQ2F_PULSE … #define TSI148_LCSR_VICR_IRQ2F_PROG … #define TSI148_LCSR_VICR_IRQ2F_1U … #define TSI148_LCSR_VICR_BIP … #define TSI148_LCSR_VICR_IRQC … #define TSI148_LCSR_VICR_IRQS … #define TSI148_LCSR_VICR_IRQL_M … #define TSI148_LCSR_VICR_IRQL_1 … #define TSI148_LCSR_VICR_IRQL_2 … #define TSI148_LCSR_VICR_IRQL_3 … #define TSI148_LCSR_VICR_IRQL_4 … #define TSI148_LCSR_VICR_IRQL_5 … #define TSI148_LCSR_VICR_IRQL_6 … #define TSI148_LCSR_VICR_IRQL_7 … static const int TSI148_LCSR_VICR_IRQL[8] = …; #define TSI148_LCSR_VICR_STID_M … /* * Interrupt Enable Register CRG + $440 */ #define TSI148_LCSR_INTEN_DMA1EN … #define TSI148_LCSR_INTEN_DMA0EN … #define TSI148_LCSR_INTEN_LM3EN … #define TSI148_LCSR_INTEN_LM2EN … #define TSI148_LCSR_INTEN_LM1EN … #define TSI148_LCSR_INTEN_LM0EN … #define TSI148_LCSR_INTEN_MB3EN … #define TSI148_LCSR_INTEN_MB2EN … #define TSI148_LCSR_INTEN_MB1EN … #define TSI148_LCSR_INTEN_MB0EN … #define TSI148_LCSR_INTEN_PERREN … #define TSI148_LCSR_INTEN_VERREN … #define TSI148_LCSR_INTEN_VIEEN … #define TSI148_LCSR_INTEN_IACKEN … #define TSI148_LCSR_INTEN_SYSFLEN … #define TSI148_LCSR_INTEN_ACFLEN … #define TSI148_LCSR_INTEN_IRQ7EN … #define TSI148_LCSR_INTEN_IRQ6EN … #define TSI148_LCSR_INTEN_IRQ5EN … #define TSI148_LCSR_INTEN_IRQ4EN … #define TSI148_LCSR_INTEN_IRQ3EN … #define TSI148_LCSR_INTEN_IRQ2EN … #define TSI148_LCSR_INTEN_IRQ1EN … static const int TSI148_LCSR_INTEN_LMEN[4] = …; static const int TSI148_LCSR_INTEN_IRQEN[7] = …; /* * Interrupt Enable Out Register CRG + $444 */ #define TSI148_LCSR_INTEO_DMA1EO … #define TSI148_LCSR_INTEO_DMA0EO … #define TSI148_LCSR_INTEO_LM3EO … #define TSI148_LCSR_INTEO_LM2EO … #define TSI148_LCSR_INTEO_LM1EO … #define TSI148_LCSR_INTEO_LM0EO … #define TSI148_LCSR_INTEO_MB3EO … #define TSI148_LCSR_INTEO_MB2EO … #define TSI148_LCSR_INTEO_MB1EO … #define TSI148_LCSR_INTEO_MB0EO … #define TSI148_LCSR_INTEO_PERREO … #define TSI148_LCSR_INTEO_VERREO … #define TSI148_LCSR_INTEO_VIEEO … #define TSI148_LCSR_INTEO_IACKEO … #define TSI148_LCSR_INTEO_SYSFLEO … #define TSI148_LCSR_INTEO_ACFLEO … #define TSI148_LCSR_INTEO_IRQ7EO … #define TSI148_LCSR_INTEO_IRQ6EO … #define TSI148_LCSR_INTEO_IRQ5EO … #define TSI148_LCSR_INTEO_IRQ4EO … #define TSI148_LCSR_INTEO_IRQ3EO … #define TSI148_LCSR_INTEO_IRQ2EO … #define TSI148_LCSR_INTEO_IRQ1EO … static const int TSI148_LCSR_INTEO_LMEO[4] = …; static const int TSI148_LCSR_INTEO_IRQEO[7] = …; /* * Interrupt Status Register CRG + $448 */ #define TSI148_LCSR_INTS_DMA1S … #define TSI148_LCSR_INTS_DMA0S … #define TSI148_LCSR_INTS_LM3S … #define TSI148_LCSR_INTS_LM2S … #define TSI148_LCSR_INTS_LM1S … #define TSI148_LCSR_INTS_LM0S … #define TSI148_LCSR_INTS_MB3S … #define TSI148_LCSR_INTS_MB2S … #define TSI148_LCSR_INTS_MB1S … #define TSI148_LCSR_INTS_MB0S … #define TSI148_LCSR_INTS_PERRS … #define TSI148_LCSR_INTS_VERRS … #define TSI148_LCSR_INTS_VIES … #define TSI148_LCSR_INTS_IACKS … #define TSI148_LCSR_INTS_SYSFLS … #define TSI148_LCSR_INTS_ACFLS … #define TSI148_LCSR_INTS_IRQ7S … #define TSI148_LCSR_INTS_IRQ6S … #define TSI148_LCSR_INTS_IRQ5S … #define TSI148_LCSR_INTS_IRQ4S … #define TSI148_LCSR_INTS_IRQ3S … #define TSI148_LCSR_INTS_IRQ2S … #define TSI148_LCSR_INTS_IRQ1S … static const int TSI148_LCSR_INTS_LMS[4] = …; static const int TSI148_LCSR_INTS_MBS[4] = …; /* * Interrupt Clear Register CRG + $44C */ #define TSI148_LCSR_INTC_DMA1C … #define TSI148_LCSR_INTC_DMA0C … #define TSI148_LCSR_INTC_LM3C … #define TSI148_LCSR_INTC_LM2C … #define TSI148_LCSR_INTC_LM1C … #define TSI148_LCSR_INTC_LM0C … #define TSI148_LCSR_INTC_MB3C … #define TSI148_LCSR_INTC_MB2C … #define TSI148_LCSR_INTC_MB1C … #define TSI148_LCSR_INTC_MB0C … #define TSI148_LCSR_INTC_PERRC … #define TSI148_LCSR_INTC_VERRC … #define TSI148_LCSR_INTC_VIEC … #define TSI148_LCSR_INTC_IACKC … #define TSI148_LCSR_INTC_SYSFLC … #define TSI148_LCSR_INTC_ACFLC … static const int TSI148_LCSR_INTC_LMC[4] = …; static const int TSI148_LCSR_INTC_MBC[4] = …; /* * Interrupt Map Register 1 CRG + $458 */ #define TSI148_LCSR_INTM1_DMA1M_M … #define TSI148_LCSR_INTM1_DMA0M_M … #define TSI148_LCSR_INTM1_LM3M_M … #define TSI148_LCSR_INTM1_LM2M_M … #define TSI148_LCSR_INTM1_LM1M_M … #define TSI148_LCSR_INTM1_LM0M_M … #define TSI148_LCSR_INTM1_MB3M_M … #define TSI148_LCSR_INTM1_MB2M_M … #define TSI148_LCSR_INTM1_MB1M_M … #define TSI148_LCSR_INTM1_MB0M_M … /* * Interrupt Map Register 2 CRG + $45C */ #define TSI148_LCSR_INTM2_PERRM_M … #define TSI148_LCSR_INTM2_VERRM_M … #define TSI148_LCSR_INTM2_VIEM_M … #define TSI148_LCSR_INTM2_IACKM_M … #define TSI148_LCSR_INTM2_SYSFLM_M … #define TSI148_LCSR_INTM2_ACFLM_M … #define TSI148_LCSR_INTM2_IRQ7M_M … #define TSI148_LCSR_INTM2_IRQ6M_M … #define TSI148_LCSR_INTM2_IRQ5M_M … #define TSI148_LCSR_INTM2_IRQ4M_M … #define TSI148_LCSR_INTM2_IRQ3M_M … #define TSI148_LCSR_INTM2_IRQ2M_M … #define TSI148_LCSR_INTM2_IRQ1M_M … /* * DMA Control (0-1) Registers CRG + $500 */ #define TSI148_LCSR_DCTL_ABT … #define TSI148_LCSR_DCTL_PAU … #define TSI148_LCSR_DCTL_DGO … #define TSI148_LCSR_DCTL_MOD … #define TSI148_LCSR_DCTL_VBKS_M … #define TSI148_LCSR_DCTL_VBKS_32 … #define TSI148_LCSR_DCTL_VBKS_64 … #define TSI148_LCSR_DCTL_VBKS_128 … #define TSI148_LCSR_DCTL_VBKS_256 … #define TSI148_LCSR_DCTL_VBKS_512 … #define TSI148_LCSR_DCTL_VBKS_1024 … #define TSI148_LCSR_DCTL_VBKS_2048 … #define TSI148_LCSR_DCTL_VBKS_4096 … #define TSI148_LCSR_DCTL_VBOT_M … #define TSI148_LCSR_DCTL_VBOT_0 … #define TSI148_LCSR_DCTL_VBOT_1 … #define TSI148_LCSR_DCTL_VBOT_2 … #define TSI148_LCSR_DCTL_VBOT_4 … #define TSI148_LCSR_DCTL_VBOT_8 … #define TSI148_LCSR_DCTL_VBOT_16 … #define TSI148_LCSR_DCTL_VBOT_32 … #define TSI148_LCSR_DCTL_VBOT_64 … #define TSI148_LCSR_DCTL_PBKS_M … #define TSI148_LCSR_DCTL_PBKS_32 … #define TSI148_LCSR_DCTL_PBKS_64 … #define TSI148_LCSR_DCTL_PBKS_128 … #define TSI148_LCSR_DCTL_PBKS_256 … #define TSI148_LCSR_DCTL_PBKS_512 … #define TSI148_LCSR_DCTL_PBKS_1024 … #define TSI148_LCSR_DCTL_PBKS_2048 … #define TSI148_LCSR_DCTL_PBKS_4096 … #define TSI148_LCSR_DCTL_PBOT_M … #define TSI148_LCSR_DCTL_PBOT_0 … #define TSI148_LCSR_DCTL_PBOT_1 … #define TSI148_LCSR_DCTL_PBOT_2 … #define TSI148_LCSR_DCTL_PBOT_4 … #define TSI148_LCSR_DCTL_PBOT_8 … #define TSI148_LCSR_DCTL_PBOT_16 … #define TSI148_LCSR_DCTL_PBOT_32 … #define TSI148_LCSR_DCTL_PBOT_64 … /* * DMA Status Registers (0-1) CRG + $504 */ #define TSI148_LCSR_DSTA_SMA … #define TSI148_LCSR_DSTA_RTA … #define TSI148_LCSR_DSTA_MRC … #define TSI148_LCSR_DSTA_VBE … #define TSI148_LCSR_DSTA_ABT … #define TSI148_LCSR_DSTA_PAU … #define TSI148_LCSR_DSTA_DON … #define TSI148_LCSR_DSTA_BSY … /* * DMA Current Link Address Lower (0-1) */ #define TSI148_LCSR_DCLAL_M … /* * DMA Source Attribute (0-1) Reg */ #define TSI148_LCSR_DSAT_TYP_M … #define TSI148_LCSR_DSAT_TYP_PCI … #define TSI148_LCSR_DSAT_TYP_VME … #define TSI148_LCSR_DSAT_TYP_PAT … #define TSI148_LCSR_DSAT_PSZ … #define TSI148_LCSR_DSAT_NIN … #define TSI148_LCSR_DSAT_2eSSTM_M … #define TSI148_LCSR_DSAT_2eSSTM_160 … #define TSI148_LCSR_DSAT_2eSSTM_267 … #define TSI148_LCSR_DSAT_2eSSTM_320 … #define TSI148_LCSR_DSAT_TM_M … #define TSI148_LCSR_DSAT_TM_SCT … #define TSI148_LCSR_DSAT_TM_BLT … #define TSI148_LCSR_DSAT_TM_MBLT … #define TSI148_LCSR_DSAT_TM_2eVME … #define TSI148_LCSR_DSAT_TM_2eSST … #define TSI148_LCSR_DSAT_TM_2eSSTB … #define TSI148_LCSR_DSAT_DBW_M … #define TSI148_LCSR_DSAT_DBW_16 … #define TSI148_LCSR_DSAT_DBW_32 … #define TSI148_LCSR_DSAT_SUP … #define TSI148_LCSR_DSAT_PGM … #define TSI148_LCSR_DSAT_AMODE_M … #define TSI148_LCSR_DSAT_AMODE_A16 … #define TSI148_LCSR_DSAT_AMODE_A24 … #define TSI148_LCSR_DSAT_AMODE_A32 … #define TSI148_LCSR_DSAT_AMODE_A64 … #define TSI148_LCSR_DSAT_AMODE_CRCSR … #define TSI148_LCSR_DSAT_AMODE_USER1 … #define TSI148_LCSR_DSAT_AMODE_USER2 … #define TSI148_LCSR_DSAT_AMODE_USER3 … #define TSI148_LCSR_DSAT_AMODE_USER4 … /* * DMA Destination Attribute Registers (0-1) */ #define TSI148_LCSR_DDAT_TYP_PCI … #define TSI148_LCSR_DDAT_TYP_VME … #define TSI148_LCSR_DDAT_2eSSTM_M … #define TSI148_LCSR_DDAT_2eSSTM_160 … #define TSI148_LCSR_DDAT_2eSSTM_267 … #define TSI148_LCSR_DDAT_2eSSTM_320 … #define TSI148_LCSR_DDAT_TM_M … #define TSI148_LCSR_DDAT_TM_SCT … #define TSI148_LCSR_DDAT_TM_BLT … #define TSI148_LCSR_DDAT_TM_MBLT … #define TSI148_LCSR_DDAT_TM_2eVME … #define TSI148_LCSR_DDAT_TM_2eSST … #define TSI148_LCSR_DDAT_TM_2eSSTB … #define TSI148_LCSR_DDAT_DBW_M … #define TSI148_LCSR_DDAT_DBW_16 … #define TSI148_LCSR_DDAT_DBW_32 … #define TSI148_LCSR_DDAT_SUP … #define TSI148_LCSR_DDAT_PGM … #define TSI148_LCSR_DDAT_AMODE_M … #define TSI148_LCSR_DDAT_AMODE_A16 … #define TSI148_LCSR_DDAT_AMODE_A24 … #define TSI148_LCSR_DDAT_AMODE_A32 … #define TSI148_LCSR_DDAT_AMODE_A64 … #define TSI148_LCSR_DDAT_AMODE_CRCSR … #define TSI148_LCSR_DDAT_AMODE_USER1 … #define TSI148_LCSR_DDAT_AMODE_USER2 … #define TSI148_LCSR_DDAT_AMODE_USER3 … #define TSI148_LCSR_DDAT_AMODE_USER4 … /* * DMA Next Link Address Lower */ #define TSI148_LCSR_DNLAL_DNLAL_M … #define TSI148_LCSR_DNLAL_LLA … /* * DMA 2eSST Broadcast Select */ #define TSI148_LCSR_DBS_M … /* * GCSR Register Group */ /* * GCSR Control and Status Register CRG + $604 */ #define TSI148_GCSR_GCTRL_LRST … #define TSI148_GCSR_GCTRL_SFAILEN … #define TSI148_GCSR_GCTRL_BDFAILS … #define TSI148_GCSR_GCTRL_SCON … #define TSI148_GCSR_GCTRL_MEN … #define TSI148_GCSR_GCTRL_LMI3S … #define TSI148_GCSR_GCTRL_LMI2S … #define TSI148_GCSR_GCTRL_LMI1S … #define TSI148_GCSR_GCTRL_LMI0S … #define TSI148_GCSR_GCTRL_MBI3S … #define TSI148_GCSR_GCTRL_MBI2S … #define TSI148_GCSR_GCTRL_MBI1S … #define TSI148_GCSR_GCTRL_MBI0S … #define TSI148_GCSR_GAP … #define TSI148_GCSR_GA_M … /* * CR/CSR Register Group */ /* * CR/CSR Bit Clear Register CRG + $FF4 */ #define TSI148_CRCSR_CSRBCR_LRSTC … #define TSI148_CRCSR_CSRBCR_SFAILC … #define TSI148_CRCSR_CSRBCR_BDFAILS … #define TSI148_CRCSR_CSRBCR_MENC … #define TSI148_CRCSR_CSRBCR_BERRSC … /* * CR/CSR Bit Set Register CRG+$FF8 */ #define TSI148_CRCSR_CSRBSR_LISTS … #define TSI148_CRCSR_CSRBSR_SFAILS … #define TSI148_CRCSR_CSRBSR_BDFAILS … #define TSI148_CRCSR_CSRBSR_MENS … #define TSI148_CRCSR_CSRBSR_BERRS … /* * CR/CSR Base Address Register CRG + FFC */ #define TSI148_CRCSR_CBAR_M … #endif /* TSI148_H */
Codebase Browser
linux