linux/drivers/staging/sm750fb/ddk750_chip.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <linux/sizes.h>

#include "ddk750_reg.h"
#include "ddk750_chip.h"
#include "ddk750_power.h"

#define MHz(x)

static enum logical_chip_type chip;

enum logical_chip_type sm750_get_chip_type(void)
{}

void sm750_set_chip_type(unsigned short dev_id, u8 rev_id)
{}

static unsigned int get_mxclk_freq(void)
{}

/*
 * This function set up the main chip clock.
 *
 * Input: Frequency to be set.
 */
static void set_chip_clock(unsigned int frequency)
{}

static void set_memory_clock(unsigned int frequency)
{}

/*
 * This function set up the master clock (MCLK).
 *
 * Input: Frequency to be set.
 *
 * NOTE:
 *      The maximum frequency the engine can run is 168MHz.
 */
static void set_master_clock(unsigned int frequency)
{}

unsigned int ddk750_get_vm_size(void)
{}

int ddk750_init_hw(struct initchip_param *p_init_param)
{}

/*
 * monk liu @ 4/6/2011:
 *	re-write the calculatePLL function of ddk750.
 *	the original version function does not use
 *	some mathematics tricks and shortcut
 *	when it doing the calculation of the best N,M,D combination
 *	I think this version gives a little upgrade in speed
 *
 * 750 pll clock formular:
 * Request Clock = (Input Clock * M )/(N * X)
 *
 * Input Clock = 14318181 hz
 * X = 2 power D
 * D ={0,1,2,3,4,5,6}
 * M = {1,...,255}
 * N = {2,...,15}
 */
unsigned int sm750_calc_pll_value(unsigned int request_orig,
				  struct pll_value *pll)
{}

unsigned int sm750_format_pll_reg(struct pll_value *p_PLL)
{}