/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. * All rights reserved. * * Purpose: MAC routines * * Author: Tevin Chen * * Date: May 21, 1996 * * Revision History: * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. * 09-03-2003 Bryan YC Fan: Add vt6655_mac_dis_protect_md & vt6655_mac_en_protect_md */ #ifndef __MAC_H__ #define __MAC_H__ #include "device.h" /*--------------------- Export Definitions -------------------------*/ /* Registers in the MAC */ #define MAC_MAX_CONTEXT_SIZE_PAGE0 … #define MAC_MAX_CONTEXT_SIZE_PAGE1 … /* Registers not related to 802.11b */ #define MAC_REG_BCFG0 … #define MAC_REG_BCFG1 … #define MAC_REG_FCR0 … #define MAC_REG_FCR1 … #define MAC_REG_BISTCMD … #define MAC_REG_BISTSR0 … #define MAC_REG_BISTSR1 … #define MAC_REG_BISTSR2 … #define MAC_REG_I2MCSR … #define MAC_REG_I2MTGID … #define MAC_REG_I2MTGAD … #define MAC_REG_I2MCFG … #define MAC_REG_I2MDIPT … #define MAC_REG_I2MDOPT … #define MAC_REG_PMC0 … #define MAC_REG_PMC1 … #define MAC_REG_STICKHW … #define MAC_REG_LOCALID … #define MAC_REG_TESTCFG … #define MAC_REG_JUMPER0 … #define MAC_REG_JUMPER1 … #define MAC_REG_TMCTL0 … #define MAC_REG_TMCTL1 … #define MAC_REG_TMDATA0 … /* MAC Parameter related */ #define MAC_REG_LRT … #define MAC_REG_SRT … #define MAC_REG_SIFS … #define MAC_REG_DIFS … #define MAC_REG_EIFS … #define MAC_REG_SLOT … #define MAC_REG_BI … #define MAC_REG_CWMAXMIN0 … #define MAC_REG_LINKOFFTOTM … #define MAC_REG_SWTMOT … #define MAC_REG_MIBCNTR … #define MAC_REG_RTSOKCNT … #define MAC_REG_RTSFAILCNT … #define MAC_REG_ACKFAILCNT … #define MAC_REG_FCSERRCNT … /* TSF Related */ #define MAC_REG_TSFCNTR … #define MAC_REG_NEXTTBTT … #define MAC_REG_TSFOFST … #define MAC_REG_TFTCTL … /* WMAC Control/Status Related */ #define MAC_REG_ENCFG … #define MAC_REG_PAGE1SEL … #define MAC_REG_CFG … #define MAC_REG_TEST … #define MAC_REG_HOSTCR … #define MAC_REG_MACCR … #define MAC_REG_RCR … #define MAC_REG_TCR … #define MAC_REG_IMR … #define MAC_REG_ISR … /* Power Saving Related */ #define MAC_REG_PSCFG … #define MAC_REG_PSCTL … #define MAC_REG_PSPWRSIG … #define MAC_REG_BBCR13 … #define MAC_REG_AIDATIM … #define MAC_REG_PWBT … #define MAC_REG_WAKEOKTMR … #define MAC_REG_CALTMR … #define MAC_REG_SYNSPACCNT … #define MAC_REG_WAKSYNOPT … /* Baseband/IF Control Group */ #define MAC_REG_BBREGCTL … #define MAC_REG_CHANNEL … #define MAC_REG_BBREGADR … #define MAC_REG_BBREGDATA … #define MAC_REG_IFREGCTL … #define MAC_REG_IFDATA … #define MAC_REG_ITRTMSET … #define MAC_REG_PAPEDELAY … #define MAC_REG_SOFTPWRCTL … #define MAC_REG_GPIOCTL0 … #define MAC_REG_GPIOCTL1 … /* MAC DMA Related Group */ #define MAC_REG_TXDMACTL0 … #define MAC_REG_TXDMAPTR0 … #define MAC_REG_AC0DMACTL … #define MAC_REG_AC0DMAPTR … #define MAC_REG_BCNDMACTL … #define MAC_REG_BCNDMAPTR … #define MAC_REG_RXDMACTL0 … #define MAC_REG_RXDMAPTR0 … #define MAC_REG_RXDMACTL1 … #define MAC_REG_RXDMAPTR1 … #define MAC_REG_SYNCDMACTL … #define MAC_REG_SYNCDMAPTR … #define MAC_REG_ATIMDMACTL … #define MAC_REG_ATIMDMAPTR … /* MiscFF PIO related */ #define MAC_REG_MISCFFNDEX … #define MAC_REG_MISCFFCTL … #define MAC_REG_MISCFFDATA … /* Extend SW Timer */ #define MAC_REG_TMDATA1 … /* WOW Related Group */ #define MAC_REG_WAKEUPEN0 … #define MAC_REG_WAKEUPEN1 … #define MAC_REG_WAKEUPSR0 … #define MAC_REG_WAKEUPSR1 … #define MAC_REG_WAKE128_0 … #define MAC_REG_WAKE128_1 … #define MAC_REG_WAKE128_2 … #define MAC_REG_WAKE128_3 … /************** Page 1 ******************/ #define MAC_REG_CRC_128_0 … #define MAC_REG_CRC_128_1 … #define MAC_REG_CRC_128_2 … #define MAC_REG_CRC_128_3 … /* MAC Configuration Group */ #define MAC_REG_PAR0 … #define MAC_REG_PAR4 … #define MAC_REG_BSSID0 … #define MAC_REG_BSSID4 … #define MAC_REG_MAR0 … #define MAC_REG_MAR4 … /* MAC RSPPKT INFO Group */ #define MAC_REG_RSPINF_B_1 … #define MAC_REG_RSPINF_B_2 … #define MAC_REG_RSPINF_B_5 … #define MAC_REG_RSPINF_B_11 … #define MAC_REG_RSPINF_A_6 … #define MAC_REG_RSPINF_A_9 … #define MAC_REG_RSPINF_A_12 … #define MAC_REG_RSPINF_A_18 … #define MAC_REG_RSPINF_A_24 … #define MAC_REG_RSPINF_A_36 … #define MAC_REG_RSPINF_A_48 … #define MAC_REG_RSPINF_A_54 … #define MAC_REG_RSPINF_A_72 … /* 802.11h relative */ #define MAC_REG_QUIETINIT … #define MAC_REG_QUIETGAP … #define MAC_REG_QUIETDUR … #define MAC_REG_MSRCTL … #define MAC_REG_MSRBBSTS … #define MAC_REG_MSRSTART … #define MAC_REG_MSRDURATION … #define MAC_REG_CCAFRACTION … #define MAC_REG_PWRCCK … #define MAC_REG_PWROFDM … /* Bits in the BCFG0 register */ #define BCFG0_PERROFF … #define BCFG0_MRDMDIS … #define BCFG0_MRDLDIS … #define BCFG0_MWMEN … #define BCFG0_VSERREN … #define BCFG0_LATMEN … /* Bits in the BCFG1 register */ #define BCFG1_CFUNOPT … #define BCFG1_CREQOPT … #define BCFG1_DMA8 … #define BCFG1_ARBITOPT … #define BCFG1_PCIMEN … #define BCFG1_MIOEN … #define BCFG1_CISDLYEN … /* Bits in RAMBIST registers */ #define BISTCMD_TSTPAT5 … #define BISTCMD_TSTPATA … #define BISTCMD_TSTERR … #define BISTCMD_TSTPATF … #define BISTCMD_TSTPAT0 … #define BISTCMD_TSTMODE … #define BISTCMD_TSTITTX … #define BISTCMD_TSTATRX … #define BISTCMD_TSTATTX … #define BISTCMD_TSTRX … #define BISTSR0_BISTGO … #define BISTSR1_TSTSR … #define BISTSR2_CMDPRTEN … #define BISTSR2_RAMTSTEN … /* Bits in the I2MCFG EEPROM register */ #define I2MCFG_BOUNDCTL … #define I2MCFG_WAITCTL … #define I2MCFG_SCLOECTL … #define I2MCFG_WBUSYCTL … #define I2MCFG_NORETRY … #define I2MCFG_I2MLDSEQ … #define I2MCFG_I2CMFAST … /* Bits in the I2MCSR EEPROM register */ #define I2MCSR_EEMW … #define I2MCSR_EEMR … #define I2MCSR_AUTOLD … #define I2MCSR_NACK … #define I2MCSR_DONE … /* Bits in the PMC1 register */ #define SPS_RST … #define PCISTIKY … #define PME_OVR … /* Bits in the STICKYHW register */ #define STICKHW_DS1_SHADOW … #define STICKHW_DS0_SHADOW … /* Bits in the TMCTL register */ #define TMCTL_TSUSP … #define TMCTL_TMD … #define TMCTL_TE … /* Bits in the TFTCTL register */ #define TFTCTL_HWUTSF … #define TFTCTL_TBTTSYNC … #define TFTCTL_HWUTSFEN … #define TFTCTL_TSFCNTRRD … #define TFTCTL_TBTTSYNCEN … #define TFTCTL_TSFSYNCEN … #define TFTCTL_TSFCNTRST … #define TFTCTL_TSFCNTREN … /* Bits in the EnhanceCFG register */ #define ENCFG_BARKERPREAM … #define ENCFG_NXTBTTCFPSTR … #define ENCFG_BCNSUSCLR … #define ENCFG_BCNSUSIND … #define ENCFG_CFP_PROTECTEN … #define ENCFG_PROTECTMD … #define ENCFG_HWPARCFP … #define ENCFG_CFNULRSP … #define ENCFG_BBTYPE_MASK … #define ENCFG_BBTYPE_G … #define ENCFG_BBTYPE_B … #define ENCFG_BBTYPE_A … /* Bits in the Page1Sel register */ #define PAGE1_SEL … /* Bits in the CFG register */ #define CFG_TKIPOPT … #define CFG_RXDMAOPT … #define CFG_TMOT_SW … #define CFG_TMOT_HWLONG … #define CFG_TMOT_HW … #define CFG_CFPENDOPT … #define CFG_BCNSUSEN … #define CFG_NOTXTIMEOUT … #define CFG_NOBUFOPT … /* Bits in the TEST register */ #define TEST_LBEXT … #define TEST_LBINT … #define TEST_LBNONE … #define TEST_SOFTINT … #define TEST_CONTTX … #define TEST_TXPE … #define TEST_NAVDIS … #define TEST_NOCTS … #define TEST_NOACK … /* Bits in the HOSTCR register */ #define HOSTCR_TXONST … #define HOSTCR_RXONST … #define HOSTCR_ADHOC … #define HOSTCR_AP … #define HOSTCR_TXON … #define HOSTCR_RXON … #define HOSTCR_MACEN … #define HOSTCR_SOFTRST … /* Bits in the MACCR register */ #define MACCR_SYNCFLUSHOK … #define MACCR_SYNCFLUSH … #define MACCR_CLRNAV … /* Bits in the MAC_REG_GPIOCTL0 register */ #define LED_ACTSET … #define LED_RFOFF … #define LED_NOCONNECT … /* Bits in the RCR register */ #define RCR_SSID … #define RCR_RXALLTYPE … #define RCR_UNICAST … #define RCR_BROADCAST … #define RCR_MULTICAST … #define RCR_WPAERR … #define RCR_ERRCRC … #define RCR_BSSID … /* Bits in the TCR register */ #define TCR_SYNCDCFOPT … #define TCR_AUTOBCNTX … /* Bits in the IMR register */ #define IMR_MEASURESTART … #define IMR_QUIETSTART … #define IMR_RADARDETECT … #define IMR_MEASUREEND … #define IMR_SOFTTIMER1 … #define IMR_RXDMA1 … #define IMR_RXNOBUF … #define IMR_MIBNEARFULL … #define IMR_SOFTINT … #define IMR_FETALERR … #define IMR_WATCHDOG … #define IMR_SOFTTIMER … #define IMR_GPIO … #define IMR_TBTT … #define IMR_RXDMA0 … #define IMR_BNTX … #define IMR_AC0DMA … #define IMR_TXDMA0 … /* Bits in the ISR register */ #define ISR_MEASURESTART … #define ISR_QUIETSTART … #define ISR_RADARDETECT … #define ISR_MEASUREEND … #define ISR_SOFTTIMER1 … #define ISR_RXDMA1 … #define ISR_RXNOBUF … #define ISR_MIBNEARFULL … #define ISR_SOFTINT … #define ISR_FETALERR … #define ISR_WATCHDOG … #define ISR_SOFTTIMER … #define ISR_GPIO … #define ISR_TBTT … #define ISR_RXDMA0 … #define ISR_BNTX … #define ISR_AC0DMA … #define ISR_TXDMA0 … /* Bits in the PSCFG register */ #define PSCFG_PHILIPMD … #define PSCFG_WAKECALEN … #define PSCFG_WAKETMREN … #define PSCFG_BBPSPROG … #define PSCFG_WAKESYN … #define PSCFG_SLEEPSYN … #define PSCFG_AUTOSLEEP … /* Bits in the PSCTL register */ #define PSCTL_WAKEDONE … #define PSCTL_PS … #define PSCTL_GO2DOZE … #define PSCTL_LNBCN … #define PSCTL_ALBCN … #define PSCTL_PSEN … /* Bits in the PSPWSIG register */ #define PSSIG_WPE3 … #define PSSIG_WPE2 … #define PSSIG_WPE1 … #define PSSIG_WRADIOPE … #define PSSIG_SPE3 … #define PSSIG_SPE2 … #define PSSIG_SPE1 … #define PSSIG_SRADIOPE … /* Bits in the BBREGCTL register */ #define BBREGCTL_DONE … #define BBREGCTL_REGR … #define BBREGCTL_REGW … /* Bits in the IFREGCTL register */ #define IFREGCTL_DONE … #define IFREGCTL_IFRF … #define IFREGCTL_REGW … /* Bits in the SOFTPWRCTL register */ #define SOFTPWRCTL_RFLEOPT … #define SOFTPWRCTL_TXPEINV … #define SOFTPWRCTL_SWPECTI … #define SOFTPWRCTL_SWPAPE … #define SOFTPWRCTL_SWCALEN … #define SOFTPWRCTL_SWRADIO_PE … #define SOFTPWRCTL_SWPE2 … #define SOFTPWRCTL_SWPE1 … #define SOFTPWRCTL_SWPE3 … /* Bits in the GPIOCTL1 register */ #define GPIO1_DATA1 … #define GPIO1_MD1 … #define GPIO1_DATA0 … #define GPIO1_MD0 … /* Bits in the DMACTL register */ #define DMACTL_CLRRUN … #define DMACTL_RUN … #define DMACTL_WAKE … #define DMACTL_DEAD … #define DMACTL_ACTIVE … /* Bits in the RXDMACTL0 register */ #define RX_PERPKT … #define RX_PERPKTCLR … /* Bits in the BCNDMACTL register */ #define BEACON_READY … /* Bits in the MISCFFCTL register */ #define MISCFFCTL_WRITE … /* Bits in WAKEUPEN0 */ #define WAKEUPEN0_DIRPKT … #define WAKEUPEN0_LINKOFF … #define WAKEUPEN0_ATIMEN … #define WAKEUPEN0_TIMEN … #define WAKEUPEN0_MAGICEN … /* Bits in WAKEUPEN1 */ #define WAKEUPEN1_128_3 … #define WAKEUPEN1_128_2 … #define WAKEUPEN1_128_1 … #define WAKEUPEN1_128_0 … /* Bits in WAKEUPSR0 */ #define WAKEUPSR0_DIRPKT … #define WAKEUPSR0_LINKOFF … #define WAKEUPSR0_ATIMEN … #define WAKEUPSR0_TIMEN … #define WAKEUPSR0_MAGICEN … /* Bits in WAKEUPSR1 */ #define WAKEUPSR1_128_3 … #define WAKEUPSR1_128_2 … #define WAKEUPSR1_128_1 … #define WAKEUPSR1_128_0 … /* Bits in the MAC_REG_GPIOCTL register */ #define GPIO0_MD … #define GPIO0_DATA … #define GPIO0_INTMD … #define GPIO1_MD … #define GPIO1_DATA … /* Bits in the MSRCTL register */ #define MSRCTL_FINISH … #define MSRCTL_READY … #define MSRCTL_RADARDETECT … #define MSRCTL_EN … #define MSRCTL_QUIETTXCHK … #define MSRCTL_QUIETRPT … #define MSRCTL_QUIETINT … #define MSRCTL_QUIETEN … /* Bits in the MSRCTL1 register */ #define MSRCTL1_TXPWR … #define MSRCTL1_CSAPAREN … #define MSRCTL1_TXPAUSE … /* Loopback mode */ #define MAC_LB_EXT … #define MAC_LB_INTERNAL … #define MAC_LB_NONE … #define DEFAULT_BI … /* MiscFIFO Offset */ #define MISCFIFO_KEYETRY0 … #define MISCFIFO_KEYENTRYSIZE … #define MISCFIFO_SYNINFO_IDX … #define MISCFIFO_SYNDATA_IDX … #define MISCFIFO_SYNDATASIZE … /* enabled mask value of irq */ #define IMR_MASK_VALUE … /* max time out delay time */ #define W_MAX_TIMEOUT … /* wait time within loop */ #define CB_DELAY_LOOP_WAIT … /* revision id */ #define REV_ID_VT3253_A0 … #define REV_ID_VT3253_A1 … #define REV_ID_VT3253_B0 … #define REV_ID_VT3253_B1 … /*--------------------- Export Types ------------------------------*/ /*--------------------- Export Macros ------------------------------*/ #define VT6655_MAC_SELECT_PAGE0(iobase) … #define VT6655_MAC_SELECT_PAGE1(iobase) … #define MAKEWORD(lb, hb) … void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); void vt6655_mac_set_short_retry_limit(struct vnt_private *priv, unsigned char retry_limit); void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit); bool MACbSoftwareReset(struct vnt_private *priv); bool MACbShutdown(struct vnt_private *priv); void MACvInitialize(struct vnt_private *priv); void vt6655_mac_set_curr_rx_0_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); void vt6655_mac_set_curr_rx_1_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); void vt6655_mac_set_curr_tx_desc_addr(int tx_type, struct vnt_private *priv, u32 curr_desc_addr); void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay); void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime); void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset, u32 dwData); bool MACbPSWakeup(struct vnt_private *priv); void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char local_id); void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx); #endif /* __MAC_H__ */
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