/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ /* * Copyright (C) 2023-24 Advanced Micro Devices, Inc. All rights reserved. */ #ifndef __AMD_MANAGER_H #define __AMD_MANAGER_H #include <linux/soundwire/sdw_amd.h> #define SDW_MANAGER_REG_OFFSET … #define AMD_SDW_DEFAULT_ROWS … #define AMD_SDW_DEFAULT_COLUMNS … #define ACP_PAD_PULLDOWN_CTRL … #define ACP_SW_PAD_KEEPER_EN … #define ACP_SW0_WAKE_EN … #define ACP_EXTERNAL_INTR_CNTL0 … #define ACP_EXTERNAL_INTR_STAT0 … #define ACP_EXTERNAL_INTR_CNTL(i) … #define ACP_EXTERNAL_INTR_STAT(i) … #define ACP_SW_WAKE_EN(i) … #define ACP_SW_EN … #define ACP_SW_EN_STATUS … #define ACP_SW_FRAMESIZE … #define ACP_SW_SSP_COUNTER … #define ACP_SW_AUDIO0_TX_EN … #define ACP_SW_AUDIO0_TX_EN_STATUS … #define ACP_SW_AUDIO0_TX_FRAME_FORMAT … #define ACP_SW_AUDIO0_TX_SAMPLEINTERVAL … #define ACP_SW_AUDIO0_TX_HCTRL_DP0 … #define ACP_SW_AUDIO0_TX_HCTRL_DP1 … #define ACP_SW_AUDIO0_TX_HCTRL_DP2 … #define ACP_SW_AUDIO0_TX_HCTRL_DP3 … #define ACP_SW_AUDIO0_TX_OFFSET_DP0 … #define ACP_SW_AUDIO0_TX_OFFSET_DP1 … #define ACP_SW_AUDIO0_TX_OFFSET_DP2 … #define ACP_SW_AUDIO0_TX_OFFSET_DP3 … #define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0 … #define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP1 … #define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP2 … #define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP3 … #define ACP_SW_AUDIO1_TX_EN … #define ACP_SW_AUDIO1_TX_EN_STATUS … #define ACP_SW_AUDIO1_TX_FRAME_FORMAT … #define ACP_SW_AUDIO1_TX_SAMPLEINTERVAL … #define ACP_SW_AUDIO1_TX_HCTRL … #define ACP_SW_AUDIO1_TX_OFFSET … #define ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0 … #define ACP_SW_AUDIO2_TX_EN … #define ACP_SW_AUDIO2_TX_EN_STATUS … #define ACP_SW_AUDIO2_TX_FRAME_FORMAT … #define ACP_SW_AUDIO2_TX_SAMPLEINTERVAL … #define ACP_SW_AUDIO2_TX_HCTRL … #define ACP_SW_AUDIO2_TX_OFFSET … #define ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0 … #define ACP_SW_AUDIO0_RX_EN … #define ACP_SW_AUDIO0_RX_EN_STATUS … #define ACP_SW_AUDIO0_RX_FRAME_FORMAT … #define ACP_SW_AUDIO0_RX_SAMPLEINTERVAL … #define ACP_SW_AUDIO0_RX_HCTRL_DP0 … #define ACP_SW_AUDIO0_RX_HCTRL_DP1 … #define ACP_SW_AUDIO0_RX_HCTRL_DP2 … #define ACP_SW_AUDIO0_RX_HCTRL_DP3 … #define ACP_SW_AUDIO0_RX_OFFSET_DP0 … #define ACP_SW_AUDIO0_RX_OFFSET_DP1 … #define ACP_SW_AUDIO0_RX_OFFSET_DP2 … #define ACP_SW_AUDIO0_RX_OFFSET_DP3 … #define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0 … #define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP1 … #define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP2 … #define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP3 … #define ACP_SW_AUDIO1_RX_EN … #define ACP_SW_AUDIO1_RX_EN_STATUS … #define ACP_SW_AUDIO1_RX_FRAME_FORMAT … #define ACP_SW_AUDIO1_RX_SAMPLEINTERVAL … #define ACP_SW_AUDIO1_RX_HCTRL … #define ACP_SW_AUDIO1_RX_OFFSET … #define ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0 … #define ACP_SW_AUDIO2_RX_EN … #define ACP_SW_AUDIO2_RX_EN_STATUS … #define ACP_SW_AUDIO2_RX_FRAME_FORMAT … #define ACP_SW_AUDIO2_RX_SAMPLEINTERVAL … #define ACP_SW_AUDIO2_RX_HCTRL … #define ACP_SW_AUDIO2_RX_OFFSET … #define ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0 … #define ACP_SW_BPT_PORT_EN … #define ACP_SW_BPT_PORT_EN_STATUS … #define ACP_SW_BPT_PORT_FRAME_FORMAT … #define ACP_SW_BPT_PORT_SAMPLEINTERVAL … #define ACP_SW_BPT_PORT_HCTRL … #define ACP_SW_BPT_PORT_OFFSET … #define ACP_SW_BPT_PORT_CHANNEL_ENABLE … #define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR … #define ACP_SW_CLK_RESUME_CTRL … #define ACP_SW_CLK_RESUME_DELAY_CNTR … #define ACP_SW_BUS_RESET_CTRL … #define ACP_SW_PRBS_ERR_STATUS … #define ACP_SW_IMM_CMD_UPPER_WORD … #define ACP_SW_IMM_CMD_LOWER_QWORD … #define ACP_SW_IMM_RESP_UPPER_WORD … #define ACP_SW_IMM_RESP_LOWER_QWORD … #define ACP_SW_IMM_CMD_STS … #define ACP_SW_BRA_BASE_ADDRESS … #define ACP_SW_BRA_TRANSFER_SIZE … #define ACP_SW_BRA_DMA_BUSY … #define ACP_SW_BRA_RESP … #define ACP_SW_BRA_RESP_FRAME_ADDR … #define ACP_SW_BRA_CURRENT_TRANSFER_SIZE … #define ACP_SW_STATE_CHANGE_STATUS_0TO7 … #define ACP_SW_STATE_CHANGE_STATUS_8TO11 … #define ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7 … #define ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11 … #define ACP_SW_CLK_FREQUENCY_CTRL … #define ACP_SW_ERROR_INTR_MASK … #define ACP_SW_PHY_TEST_MODE_DATA_OFF … #define ACP_DELAY_US … #define AMD_SDW_TIMEOUT … #define AMD_SDW_DEFAULT_CLK_FREQ … #define AMD_SDW_MCP_RESP_ACK … #define AMD_SDW_MCP_RESP_NACK … #define AMD_SDW_MCP_RESP_RDATA … #define AMD_SDW_MCP_CMD_SSP_TAG … #define AMD_SDW_MCP_CMD_COMMAND … #define AMD_SDW_MCP_CMD_DEV_ADDR … #define AMD_SDW_MCP_CMD_REG_ADDR_HIGH … #define AMD_SDW_MCP_CMD_REG_ADDR_LOW … #define AMD_SDW_MCP_CMD_REG_DATA … #define AMD_SDW_MCP_SLAVE_STAT_0_3 … #define AMD_SDW_MCP_SLAVE_STAT_4_11 … #define AMD_SDW_MCP_SLAVE_STATUS_MASK … #define AMD_SDW_MCP_SLAVE_STATUS_BITS … #define AMD_SDW_MCP_SLAVE_STATUS_8TO_11 … #define AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(x) … #define AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(x) … #define AMD_SDW_MASTER_SUSPEND_DELAY_MS … #define AMD_SDW_QUIRK_MASK_BUS_ENABLE … #define AMD_SDW_IMM_RES_VALID … #define AMD_SDW_IMM_CMD_BUSY … #define AMD_SDW_ENABLE … #define AMD_SDW_DISABLE … #define AMD_SDW_BUS_RESET_CLEAR_REQ … #define AMD_SDW_BUS_RESET_REQ … #define AMD_SDW_BUS_RESET_DONE … #define AMD_SDW_BUS_BASE_FREQ … #define AMD_SDW0_EXT_INTR_MASK … #define AMD_SDW1_EXT_INTR_MASK … #define AMD_SDW_IRQ_MASK_0TO7 … #define AMD_SDW_IRQ_MASK_8TO11 … #define AMD_SDW_IRQ_ERROR_MASK … #define AMD_SDW_MAX_FREQ_NUM … #define AMD_SDW0_MAX_TX_PORTS … #define AMD_SDW0_MAX_RX_PORTS … #define AMD_SDW1_MAX_TX_PORTS … #define AMD_SDW1_MAX_RX_PORTS … #define AMD_SDW0_MAX_DAI … #define AMD_SDW1_MAX_DAI … #define AMD_SDW_SLAVE_0_ATTACHED … #define AMD_SDW_SSP_COUNTER_VAL … #define AMD_DPN_FRAME_FMT_PFM … #define AMD_DPN_FRAME_FMT_PDM … #define AMD_DPN_FRAME_FMT_BLK_PKG_MODE … #define AMD_DPN_FRAME_FMT_BLK_GRP_CTRL … #define AMD_DPN_FRAME_FMT_WORD_LEN … #define AMD_DPN_FRAME_FMT_PCM_OR_PDM … #define AMD_DPN_HCTRL_HSTOP … #define AMD_DPN_HCTRL_HSTART … #define AMD_DPN_OFFSET_CTRL_1 … #define AMD_DPN_OFFSET_CTRL_2 … #define AMD_DPN_CH_EN_LCTRL … #define AMD_DPN_CH_EN_CHMASK … #define AMD_SDW_STAT_MAX_RETRY_COUNT … #define AMD_SDW0_PAD_PULLDOWN_CTRL_ENABLE_MASK … #define AMD_SDW1_PAD_PULLDOWN_CTRL_ENABLE_MASK … #define AMD_SDW0_PAD_PULLDOWN_CTRL_DISABLE_MASK … #define AMD_SDW1_PAD_PULLDOWN_CTRL_DISABLE_MASK … #define AMD_SDW0_PAD_KEEPER_EN_MASK … #define AMD_SDW1_PAD_KEEPER_EN_MASK … #define AMD_SDW0_PAD_KEEPER_DISABLE_MASK … #define AMD_SDW1_PAD_KEEPER_DISABLE_MASK … #define AMD_SDW_PREQ_INTR_STAT … #define AMD_SDW_CLK_STOP_DONE … #define AMD_SDW_CLK_RESUME_REQ … #define AMD_SDW_CLK_RESUME_DONE … #define AMD_SDW_WAKE_STAT_MASK … #define AMD_SDW_WAKE_INTR_MASK … static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = …; struct sdw_manager_dp_reg { … }; /* * SDW0 Manager instance registers 6 CPU DAI (3 TX & 3 RX Ports) * whereas SDW1 Manager Instance registers 2 CPU DAI (one TX & one RX port) * Below is the CPU DAI <->Manager port number mapping * i.e SDW0 Pin0 -> port number 0 -> AUDIO0 TX * SDW0 Pin1 -> Port number 1 -> AUDIO1 TX * SDW0 Pin2 -> Port number 2 -> AUDIO2 TX * SDW0 Pin3 -> port number 3 -> AUDIO0 RX * SDW0 Pin4 -> Port number 4 -> AUDIO1 RX * SDW0 Pin5 -> Port number 5 -> AUDIO2 RX * Whereas for SDW1 instance * SDW1 Pin0 -> port number 0 -> AUDIO1 TX * SDW1 Pin1 -> Port number 1 -> AUDIO1 RX * Same mapping should be used for programming DMA controller registers in SoundWire DMA driver. * i.e if AUDIO0 TX channel is selected then we need to use AUDIO0 TX registers for DMA programming * in SoundWire DMA driver. */ static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] = …; static struct sdw_manager_dp_reg sdw1_manager_dp_reg[AMD_SDW1_MAX_DAI] = …; static u32 sdw_manager_reg_mask_array[AMD_SDW_MAX_MANAGER_COUNT] = …; #endif
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