/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ /* Copyright(c) 2015-17 Intel Corporation. */ #ifndef __SDW_INTEL_H #define __SDW_INTEL_H #include <linux/irqreturn.h> #include <linux/soundwire/sdw.h> /********************************************************************* * cAVS and ACE1.x definitions *********************************************************************/ #define SDW_SHIM_BASE … #define SDW_ALH_BASE … #define SDW_SHIM_BASE_ACE … #define SDW_ALH_BASE_ACE … #define SDW_LINK_BASE … #define SDW_LINK_SIZE … /* Intel SHIM Registers Definition */ /* LCAP */ #define SDW_SHIM_LCAP … #define SDW_SHIM_LCAP_LCOUNT_MASK … #define SDW_SHIM_LCAP_MLCS_MASK … /* LCTL */ #define SDW_SHIM_LCTL … #define SDW_SHIM_LCTL_SPA … #define SDW_SHIM_LCTL_SPA_MASK … #define SDW_SHIM_LCTL_CPA … #define SDW_SHIM_LCTL_CPA_MASK … #define SDW_SHIM_LCTL_MLCS_MASK … #define SDW_SHIM_MLCS_XTAL_CLK … #define SDW_SHIM_MLCS_CARDINAL_CLK … #define SDW_SHIM_MLCS_AUDIO_PLL_CLK … /* SYNC */ #define SDW_SHIM_SYNC … #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 … #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 … #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 … #define SDW_SHIM_SYNC_SYNCPRD_VAL_96 … #define SDW_SHIM_SYNC_SYNCPRD … #define SDW_SHIM_SYNC_SYNCCPU … #define SDW_SHIM_SYNC_CMDSYNC_MASK … #define SDW_SHIM_SYNC_CMDSYNC … #define SDW_SHIM_SYNC_SYNCGO … /* Control stream capabililities and channel mask */ #define SDW_SHIM_CTLSCAP(x) … #define SDW_SHIM_CTLS0CM(x) … #define SDW_SHIM_CTLS1CM(x) … #define SDW_SHIM_CTLS2CM(x) … #define SDW_SHIM_CTLS3CM(x) … /* PCM Stream capabilities */ #define SDW_SHIM_PCMSCAP(x) … #define SDW_SHIM_PCMSCAP_ISS … #define SDW_SHIM_PCMSCAP_OSS … #define SDW_SHIM_PCMSCAP_BSS … /* PCM Stream Channel Map */ #define SDW_SHIM_PCMSYCHM(x, y) … /* PCM Stream Channel Count */ #define SDW_SHIM_PCMSYCHC(x, y) … #define SDW_SHIM_PCMSYCM_LCHN … #define SDW_SHIM_PCMSYCM_HCHN … #define SDW_SHIM_PCMSYCM_STREAM … #define SDW_SHIM_PCMSYCM_DIR … /* IO control */ #define SDW_SHIM_IOCTL(x) … #define SDW_SHIM_IOCTL_MIF … #define SDW_SHIM_IOCTL_CO … #define SDW_SHIM_IOCTL_COE … #define SDW_SHIM_IOCTL_DO … #define SDW_SHIM_IOCTL_DOE … #define SDW_SHIM_IOCTL_BKE … #define SDW_SHIM_IOCTL_WPDD … #define SDW_SHIM_IOCTL_CIBD … #define SDW_SHIM_IOCTL_DIBD … /* Wake Enable*/ #define SDW_SHIM_WAKEEN … #define SDW_SHIM_WAKEEN_ENABLE … /* Wake Status */ #define SDW_SHIM_WAKESTS … #define SDW_SHIM_WAKESTS_STATUS … /* AC Timing control */ #define SDW_SHIM_CTMCTL(x) … #define SDW_SHIM_CTMCTL_DACTQE … #define SDW_SHIM_CTMCTL_DODS … #define SDW_SHIM_CTMCTL_DOAIS … /* Intel ALH Register definitions */ #define SDW_ALH_STRMZCFG(x) … #define SDW_ALH_NUM_STREAMS … #define SDW_ALH_STRMZCFG_DMAT_VAL … #define SDW_ALH_STRMZCFG_DMAT … #define SDW_ALH_STRMZCFG_CHN … /********************************************************************* * ACE2.x definitions for SHIM registers - only accessible when the * HDAudio extended link LCTL.SPA/CPA = 1. *********************************************************************/ /* x variable is link index */ #define SDW_SHIM2_GENERIC_BASE(x) … #define SDW_IP_BASE(x) … #define SDW_SHIM2_VS_BASE(x) … /* SHIM2 Generic Registers */ /* Read-only capabilities */ #define SDW_SHIM2_LECAP … #define SDW_SHIM2_LECAP_HDS … #define SDW_SHIM2_LECAP_MLC … /* PCM Stream capabilities */ #define SDW_SHIM2_PCMSCAP … #define SDW_SHIM2_PCMSCAP_ISS … #define SDW_SHIM2_PCMSCAP_OSS … #define SDW_SHIM2_PCMSCAP_BSS … /* Read-only PCM Stream Channel Count, y variable is stream */ #define SDW_SHIM2_PCMSYCHC(y) … #define SDW_SHIM2_PCMSYCHC_CS … /* PCM Stream Channel Map */ #define SDW_SHIM2_PCMSYCHM(y) … #define SDW_SHIM2_PCMSYCHM_LCHAN … #define SDW_SHIM2_PCMSYCHM_HCHAN … #define SDW_SHIM2_PCMSYCHM_STRM … #define SDW_SHIM2_PCMSYCHM_DIR … /* SHIM2 vendor-specific registers */ #define SDW_SHIM2_INTEL_VS_LVSCTL … #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG … #define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS … #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD … #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD … #define SDW_SHIM2_MLCS_XTAL_CLK … #define SDW_SHIM2_MLCS_CARDINAL_CLK … #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK … #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK … #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK … #define SDW_SHIM2_INTEL_VS_WAKEEN … #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE … #define SDW_SHIM2_INTEL_VS_WAKESTS … #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS … #define SDW_SHIM2_INTEL_VS_IOCTL … #define SDW_SHIM2_INTEL_VS_IOCTL_MIF … #define SDW_SHIM2_INTEL_VS_IOCTL_CO … #define SDW_SHIM2_INTEL_VS_IOCTL_COE … #define SDW_SHIM2_INTEL_VS_IOCTL_DO … #define SDW_SHIM2_INTEL_VS_IOCTL_DOE … #define SDW_SHIM2_INTEL_VS_IOCTL_BKE … #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD … #define SDW_SHIM2_INTEL_VS_IOCTL_ODC … #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD … #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD … #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD … #define SDW_SHIM2_INTEL_VS_ACTMCTL … #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE … #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS … #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE … #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS … #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE … #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS … #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS … #define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 … #define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 … #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE … /** * struct sdw_intel_stream_params_data: configuration passed during * the @params_stream callback, e.g. for interaction with DSP * firmware. */ struct sdw_intel_stream_params_data { … }; /** * struct sdw_intel_stream_free_data: configuration passed during * the @free_stream callback, e.g. for interaction with DSP * firmware. */ struct sdw_intel_stream_free_data { … }; /** * struct sdw_intel_ops: Intel audio driver callback ops * */ struct sdw_intel_ops { … }; /** * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables * @handle: ACPI controller handle * @count: link count found with "sdw-master-count" or "sdw-manager-list" property * @link_mask: bit-wise mask listing links enabled by BIOS menu * * this structure could be expanded to e.g. provide all the _ADR * information in case the link_mask is not sufficient to identify * platform capabilities. */ struct sdw_intel_acpi_info { … }; struct sdw_intel_link_dev; /* Intel clock-stop/pm_runtime quirk definitions */ /* * Force the clock to remain on during pm_runtime suspend. This might * be needed if Slave devices do not have an alternate clock source or * if the latency requirements are very strict. */ #define SDW_INTEL_CLK_STOP_NOT_ALLOWED … /* * Stop the bus during pm_runtime suspend. If set, a complete bus * reset and re-enumeration will be performed when the bus * restarts. This mode shall not be used if Slave devices can generate * in-band wakes. */ #define SDW_INTEL_CLK_STOP_TEARDOWN … /* * Stop the bus during pm_suspend if Slaves are not wake capable * (e.g. speaker amplifiers). The clock-stop mode is typically * slightly higher power than when the IP is completely powered-off. */ #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY … /* * Require a bus reset (and complete re-enumeration) when exiting * clock stop modes. This may be needed if the controller power was * turned off and all context lost. This quirk shall not be used if a * Slave device needs to remain enumerated and keep its context, * e.g. to provide the reasons for the wake, report acoustic events or * pass a history buffer. */ #define SDW_INTEL_CLK_STOP_BUS_RESET … struct hdac_bus; /** * struct sdw_intel_ctx - context allocated by the controller * driver probe * @count: link count * @mmio_base: mmio base of SoundWire registers, only used to check * hardware capabilities after all power dependencies are settled. * @link_mask: bit-wise mask listing SoundWire links reported by the * Controller * @num_slaves: total number of devices exposed across all enabled links * @handle: ACPI parent handle * @ldev: information for each link (controller-specific and kept * opaque here) * @ids: array of slave_id, representing Slaves exposed across all enabled * links * @link_list: list to handle interrupts across all links * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers. * @shim_mask: flags to track initialization of SHIM shared registers * @shim_base: sdw shim base. * @alh_base: sdw alh base. */ struct sdw_intel_ctx { … }; /** * struct sdw_intel_res - Soundwire Intel global resource structure, * typically populated by the DSP driver * * @hw_ops: abstraction for platform ops * @count: link count * @mmio_base: mmio base of SoundWire registers * @irq: interrupt number * @handle: ACPI parent handle * @parent: parent device * @ops: callback ops * @dev: device implementing hwparams and free callbacks * @link_mask: bit-wise mask listing links selected by the DSP driver * This mask may be a subset of the one reported by the controller since * machine-specific quirks are handled in the DSP driver. * @clock_stop_quirks: mask array of possible behaviors requested by the * DSP driver. The quirks are common for all links for now. * @shim_base: sdw shim base. * @alh_base: sdw alh base. * @ext: extended HDaudio link support * @hbus: hdac_bus pointer, needed for power management * @eml_lock: mutex protecting shared registers in the HDaudio multi-link * space */ struct sdw_intel_res { … }; /* * On Intel platforms, the SoundWire IP has dependencies on power * rails shared with the DSP, and the initialization steps are split * in three. First an ACPI scan to check what the firmware describes * in DSDT tables, then an allocation step (with no hardware * configuration but with all the relevant devices created) and last * the actual hardware configuration. The final stage is a global * interrupt enable which is controlled by the DSP driver. Splitting * these phases helps simplify the boot flow and make early decisions * on e.g. which machine driver to select (I2S mode, HDaudio or * SoundWire). */ int sdw_intel_acpi_scan(acpi_handle *parent_handle, struct sdw_intel_acpi_info *info); void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx); struct sdw_intel_ctx * sdw_intel_probe(struct sdw_intel_res *res); int sdw_intel_startup(struct sdw_intel_ctx *ctx); void sdw_intel_exit(struct sdw_intel_ctx *ctx); irqreturn_t sdw_intel_thread(int irq, void *dev_id); #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE … struct sdw_intel; /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms. * @debugfs_init: initialize all debugfs capabilities * @debugfs_exit: close and cleanup debugfs capabilities * @get_link_count: fetch link count from hardware registers * @register_dai: read all PDI information and register DAIs * @check_clock_stop: throw error message if clock is not stopped. * @start_bus: normal start * @start_bus_after_reset: start after reset * @start_bus_after_clock_stop: start after mode0 clock stop * @stop_bus: stop all bus * @link_power_up: power-up using chip-specific helpers * @link_power_down: power-down with chip-specific helpers * @shim_check_wake: check if a wake was received * @shim_wake: enable/disable in-band wake management * @pre_bank_switch: helper for bus management * @post_bank_switch: helper for bus management * @sync_arm: helper for multi-link synchronization * @sync_go_unlocked: helper for multi-link synchronization - * shim_lock is assumed to be locked at higher level * @sync_go: helper for multi-link synchronization * @sync_check_cmdsync_unlocked: helper for multi-link synchronization * and bank switch - shim_lock is assumed to be locked at higher level * @program_sdi: helper for codec command/control based on dev_num */ struct sdw_intel_hw_ops { … }; extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops; extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops; /* * IDA min selected to allow for 5 unconstrained devices per link, * and 6 system-unique Device Numbers for wake-capable devices. */ #define SDW_INTEL_DEV_NUM_IDA_MIN … /* * Max number of links supported in hardware */ #define SDW_INTEL_MAX_LINKS … #endif
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