// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2019, Linaro Limited #include <linux/clk.h> #include <linux/completion.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/debugfs.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/pm_wakeirq.h> #include <linux/slimbus.h> #include <linux/soundwire/sdw.h> #include <linux/soundwire/sdw_registers.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include "bus.h" #define SWRM_COMP_SW_RESET … #define SWRM_COMP_STATUS … #define SWRM_LINK_MANAGER_EE … #define SWRM_EE_CPU … #define SWRM_FRM_GEN_ENABLED … #define SWRM_VERSION_1_3_0 … #define SWRM_VERSION_1_5_1 … #define SWRM_VERSION_1_7_0 … #define SWRM_VERSION_2_0_0 … #define SWRM_COMP_HW_VERSION … #define SWRM_COMP_CFG_ADDR … #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK … #define SWRM_COMP_CFG_ENABLE_MSK … #define SWRM_COMP_PARAMS … #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH … #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH … #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK … #define SWRM_COMP_PARAMS_DIN_PORTS_MASK … #define SWRM_COMP_MASTER_ID … #define SWRM_V1_3_INTERRUPT_STATUS … #define SWRM_V2_0_INTERRUPT_STATUS … #define SWRM_INTERRUPT_STATUS_RMSK … #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ … #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED … #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS … #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET … #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW … #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW … #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW … #define SWRM_INTERRUPT_STATUS_CMD_ERROR … #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION … #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH … #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED … #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED … #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL … #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 … #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 … #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP … #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED … #define SWRM_INTERRUPT_MAX … #define SWRM_V1_3_INTERRUPT_MASK_ADDR … #define SWRM_V1_3_INTERRUPT_CLEAR … #define SWRM_V2_0_INTERRUPT_CLEAR … #define SWRM_V1_3_INTERRUPT_CPU_EN … #define SWRM_V2_0_INTERRUPT_CPU_EN … #define SWRM_V1_3_CMD_FIFO_WR_CMD … #define SWRM_V2_0_CMD_FIFO_WR_CMD … #define SWRM_V1_3_CMD_FIFO_RD_CMD … #define SWRM_V2_0_CMD_FIFO_RD_CMD … #define SWRM_CMD_FIFO_CMD … #define SWRM_CMD_FIFO_FLUSH … #define SWRM_V1_3_CMD_FIFO_STATUS … #define SWRM_V2_0_CMD_FIFO_STATUS … #define SWRM_RD_CMD_FIFO_CNT_MASK … #define SWRM_WR_CMD_FIFO_CNT_MASK … #define SWRM_CMD_FIFO_CFG_ADDR … #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE … #define SWRM_RD_WR_CMD_RETRIES … #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR … #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR … #define SWRM_RD_FIFO_CMD_ID_MASK … #define SWRM_ENUMERATOR_CFG_ADDR … #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) … #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) … #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) … #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK … #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK … #define SWRM_MCP_BUS_CTRL … #define SWRM_MCP_BUS_CLK_START … #define SWRM_MCP_CFG_ADDR … #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK … #define SWRM_DEF_CMD_NO_PINGS … #define SWRM_MCP_STATUS … #define SWRM_MCP_STATUS_BANK_NUM_MASK … #define SWRM_MCP_SLV_STATUS … #define SWRM_MCP_SLV_STATUS_MASK … #define SWRM_MCP_SLV_STATUS_SZ … #define SWRM_DP_PORT_CTRL_BANK(n, m) … #define SWRM_DP_PORT_CTRL_2_BANK(n, m) … #define SWRM_DP_BLOCK_CTRL_1(n) … #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) … #define SWRM_DP_PORT_HCTRL_BANK(n, m) … #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) … #define SWRM_DP_SAMPLECTRL2_BANK(n, m) … #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) … #define SWR_V1_3_MSTR_MAX_REG_ADDR … #define SWR_V2_0_MSTR_MAX_REG_ADDR … #define SWRM_V2_0_CLK_CTRL … #define SWRM_V2_0_CLK_CTRL_CLK_START … #define SWRM_V2_0_LINK_STATUS … #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT … #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT … #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT … #define SWRM_AHB_BRIDGE_WR_DATA_0 … #define SWRM_AHB_BRIDGE_WR_ADDR_0 … #define SWRM_AHB_BRIDGE_RD_ADDR_0 … #define SWRM_AHB_BRIDGE_RD_DATA_0 … #define SWRM_REG_VAL_PACK(data, dev, id, reg) … #define MAX_FREQ_NUM … #define TIMEOUT_MS … #define QCOM_SWRM_MAX_RD_LEN … #define QCOM_SDW_MAX_PORTS … #define DEFAULT_CLK_FREQ … #define SWRM_MAX_DAIS … #define SWR_INVALID_PARAM … #define SWR_HSTOP_MAX_VAL … #define SWR_HSTART_MIN_VAL … #define SWR_BROADCAST_CMD_ID … #define SWR_MAX_CMD_ID … #define MAX_FIFO_RD_RETRY … #define SWR_OVERFLOW_RETRY_COUNT … #define SWRM_LINK_STATUS_RETRY_CNT … enum { … }; struct qcom_swrm_port_config { … }; /* * Internal IDs for different register layouts. Only few registers differ per * each variant, so the list of IDs below does not include all of registers. */ enum { … }; struct qcom_swrm_ctrl { … }; struct qcom_swrm_data { … }; static const unsigned int swrm_v1_3_reg_layout[] = …; static const struct qcom_swrm_data swrm_v1_3_data = …; static const struct qcom_swrm_data swrm_v1_5_data = …; static const struct qcom_swrm_data swrm_v1_6_data = …; static const unsigned int swrm_v2_0_reg_layout[] = …; static const struct qcom_swrm_data swrm_v2_0_data = …; #define to_qcom_sdw(b) … static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val) { … } static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, int val) { … } static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val) { … } static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, int val) { … } static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, u8 dev_addr, u16 reg_addr) { … } static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) { … } static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) { … } static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) { … } static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, u8 dev_addr, u16 reg_addr) { … } static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, u8 dev_addr, u16 reg_addr, u32 len, u8 *rval) { … } static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) { … } static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) { … } static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, struct sdw_slave *slave, int devnum) { … } static int qcom_swrm_enumerate(struct sdw_bus *bus) { … } static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) { … } static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) { … } static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) { … } static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) { … } static int qcom_swrm_read_prop(struct sdw_bus *bus) { … } static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) { … } static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) { … } static int qcom_swrm_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, unsigned int bank) { … } static int qcom_swrm_transport_params(struct sdw_bus *bus, struct sdw_transport_params *params, enum sdw_reg_bank bank) { … } static int qcom_swrm_port_enable(struct sdw_bus *bus, struct sdw_enable_ch *enable_ch, unsigned int bank) { … } static const struct sdw_master_port_ops qcom_swrm_port_ops = …; static const struct sdw_master_ops qcom_swrm_ops = …; static int qcom_swrm_compute_params(struct sdw_bus *bus) { … } static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = …; static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, struct sdw_stream_runtime *stream) { … } static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, struct sdw_stream_runtime *stream, struct snd_pcm_hw_params *params, int direction) { … } static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) { … } static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) { … } static int qcom_swrm_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = …; static const struct snd_soc_component_driver qcom_swrm_dai_component = …; static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) { … } static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) { … } #ifdef CONFIG_DEBUG_FS static int swrm_reg_show(struct seq_file *s_file, void *data) { … } DEFINE_SHOW_ATTRIBUTE(…); #endif static int qcom_swrm_probe(struct platform_device *pdev) { … } static void qcom_swrm_remove(struct platform_device *pdev) { … } static int __maybe_unused swrm_runtime_resume(struct device *dev) { … } static int __maybe_unused swrm_runtime_suspend(struct device *dev) { … } static const struct dev_pm_ops swrm_dev_pm_ops = …; static const struct of_device_id qcom_swrm_of_match[] = …; MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); static struct platform_driver qcom_swrm_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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