// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2022 Analog Devices, Inc. * Author: Cosmin Tanislav <[email protected]> */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> #include <linux/units.h> #include <asm/div64.h> #include <linux/unaligned.h> #include <linux/iio/buffer.h> #include <linux/iio/iio.h> #include <linux/iio/kfifo_buf.h> #include <linux/iio/sysfs.h> #define AD4130_NAME … #define AD4130_COMMS_READ_MASK … #define AD4130_STATUS_REG … #define AD4130_ADC_CONTROL_REG … #define AD4130_ADC_CONTROL_BIPOLAR_MASK … #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK … #define AD4130_INT_REF_2_5V … #define AD4130_INT_REF_1_25V … #define AD4130_ADC_CONTROL_CSB_EN_MASK … #define AD4130_ADC_CONTROL_INT_REF_EN_MASK … #define AD4130_ADC_CONTROL_MODE_MASK … #define AD4130_ADC_CONTROL_MCLK_SEL_MASK … #define AD4130_MCLK_FREQ_76_8KHZ … #define AD4130_MCLK_FREQ_153_6KHZ … #define AD4130_DATA_REG … #define AD4130_IO_CONTROL_REG … #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK … #define AD4130_IO_CONTROL_GPIO_DATA_MASK … #define AD4130_IO_CONTROL_GPIO_CTRL_MASK … #define AD4130_VBIAS_REG … #define AD4130_ID_REG … #define AD4130_ERROR_REG … #define AD4130_ERROR_EN_REG … #define AD4130_MCLK_COUNT_REG … #define AD4130_CHANNEL_X_REG(x) … #define AD4130_CHANNEL_EN_MASK … #define AD4130_CHANNEL_SETUP_MASK … #define AD4130_CHANNEL_AINP_MASK … #define AD4130_CHANNEL_AINM_MASK … #define AD4130_CHANNEL_IOUT1_MASK … #define AD4130_CHANNEL_IOUT2_MASK … #define AD4130_CONFIG_X_REG(x) … #define AD4130_CONFIG_IOUT1_VAL_MASK … #define AD4130_CONFIG_IOUT2_VAL_MASK … #define AD4130_CONFIG_BURNOUT_MASK … #define AD4130_CONFIG_REF_BUFP_MASK … #define AD4130_CONFIG_REF_BUFM_MASK … #define AD4130_CONFIG_REF_SEL_MASK … #define AD4130_CONFIG_PGA_MASK … #define AD4130_FILTER_X_REG(x) … #define AD4130_FILTER_MODE_MASK … #define AD4130_FILTER_SELECT_MASK … #define AD4130_FILTER_SELECT_MIN … #define AD4130_OFFSET_X_REG(x) … #define AD4130_GAIN_X_REG(x) … #define AD4130_MISC_REG … #define AD4130_FIFO_CONTROL_REG … #define AD4130_FIFO_CONTROL_HEADER_MASK … #define AD4130_FIFO_CONTROL_MODE_MASK … #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK … #define AD4130_FIFO_CONTROL_WM_MASK … #define AD4130_WATERMARK_256 … #define AD4130_FIFO_STATUS_REG … #define AD4130_FIFO_THRESHOLD_REG … #define AD4130_FIFO_DATA_REG … #define AD4130_FIFO_SIZE … #define AD4130_FIFO_MAX_SAMPLE_SIZE … #define AD4130_MAX_ANALOG_PINS … #define AD4130_MAX_CHANNELS … #define AD4130_MAX_DIFF_INPUTS … #define AD4130_MAX_GPIOS … #define AD4130_MAX_ODR … #define AD4130_MAX_PGA … #define AD4130_MAX_SETUPS … #define AD4130_AIN2_P1 … #define AD4130_AIN3_P2 … #define AD4130_RESET_BUF_SIZE … #define AD4130_RESET_SLEEP_US … #define AD4130_INVALID_SLOT … static const unsigned int ad4130_reg_size[] = …; enum ad4130_int_ref_val { … }; enum ad4130_mclk_sel { … }; enum ad4130_int_pin_sel { … }; enum ad4130_iout { … }; enum ad4130_burnout { … }; enum ad4130_ref_sel { … }; enum ad4130_fifo_mode { … }; enum ad4130_mode { … }; enum ad4130_filter_mode { … }; enum ad4130_pin_function { … }; struct ad4130_setup_info { … }; struct ad4130_slot_info { … }; struct ad4130_chan_info { … }; struct ad4130_filter_config { … }; struct ad4130_state { … }; static const char * const ad4130_int_pin_names[] = …; static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = …; static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = …; #define AD4130_VARIABLE_ODR_CONFIG(_filter_mode, _odr_div, _fs_max) … #define AD4130_FIXED_ODR_CONFIG(_filter_mode, _odr_div) … static const struct ad4130_filter_config ad4130_filter_configs[] = …; static const char * const ad4130_filter_modes_str[] = …; static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, unsigned int *size) { … } static unsigned int ad4130_data_reg_size(struct ad4130_state *st) { … } static unsigned int ad4130_resolution(struct ad4130_state *st) { … } static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val) { … } static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val) { … } static const struct regmap_config ad4130_regmap_config = …; static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc, unsigned long *valid_mask, unsigned int ngpios) { … } static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { … } static void ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) { … } static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode) { … } static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en) { … } static unsigned int ad4130_watermark_reg_val(unsigned int val) { … } static int ad4130_set_fifo_mode(struct ad4130_state *st, enum ad4130_fifo_mode mode) { … } static void ad4130_push_fifo_data(struct iio_dev *indio_dev) { … } static irqreturn_t ad4130_irq_handler(int irq, void *private) { … } static int ad4130_find_slot(struct ad4130_state *st, struct ad4130_setup_info *target_setup_info, unsigned int *slot, bool *overwrite) { … } static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel) { … } static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot) { … } static int ad4130_link_channel_slot(struct ad4130_state *st, unsigned int channel, unsigned int slot) { … } static int ad4130_write_slot_setup(struct ad4130_state *st, unsigned int slot, struct ad4130_setup_info *setup_info) { … } static int ad4130_write_channel_setup(struct ad4130_state *st, unsigned int channel, bool on_enable) { … } static int ad4130_set_channel_enable(struct ad4130_state *st, unsigned int channel, bool status) { … } /* * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes * the relation between filter mode, ODR and FS. * * Notice that the max ODR of each filter mode is not necessarily the * absolute max ODR supported by the chip. * * The ODR divider is not explicitly specified, but it can be deduced based * on the ODR range of each filter mode. * * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the * absolute max ODR is divided by 11 to achieve the max ODR of this filter * mode. * * The formulas for converting between ODR and FS for a specific filter * mode can be deduced from the same table. * * Notice that FS = 1 actually means max ODR, and that ODR decreases by * (maximum ODR / maximum FS) for each increment of FS. * * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=> * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div) * (used in ad4130_fs_to_freq) * * For the opposite formula, FS can be extracted from the last one. * * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=> * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=> * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR * (used in ad4130_fs_to_freq) */ static void ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode, int val, int val2, unsigned int *fs) { … } static void ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode, unsigned int fs, int *val, int *val2) { … } static int ad4130_set_filter_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, unsigned int val) { … } static int ad4130_get_filter_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { … } static const struct iio_enum ad4130_filter_mode_enum = …; static const struct iio_chan_spec_ext_info ad4130_filter_mode_ext_info[] = …; static const struct iio_chan_spec ad4130_channel_template = …; static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel, int val, int val2) { … } static int ad4130_set_channel_freq(struct ad4130_state *st, unsigned int channel, int val, int val2) { … } static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, int *val) { … } static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, int *val) { … } static int ad4130_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) { … } static int ad4130_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, const int **vals, int *type, int *length, long info) { … } static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long info) { … } static int ad4130_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) { … } static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { … } static int ad4130_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { … } static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val) { … } static const struct iio_info ad4130_info = …; static int ad4130_buffer_postenable(struct iio_dev *indio_dev) { … } static int ad4130_buffer_predisable(struct iio_dev *indio_dev) { … } static const struct iio_buffer_setup_ops ad4130_buffer_ops = …; static ssize_t hwfifo_watermark_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t hwfifo_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t hwfifo_watermark_min_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t hwfifo_watermark_max_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0); static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0); static const struct iio_dev_attr *ad4130_fifo_attributes[] = …; static int _ad4130_find_table_index(const unsigned int *tbl, size_t len, unsigned int val) { … } #define ad4130_find_table_index(table, val) … static int ad4130_get_ref_voltage(struct ad4130_state *st, enum ad4130_ref_sel ref_sel) { … } static int ad4130_parse_fw_setup(struct ad4130_state *st, struct fwnode_handle *child, struct ad4130_setup_info *setup_info) { … } static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) { … } static int ad4130_validate_diff_channels(struct ad4130_state *st, u32 *pins, unsigned int len) { … } static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin) { … } static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin) { … } static int ad4130_validate_vbias_pins(struct ad4130_state *st, u32 *pins, unsigned int len) { … } static int ad4130_parse_fw_channel(struct iio_dev *indio_dev, struct fwnode_handle *child) { … } static int ad4130_parse_fw_children(struct iio_dev *indio_dev) { … } static int ad4310_parse_fw(struct iio_dev *indio_dev) { … } static void ad4130_fill_scale_tbls(struct ad4130_state *st) { … } static void ad4130_clk_disable_unprepare(void *clk) { … } static int ad4130_set_mclk_sel(struct ad4130_state *st, enum ad4130_mclk_sel mclk_sel) { … } static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int ad4130_int_clk_is_enabled(struct clk_hw *hw) { … } static int ad4130_int_clk_prepare(struct clk_hw *hw) { … } static void ad4130_int_clk_unprepare(struct clk_hw *hw) { … } static const struct clk_ops ad4130_int_clk_ops = …; static int ad4130_setup_int_clk(struct ad4130_state *st) { … } static int ad4130_setup(struct iio_dev *indio_dev) { … } static int ad4130_soft_reset(struct ad4130_state *st) { … } static void ad4130_disable_regulators(void *data) { … } static int ad4130_probe(struct spi_device *spi) { … } static const struct of_device_id ad4130_of_match[] = …; MODULE_DEVICE_TABLE(of, ad4130_of_match); static struct spi_driver ad4130_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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