// SPDX-License-Identifier: GPL-2.0 /* * AD7192 and similar SPI ADC driver * * Copyright 2011-2015 Analog Devices Inc. */ #include <linux/interrupt.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/sysfs.h> #include <linux/spi/spi.h> #include <linux/regulator/consumer.h> #include <linux/err.h> #include <linux/sched.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/property.h> #include <linux/units.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> #include <linux/iio/buffer.h> #include <linux/iio/trigger.h> #include <linux/iio/trigger_consumer.h> #include <linux/iio/triggered_buffer.h> #include <linux/iio/adc/ad_sigma_delta.h> /* Registers */ #define AD7192_REG_COMM … #define AD7192_REG_STAT … #define AD7192_REG_MODE … #define AD7192_REG_CONF … #define AD7192_REG_DATA … #define AD7192_REG_ID … #define AD7192_REG_GPOCON … #define AD7192_REG_OFFSET … /* (AD7792)/24-bit (AD7192)) */ #define AD7192_REG_FULLSALE … /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ /* Communications Register Bit Designations (AD7192_REG_COMM) */ #define AD7192_COMM_WEN … #define AD7192_COMM_WRITE … #define AD7192_COMM_READ … #define AD7192_COMM_ADDR_MASK … #define AD7192_COMM_CREAD … /* Status Register Bit Designations (AD7192_REG_STAT) */ #define AD7192_STAT_RDY … #define AD7192_STAT_ERR … #define AD7192_STAT_NOREF … #define AD7192_STAT_PARITY … #define AD7192_STAT_CH3 … #define AD7192_STAT_CH2 … #define AD7192_STAT_CH1 … /* Mode Register Bit Designations (AD7192_REG_MODE) */ #define AD7192_MODE_SEL_MASK … #define AD7192_MODE_STA_MASK … #define AD7192_MODE_CLKSRC_MASK … #define AD7192_MODE_AVG_MASK … /* Fast Settling Filter Average Select Mask (AD7193 only) */ #define AD7192_MODE_SINC3 … #define AD7192_MODE_ENPAR … #define AD7192_MODE_CLKDIV … #define AD7192_MODE_SCYCLE … #define AD7192_MODE_REJ60 … /* Filter Update Rate Select Mask */ #define AD7192_MODE_RATE_MASK … /* Mode Register: AD7192_MODE_SEL options */ #define AD7192_MODE_CONT … #define AD7192_MODE_SINGLE … #define AD7192_MODE_IDLE … #define AD7192_MODE_PWRDN … #define AD7192_MODE_CAL_INT_ZERO … #define AD7192_MODE_CAL_INT_FULL … #define AD7192_MODE_CAL_SYS_ZERO … #define AD7192_MODE_CAL_SYS_FULL … /* Mode Register: AD7192_MODE_CLKSRC options */ #define AD7192_CLK_EXT_MCLK1_2 … /* from MCLK1 to MCLK2 */ #define AD7192_CLK_EXT_MCLK2 … #define AD7192_CLK_INT … /* available at the MCLK2 pin */ #define AD7192_CLK_INT_CO … /* at the MCLK2 pin */ /* Configuration Register Bit Designations (AD7192_REG_CONF) */ #define AD7192_CONF_CHOP … #define AD7192_CONF_ACX … #define AD7192_CONF_REFSEL … #define AD7192_CONF_CHAN_MASK … #define AD7192_CONF_BURN … #define AD7192_CONF_REFDET … #define AD7192_CONF_BUF … #define AD7192_CONF_UNIPOLAR … #define AD7192_CONF_GAIN_MASK … #define AD7192_CH_AIN1P_AIN2M … #define AD7192_CH_AIN3P_AIN4M … #define AD7192_CH_TEMP … #define AD7192_CH_AIN2P_AIN2M … #define AD7192_CH_AIN1 … #define AD7192_CH_AIN2 … #define AD7192_CH_AIN3 … #define AD7192_CH_AIN4 … #define AD7193_CH_AIN1P_AIN2M … #define AD7193_CH_AIN3P_AIN4M … #define AD7193_CH_AIN5P_AIN6M … #define AD7193_CH_AIN7P_AIN8M … #define AD7193_CH_TEMP … #define AD7193_CH_AIN2P_AIN2M … #define AD7193_CH_AIN1 … #define AD7193_CH_AIN2 … #define AD7193_CH_AIN3 … #define AD7193_CH_AIN4 … #define AD7193_CH_AIN5 … #define AD7193_CH_AIN6 … #define AD7193_CH_AIN7 … #define AD7193_CH_AIN8 … #define AD7193_CH_AINCOM … #define AD7194_CH_POS(x) … #define AD7194_CH_NEG(x) … /* 10th bit corresponds to CON18(Pseudo) */ #define AD7194_CH(p) … #define AD7194_DIFF_CH(p, n) … #define AD7194_CH_TEMP … #define AD7194_CH_BASE_NR … #define AD7194_CH_AIN_START … #define AD7194_CH_AIN_NR … #define AD7194_CH_MAX_NR … /* ID Register Bit Designations (AD7192_REG_ID) */ #define CHIPID_AD7190 … #define CHIPID_AD7192 … #define CHIPID_AD7193 … #define CHIPID_AD7194 … #define CHIPID_AD7195 … #define AD7192_ID_MASK … /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ #define AD7192_GPOCON_BPDSW … #define AD7192_GPOCON_GP32EN … #define AD7192_GPOCON_GP10EN … #define AD7192_GPOCON_P3DAT … #define AD7192_GPOCON_P2DAT … #define AD7192_GPOCON_P1DAT … #define AD7192_GPOCON_P0DAT … #define AD7192_EXT_FREQ_MHZ_MIN … #define AD7192_EXT_FREQ_MHZ_MAX … #define AD7192_INT_FREQ_MHZ … #define AD7192_NO_SYNC_FILTER … #define AD7192_SYNC3_FILTER … #define AD7192_SYNC4_FILTER … /* NOTE: * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. * In order to avoid contentions on the SPI bus, it's therefore necessary * to use spi bus locking. * * The DOUT/RDY output must also be wired to an interrupt capable GPIO. */ enum { … }; enum { … }; struct ad7192_chip_info { … }; struct ad7192_state { … }; static const char * const ad7192_syscalib_modes[] = …; static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, unsigned int mode) { … } static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { … } static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, const char *buf, size_t len) { … } static const struct iio_enum ad7192_syscalib_mode_enum = …; static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = …; static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) { … } static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) { … } static int ad7192_set_mode(struct ad_sigma_delta *sd, enum ad_sigma_delta_mode mode) { … } static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) { … } static int ad7192_disable_all(struct ad_sigma_delta *sd) { … } static const struct ad_sigma_delta_info ad7192_sigma_delta_info = …; static const struct ad_sigma_delta_info ad7194_sigma_delta_info = …; static const struct ad_sd_calib_data ad7192_calib_arr[8] = …; static int ad7192_calibrate_all(struct ad7192_state *st) { … } static inline bool ad7192_valid_external_frequency(u32 freq) { … } /* * Position 0 of ad7192_clock_names, xtal, corresponds to clock source * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to * AD7192_CLK_EXT_MCLK2 */ static const char *const ad7192_clock_names[] = …; static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) { … } static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int ad7192_clk_output_is_enabled(struct clk_hw *hw) { … } static int ad7192_clk_prepare(struct clk_hw *hw) { … } static void ad7192_clk_unprepare(struct clk_hw *hw) { … } static const struct clk_ops ad7192_int_clk_ops = …; static int ad7192_register_clk_provider(struct ad7192_state *st) { … } static int ad7192_clock_setup(struct ad7192_state *st) { … } static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) { … } static ssize_t ad7192_show_ac_excitation(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t ad7192_show_bridge_switch(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t ad7192_set(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { … } static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) { … } static int ad7192_get_f_order(struct ad7192_state *st) { … } static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, bool chop_en) { … } static int ad7192_get_f_adc(struct ad7192_state *st) { … } static void ad7192_update_filter_freq_avail(struct ad7192_state *st) { … } static IIO_DEVICE_ATTR(bridge_switch_en, 0644, ad7192_show_bridge_switch, ad7192_set, AD7192_REG_GPOCON); static IIO_DEVICE_ATTR(ac_excitation_en, 0644, ad7192_show_ac_excitation, ad7192_set, AD7192_REG_CONF); static struct attribute *ad7192_attributes[] = …; static const struct attribute_group ad7192_attribute_group = …; static struct attribute *ad7195_attributes[] = …; static const struct attribute_group ad7195_attribute_group = …; static unsigned int ad7192_get_temp_scale(bool unipolar) { … } static int ad7192_set_3db_filter_freq(struct ad7192_state *st, int val, int val2) { … } static int ad7192_get_3db_filter_freq(struct ad7192_state *st) { … } static int ad7192_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long m) { … } static int ad7192_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { … } static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long mask) { … } static int ad7192_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, const int **vals, int *type, int *length, long mask) { … } static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { … } static const struct iio_info ad7192_info = …; static const struct iio_info ad7194_info = …; static const struct iio_info ad7195_info = …; #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \ _mask_all, _mask_type_av, _mask_all_av, _ext_info) … #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) … #define AD719x_CHANNEL(_si, _channel1, _address) … #define AD719x_TEMP_CHANNEL(_si, _address) … #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) … #define AD7193_CHANNEL(_si, _channel1, _address) … static const struct iio_chan_spec ad7192_channels[] = …; static const struct iio_chan_spec ad7193_channels[] = …; static bool ad7194_validate_ain_channel(struct device *dev, u32 ain) { … } static int ad7194_parse_channels(struct iio_dev *indio_dev) { … } static const struct ad7192_chip_info ad7192_chip_info_tbl[] = …; static int ad7192_probe(struct spi_device *spi) { … } static const struct of_device_id ad7192_of_match[] = …; MODULE_DEVICE_TABLE(of, ad7192_of_match); static const struct spi_device_id ad7192_ids[] = …; MODULE_DEVICE_TABLE(spi, ad7192_ids); static struct spi_driver ad7192_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_IMPORT_NS(…);
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