// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. * Copyright (c) 2022 Linaro Limited. * Author: Caleb Connolly <[email protected]> * * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. */ #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/math64.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/spmi.h> #include <linux/types.h> #include <linux/units.h> #include <linux/unaligned.h> #include <linux/iio/iio.h> #include <linux/iio/types.h> #include <soc/qcom/qcom-spmi-pmic.h> #define DRIVER_NAME … #define RR_ADC_EN_CTL … #define RR_ADC_SKIN_TEMP_LSB … #define RR_ADC_SKIN_TEMP_MSB … #define RR_ADC_CTL … #define RR_ADC_CTL_CONTINUOUS_SEL … #define RR_ADC_LOG … #define RR_ADC_LOG_CLR_CTRL … #define RR_ADC_FAKE_BATT_LOW_LSB … #define RR_ADC_FAKE_BATT_LOW_MSB … #define RR_ADC_FAKE_BATT_HIGH_LSB … #define RR_ADC_FAKE_BATT_HIGH_MSB … #define RR_ADC_BATT_ID_CTRL … #define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV … #define RR_ADC_BATT_ID_TRIGGER … #define RR_ADC_BATT_ID_STS … #define RR_ADC_BATT_ID_CFG … #define BATT_ID_SETTLE_MASK … #define RR_ADC_BATT_ID_5_LSB … #define RR_ADC_BATT_ID_5_MSB … #define RR_ADC_BATT_ID_15_LSB … #define RR_ADC_BATT_ID_15_MSB … #define RR_ADC_BATT_ID_150_LSB … #define RR_ADC_BATT_ID_150_MSB … #define RR_ADC_BATT_THERM_CTRL … #define RR_ADC_BATT_THERM_TRIGGER … #define RR_ADC_BATT_THERM_STS … #define RR_ADC_BATT_THERM_CFG … #define RR_ADC_BATT_THERM_LSB … #define RR_ADC_BATT_THERM_MSB … #define RR_ADC_BATT_THERM_FREQ … #define RR_ADC_AUX_THERM_CTRL … #define RR_ADC_AUX_THERM_TRIGGER … #define RR_ADC_AUX_THERM_STS … #define RR_ADC_AUX_THERM_CFG … #define RR_ADC_AUX_THERM_LSB … #define RR_ADC_AUX_THERM_MSB … #define RR_ADC_SKIN_HOT … #define RR_ADC_SKIN_TOO_HOT … #define RR_ADC_AUX_THERM_C1 … #define RR_ADC_AUX_THERM_C2 … #define RR_ADC_AUX_THERM_C3 … #define RR_ADC_AUX_THERM_HALF_RANGE … #define RR_ADC_USB_IN_V_CTRL … #define RR_ADC_USB_IN_V_TRIGGER … #define RR_ADC_USB_IN_V_STS … #define RR_ADC_USB_IN_V_LSB … #define RR_ADC_USB_IN_V_MSB … #define RR_ADC_USB_IN_I_CTRL … #define RR_ADC_USB_IN_I_TRIGGER … #define RR_ADC_USB_IN_I_STS … #define RR_ADC_USB_IN_I_LSB … #define RR_ADC_USB_IN_I_MSB … #define RR_ADC_DC_IN_V_CTRL … #define RR_ADC_DC_IN_V_TRIGGER … #define RR_ADC_DC_IN_V_STS … #define RR_ADC_DC_IN_V_LSB … #define RR_ADC_DC_IN_V_MSB … #define RR_ADC_DC_IN_I_CTRL … #define RR_ADC_DC_IN_I_TRIGGER … #define RR_ADC_DC_IN_I_STS … #define RR_ADC_DC_IN_I_LSB … #define RR_ADC_DC_IN_I_MSB … #define RR_ADC_PMI_DIE_TEMP_CTRL … #define RR_ADC_PMI_DIE_TEMP_TRIGGER … #define RR_ADC_PMI_DIE_TEMP_STS … #define RR_ADC_PMI_DIE_TEMP_CFG … #define RR_ADC_PMI_DIE_TEMP_LSB … #define RR_ADC_PMI_DIE_TEMP_MSB … #define RR_ADC_CHARGER_TEMP_CTRL … #define RR_ADC_CHARGER_TEMP_TRIGGER … #define RR_ADC_CHARGER_TEMP_STS … #define RR_ADC_CHARGER_TEMP_CFG … #define RR_ADC_CHARGER_TEMP_LSB … #define RR_ADC_CHARGER_TEMP_MSB … #define RR_ADC_CHARGER_HOT … #define RR_ADC_CHARGER_TOO_HOT … #define RR_ADC_GPIO_CTRL … #define RR_ADC_GPIO_TRIGGER … #define RR_ADC_GPIO_STS … #define RR_ADC_GPIO_LSB … #define RR_ADC_GPIO_MSB … #define RR_ADC_ATEST_CTRL … #define RR_ADC_ATEST_TRIGGER … #define RR_ADC_ATEST_STS … #define RR_ADC_ATEST_LSB … #define RR_ADC_ATEST_MSB … #define RR_ADC_SEC_ACCESS … #define RR_ADC_PERPH_RESET_CTL2 … #define RR_ADC_PERPH_RESET_CTL3 … #define RR_ADC_PERPH_RESET_CTL4 … #define RR_ADC_INT_TEST1 … #define RR_ADC_INT_TEST_VAL … #define RR_ADC_TM_TRIGGER_CTRLS … #define RR_ADC_TM_ADC_CTRLS … #define RR_ADC_TM_CNL_CTRL … #define RR_ADC_TM_BATT_ID_CTRL … #define RR_ADC_TM_THERM_CTRL … #define RR_ADC_TM_CONV_STS … #define RR_ADC_TM_ADC_READ_LSB … #define RR_ADC_TM_ADC_READ_MSB … #define RR_ADC_TM_ATEST_MUX_1 … #define RR_ADC_TM_ATEST_MUX_2 … #define RR_ADC_TM_REFERENCES … #define RR_ADC_TM_MISC_CTL … #define RR_ADC_TM_RR_CTRL … #define RR_ADC_TRIGGER_EVERY_CYCLE … #define RR_ADC_TRIGGER_CTL … #define RR_ADC_BATT_ID_RANGE … #define RR_ADC_BITS … #define RR_ADC_CHAN_MSB … #define RR_ADC_FS_VOLTAGE_MV … /* BATT_THERM 0.25K/LSB */ #define RR_ADC_BATT_THERM_LSB_K … #define RR_ADC_TEMP_FS_VOLTAGE_NUM … #define RR_ADC_TEMP_FS_VOLTAGE_DEN … #define RR_ADC_DIE_TEMP_OFFSET … #define RR_ADC_DIE_TEMP_SLOPE … #define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC … #define RR_ADC_CHG_TEMP_GF_OFFSET_UV … #define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C … #define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV … #define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C … #define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV … #define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C … #define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV … #define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C … #define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV … #define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C … #define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC … #define RR_ADC_CHG_THRESHOLD_SCALE … #define RR_ADC_VOLT_INPUT_FACTOR … #define RR_ADC_CURR_INPUT_FACTOR … #define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL … #define RR_ADC_CURR_USBIN_660_FACTOR_MIL … #define RR_ADC_CURR_USBIN_660_UV_VAL … #define RR_ADC_GPIO_FS_RANGE … #define RR_ADC_COHERENT_CHECK_RETRY … #define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN … #define RR_ADC_STS_CHANNEL_READING_MASK … #define RR_ADC_STS_CHANNEL_STS … #define RR_ADC_TP_REV_VERSION1 … #define RR_ADC_TP_REV_VERSION2 … #define RR_ADC_TP_REV_VERSION3 … #define RRADC_BATT_ID_DELAY_MAX … enum rradc_channel_id { … }; struct rradc_chip; /** * struct rradc_channel - rradc channel data * @label: channel label * @lsb: Channel least significant byte * @status: Channel status address * @size: number of bytes to read * @trigger_addr: Trigger address, trigger is only used on some channels * @trigger_mask: Trigger mask * @scale_fn: Post process callback for channels which can't be exposed * as offset + scale. */ struct rradc_channel { … }; struct rradc_chip { … }; static const int batt_id_delays[] = …; static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len) { … } static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, int64_t *slope) { … } /* * These functions explicitly cast int64_t to int. * They will never overflow, as the values are small enough. */ static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, int *result_ohms) { … } static int rradc_enable_continuous_mode(struct rradc_chip *chip) { … } static int rradc_disable_continuous_mode(struct rradc_chip *chip) { … } static bool rradc_is_ready(struct rradc_chip *chip, enum rradc_channel_id chan_address) { … } static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, enum rradc_channel_id chan_address) { … } static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, enum rradc_channel_id chan_address, u16 *data) { … } static int rradc_do_conversion(struct rradc_chip *chip, enum rradc_channel_id chan_address, u16 *data) { … } static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val, int *val2) { … } static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val) { … } static int rradc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan_spec, int *val, int *val2, long mask) { … } static int rradc_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) { … } static const struct iio_info rradc_info = …; static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = …; static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = …; static int rradc_probe(struct platform_device *pdev) { … } static const struct of_device_id rradc_match_table[] = …; MODULE_DEVICE_TABLE(of, rradc_match_table); static struct platform_driver rradc_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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