/* SPDX-License-Identifier: GPL-2.0 */ /* * This file is part of STM32 DFSDM driver * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved * Author(s): Arnaud Pouliquen <[email protected]>. */ #ifndef MDF_STM32_DFSDM__H #define MDF_STM32_DFSDM__H #include <linux/bitfield.h> /* * STM32 DFSDM - global register map * __________________________________________________________ * | Offset | Registers block | * ---------------------------------------------------------- * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS | * ---------------------------------------------------------- * | 0x020 | CHANNEL 1 | * ---------------------------------------------------------- * | ... | ..... | * ---------------------------------------------------------- * | 0x20 x n | CHANNEL n | * ---------------------------------------------------------- * | 0x100 | FILTER 0 + COMMON FILTER FIELDs | * ---------------------------------------------------------- * | 0x200 | FILTER 1 | * ---------------------------------------------------------- * | | ..... | * ---------------------------------------------------------- * | 0x100 x m | FILTER m | * ---------------------------------------------------------- * | | ..... | * ---------------------------------------------------------- * | 0x7F0-7FC | Identification registers | * ---------------------------------------------------------- */ /* * Channels register definitions */ #define DFSDM_CHCFGR1(y) … #define DFSDM_CHCFGR2(y) … #define DFSDM_AWSCDR(y) … #define DFSDM_CHWDATR(y) … #define DFSDM_CHDATINR(y) … /* CHCFGR1: Channel configuration register 1 */ #define DFSDM_CHCFGR1_SITP_MASK … #define DFSDM_CHCFGR1_SITP(v) … #define DFSDM_CHCFGR1_SPICKSEL_MASK … #define DFSDM_CHCFGR1_SPICKSEL(v) … #define DFSDM_CHCFGR1_SCDEN_MASK … #define DFSDM_CHCFGR1_SCDEN(v) … #define DFSDM_CHCFGR1_CKABEN_MASK … #define DFSDM_CHCFGR1_CKABEN(v) … #define DFSDM_CHCFGR1_CHEN_MASK … #define DFSDM_CHCFGR1_CHEN(v) … #define DFSDM_CHCFGR1_CHINSEL_MASK … #define DFSDM_CHCFGR1_CHINSEL(v) … #define DFSDM_CHCFGR1_DATMPX_MASK … #define DFSDM_CHCFGR1_DATMPX(v) … #define DFSDM_CHCFGR1_DATPACK_MASK … #define DFSDM_CHCFGR1_DATPACK(v) … #define DFSDM_CHCFGR1_CKOUTDIV_MASK … #define DFSDM_CHCFGR1_CKOUTDIV(v) … #define DFSDM_CHCFGR1_CKOUTSRC_MASK … #define DFSDM_CHCFGR1_CKOUTSRC(v) … #define DFSDM_CHCFGR1_DFSDMEN_MASK … #define DFSDM_CHCFGR1_DFSDMEN(v) … /* CHCFGR2: Channel configuration register 2 */ #define DFSDM_CHCFGR2_DTRBS_MASK … #define DFSDM_CHCFGR2_DTRBS(v) … #define DFSDM_CHCFGR2_OFFSET_MASK … #define DFSDM_CHCFGR2_OFFSET(v) … /* AWSCDR: Channel analog watchdog and short circuit detector */ #define DFSDM_AWSCDR_SCDT_MASK … #define DFSDM_AWSCDR_SCDT(v) … #define DFSDM_AWSCDR_BKSCD_MASK … #define DFSDM_AWSCDR_BKSCD(v) … #define DFSDM_AWSCDR_AWFOSR_MASK … #define DFSDM_AWSCDR_AWFOSR(v) … #define DFSDM_AWSCDR_AWFORD_MASK … #define DFSDM_AWSCDR_AWFORD(v) … /* * Filters register definitions */ #define DFSDM_FILTER_BASE_ADR … #define DFSDM_FILTER_REG_MASK … #define DFSDM_FILTER_X_BASE_ADR(x) … #define DFSDM_CR1(x) … #define DFSDM_CR2(x) … #define DFSDM_ISR(x) … #define DFSDM_ICR(x) … #define DFSDM_JCHGR(x) … #define DFSDM_FCR(x) … #define DFSDM_JDATAR(x) … #define DFSDM_RDATAR(x) … #define DFSDM_AWHTR(x) … #define DFSDM_AWLTR(x) … #define DFSDM_AWSR(x) … #define DFSDM_AWCFR(x) … #define DFSDM_EXMAX(x) … #define DFSDM_EXMIN(x) … #define DFSDM_CNVTIMR(x) … /* CR1 Control register 1 */ #define DFSDM_CR1_DFEN_MASK … #define DFSDM_CR1_DFEN(v) … #define DFSDM_CR1_JSWSTART_MASK … #define DFSDM_CR1_JSWSTART(v) … #define DFSDM_CR1_JSYNC_MASK … #define DFSDM_CR1_JSYNC(v) … #define DFSDM_CR1_JSCAN_MASK … #define DFSDM_CR1_JSCAN(v) … #define DFSDM_CR1_JDMAEN_MASK … #define DFSDM_CR1_JDMAEN(v) … #define DFSDM_CR1_JEXTSEL_MASK … #define DFSDM_CR1_JEXTSEL(v) … #define DFSDM_CR1_JEXTEN_MASK … #define DFSDM_CR1_JEXTEN(v) … #define DFSDM_CR1_RSWSTART_MASK … #define DFSDM_CR1_RSWSTART(v) … #define DFSDM_CR1_RCONT_MASK … #define DFSDM_CR1_RCONT(v) … #define DFSDM_CR1_RSYNC_MASK … #define DFSDM_CR1_RSYNC(v) … #define DFSDM_CR1_RDMAEN_MASK … #define DFSDM_CR1_RDMAEN(v) … #define DFSDM_CR1_RCH_MASK … #define DFSDM_CR1_RCH(v) … #define DFSDM_CR1_FAST_MASK … #define DFSDM_CR1_FAST(v) … #define DFSDM_CR1_AWFSEL_MASK … #define DFSDM_CR1_AWFSEL(v) … /* CR2: Control register 2 */ #define DFSDM_CR2_IE_MASK … #define DFSDM_CR2_IE(v) … #define DFSDM_CR2_JEOCIE_MASK … #define DFSDM_CR2_JEOCIE(v) … #define DFSDM_CR2_REOCIE_MASK … #define DFSDM_CR2_REOCIE(v) … #define DFSDM_CR2_JOVRIE_MASK … #define DFSDM_CR2_JOVRIE(v) … #define DFSDM_CR2_ROVRIE_MASK … #define DFSDM_CR2_ROVRIE(v) … #define DFSDM_CR2_AWDIE_MASK … #define DFSDM_CR2_AWDIE(v) … #define DFSDM_CR2_SCDIE_MASK … #define DFSDM_CR2_SCDIE(v) … #define DFSDM_CR2_CKABIE_MASK … #define DFSDM_CR2_CKABIE(v) … #define DFSDM_CR2_EXCH_MASK … #define DFSDM_CR2_EXCH(v) … #define DFSDM_CR2_AWDCH_MASK … #define DFSDM_CR2_AWDCH(v) … /* ISR: Interrupt status register */ #define DFSDM_ISR_JEOCF_MASK … #define DFSDM_ISR_JEOCF(v) … #define DFSDM_ISR_REOCF_MASK … #define DFSDM_ISR_REOCF(v) … #define DFSDM_ISR_JOVRF_MASK … #define DFSDM_ISR_JOVRF(v) … #define DFSDM_ISR_ROVRF_MASK … #define DFSDM_ISR_ROVRF(v) … #define DFSDM_ISR_AWDF_MASK … #define DFSDM_ISR_AWDF(v) … #define DFSDM_ISR_JCIP_MASK … #define DFSDM_ISR_JCIP(v) … #define DFSDM_ISR_RCIP_MASK … #define DFSDM_ISR_RCIP(v) … #define DFSDM_ISR_CKABF_MASK … #define DFSDM_ISR_CKABF(v) … #define DFSDM_ISR_SCDF_MASK … #define DFSDM_ISR_SCDF(v) … /* ICR: Interrupt flag clear register */ #define DFSDM_ICR_CLRJOVRF_MASK … #define DFSDM_ICR_CLRJOVRF(v) … #define DFSDM_ICR_CLRROVRF_MASK … #define DFSDM_ICR_CLRROVRF(v) … #define DFSDM_ICR_CLRCKABF_MASK … #define DFSDM_ICR_CLRCKABF(v) … #define DFSDM_ICR_CLRCKABF_CH_MASK(y) … #define DFSDM_ICR_CLRCKABF_CH(v, y) … #define DFSDM_ICR_CLRSCDF_MASK … #define DFSDM_ICR_CLRSCDF(v) … #define DFSDM_ICR_CLRSCDF_CH_MASK(y) … #define DFSDM_ICR_CLRSCDF_CH(v, y) … /* FCR: Filter control register */ #define DFSDM_FCR_IOSR_MASK … #define DFSDM_FCR_IOSR(v) … #define DFSDM_FCR_FOSR_MASK … #define DFSDM_FCR_FOSR(v) … #define DFSDM_FCR_FORD_MASK … #define DFSDM_FCR_FORD(v) … /* RDATAR: Filter data register for regular channel */ #define DFSDM_DATAR_CH_MASK … #define DFSDM_DATAR_DATA_OFFSET … #define DFSDM_DATAR_DATA_MASK … /* AWLTR: Filter analog watchdog low threshold register */ #define DFSDM_AWLTR_BKAWL_MASK … #define DFSDM_AWLTR_BKAWL(v) … #define DFSDM_AWLTR_AWLT_MASK … #define DFSDM_AWLTR_AWLT(v) … /* AWHTR: Filter analog watchdog low threshold register */ #define DFSDM_AWHTR_BKAWH_MASK … #define DFSDM_AWHTR_BKAWH(v) … #define DFSDM_AWHTR_AWHT_MASK … #define DFSDM_AWHTR_AWHT(v) … /* AWSR: Filter watchdog status register */ #define DFSDM_AWSR_AWLTF_MASK … #define DFSDM_AWSR_AWLTF(v) … #define DFSDM_AWSR_AWHTF_MASK … #define DFSDM_AWSR_AWHTF(v) … /* AWCFR: Filter watchdog status register */ #define DFSDM_AWCFR_AWLTF_MASK … #define DFSDM_AWCFR_AWLTF(v) … #define DFSDM_AWCFR_AWHTF_MASK … #define DFSDM_AWCFR_AWHTF(v) … /* * Identification register definitions */ #define DFSDM_HWCFGR … #define DFSDM_VERR … #define DFSDM_IPIDR … #define DFSDM_SIDR … /* HWCFGR: Hardware configuration register */ #define DFSDM_HWCFGR_NBT_MASK … #define DFSDM_HWCFGR_NBF_MASK … /* VERR: Version register */ #define DFSDM_VERR_MINREV_MASK … #define DFSDM_VERR_MAJREV_MASK … #define STM32MP15_IPIDR_NUMBER … /* DFSDM filter order */ enum stm32_dfsdm_sinc_order { … }; /** * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling * @iosr: integrator oversampling * @fosr: filter oversampling * @rshift: output sample right shift (hardware shift) * @lshift: output sample left shift (software shift) * @res: output sample resolution * @bits: output sample resolution in bits * @max: output sample maximum positive value */ struct stm32_dfsdm_filter_osr { … }; /** * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter * @ford: filter order * @flo: filter oversampling data table indexed by fast mode flag * @sync_mode: filter synchronized with filter 0 * @fast: filter fast mode */ struct stm32_dfsdm_filter { … }; /** * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel * @id: id of the channel * @type: interface type linked to stm32_dfsdm_chan_type * @src: interface type linked to stm32_dfsdm_chan_src * @alt_si: alternative serial input interface */ struct stm32_dfsdm_channel { … }; /** * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances) * @base: control registers base cpu addr * @phys_base: DFSDM IP register physical address * @regmap: regmap for register read/write * @fl_list: filter resources list * @num_fls: number of filter resources available * @ch_list: channel resources list * @num_chs: number of channel resources available * @spi_master_freq: SPI clock out frequency */ struct stm32_dfsdm { … }; /* DFSDM channel serial spi clock source */ enum stm32_dfsdm_spi_clk_src { … }; int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm); int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm); #endif
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