/* SPDX-License-Identifier: GPL-2.0 */ /* * This file is part of STM32 ADC driver * * Copyright (C) 2016, STMicroelectronics - All Rights Reserved * Author: Fabrice Gasnier <[email protected]>. * */ #ifndef __STM32_ADC_H #define __STM32_ADC_H /* * STM32 - ADC global register map * ________________________________________________________ * | Offset | Register | * -------------------------------------------------------- * | 0x000 | Master ADC1 | * -------------------------------------------------------- * | 0x100 | Slave ADC2 | * -------------------------------------------------------- * | 0x200 | Slave ADC3 | * -------------------------------------------------------- * | 0x300 | Master & Slave common regs | * -------------------------------------------------------- */ /* Maximum ADC instances number per ADC block for all supported SoCs */ #define STM32_ADC_MAX_ADCS … #define STM32_ADC_OFFSET … #define STM32_ADCX_COMN_OFFSET … /* STM32F4 - Registers for each ADC instance */ #define STM32F4_ADC_SR … #define STM32F4_ADC_CR1 … #define STM32F4_ADC_CR2 … #define STM32F4_ADC_SMPR1 … #define STM32F4_ADC_SMPR2 … #define STM32F4_ADC_HTR … #define STM32F4_ADC_LTR … #define STM32F4_ADC_SQR1 … #define STM32F4_ADC_SQR2 … #define STM32F4_ADC_SQR3 … #define STM32F4_ADC_JSQR … #define STM32F4_ADC_JDR1 … #define STM32F4_ADC_JDR2 … #define STM32F4_ADC_JDR3 … #define STM32F4_ADC_JDR4 … #define STM32F4_ADC_DR … /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ #define STM32F4_ADC_CSR … #define STM32F4_ADC_CCR … /* STM32F4_ADC_SR - bit fields */ #define STM32F4_OVR … #define STM32F4_STRT … #define STM32F4_EOC … /* STM32F4_ADC_CR1 - bit fields */ #define STM32F4_OVRIE … #define STM32F4_RES_SHIFT … #define STM32F4_RES_MASK … #define STM32F4_SCAN … #define STM32F4_EOCIE … /* STM32F4_ADC_CR2 - bit fields */ #define STM32F4_SWSTART … #define STM32F4_EXTEN_SHIFT … #define STM32F4_EXTEN_MASK … #define STM32F4_EXTSEL_SHIFT … #define STM32F4_EXTSEL_MASK … #define STM32F4_EOCS … #define STM32F4_DDS … #define STM32F4_DMA … #define STM32F4_ADON … /* STM32F4_ADC_CSR - bit fields */ #define STM32F4_OVR3 … #define STM32F4_EOC3 … #define STM32F4_OVR2 … #define STM32F4_EOC2 … #define STM32F4_OVR1 … #define STM32F4_EOC1 … /* STM32F4_ADC_CCR - bit fields */ #define STM32F4_ADC_ADCPRE_SHIFT … #define STM32F4_ADC_ADCPRE_MASK … /* STM32H7 - Registers for each ADC instance */ #define STM32H7_ADC_ISR … #define STM32H7_ADC_IER … #define STM32H7_ADC_CR … #define STM32H7_ADC_CFGR … #define STM32H7_ADC_SMPR1 … #define STM32H7_ADC_SMPR2 … #define STM32H7_ADC_PCSEL … #define STM32H7_ADC_SQR1 … #define STM32H7_ADC_SQR2 … #define STM32H7_ADC_SQR3 … #define STM32H7_ADC_SQR4 … #define STM32H7_ADC_DR … #define STM32H7_ADC_DIFSEL … #define STM32H7_ADC_CALFACT … #define STM32H7_ADC_CALFACT2 … /* STM32MP1 - ADC2 instance option register */ #define STM32MP1_ADC2_OR … /* STM32MP1 - Identification registers */ #define STM32MP1_ADC_HWCFGR0 … #define STM32MP1_ADC_VERR … #define STM32MP1_ADC_IPDR … #define STM32MP1_ADC_SIDR … /* STM32MP13 - Registers for each ADC instance */ #define STM32MP13_ADC_DIFSEL … #define STM32MP13_ADC_CALFACT … #define STM32MP13_ADC2_OR … /* STM32H7 - common registers for all ADC instances */ #define STM32H7_ADC_CSR … #define STM32H7_ADC_CCR … /* STM32H7_ADC_ISR - bit fields */ #define STM32MP1_VREGREADY … #define STM32H7_OVR … #define STM32H7_EOC … #define STM32H7_ADRDY … /* STM32H7_ADC_IER - bit fields */ #define STM32H7_OVRIE … #define STM32H7_EOCIE … /* STM32H7_ADC_CR - bit fields */ #define STM32H7_ADCAL … #define STM32H7_ADCALDIF … #define STM32H7_DEEPPWD … #define STM32H7_ADVREGEN … #define STM32H7_LINCALRDYW6 … #define STM32H7_LINCALRDYW5 … #define STM32H7_LINCALRDYW4 … #define STM32H7_LINCALRDYW3 … #define STM32H7_LINCALRDYW2 … #define STM32H7_LINCALRDYW1 … #define STM32H7_LINCALRDYW_MASK … #define STM32H7_ADCALLIN … #define STM32H7_BOOST … #define STM32H7_ADSTP … #define STM32H7_ADSTART … #define STM32H7_ADDIS … #define STM32H7_ADEN … /* STM32H7_ADC_CFGR bit fields */ #define STM32H7_EXTEN_SHIFT … #define STM32H7_EXTEN_MASK … #define STM32H7_EXTSEL_SHIFT … #define STM32H7_EXTSEL_MASK … #define STM32H7_RES_SHIFT … #define STM32H7_RES_MASK … #define STM32H7_DMNGT_SHIFT … #define STM32H7_DMNGT_MASK … enum stm32h7_adc_dmngt { … }; /* STM32H7_ADC_DIFSEL - bit fields */ #define STM32H7_DIFSEL_MASK … /* STM32H7_ADC_CALFACT - bit fields */ #define STM32H7_CALFACT_D_SHIFT … #define STM32H7_CALFACT_D_MASK … #define STM32H7_CALFACT_S_SHIFT … #define STM32H7_CALFACT_S_MASK … /* STM32H7_ADC_CALFACT2 - bit fields */ #define STM32H7_LINCALFACT_SHIFT … #define STM32H7_LINCALFACT_MASK … /* STM32H7_ADC_CSR - bit fields */ #define STM32H7_OVR_SLV … #define STM32H7_EOC_SLV … #define STM32H7_OVR_MST … #define STM32H7_EOC_MST … /* STM32H7_ADC_CCR - bit fields */ #define STM32H7_VBATEN … #define STM32H7_VREFEN … #define STM32H7_PRESC_SHIFT … #define STM32H7_PRESC_MASK … #define STM32H7_CKMODE_SHIFT … #define STM32H7_CKMODE_MASK … /* STM32MP1_ADC2_OR - bit fields */ #define STM32MP1_VDDCOREEN … /* STM32MP1_ADC_HWCFGR0 - bit fields */ #define STM32MP1_ADCNUM_SHIFT … #define STM32MP1_ADCNUM_MASK … #define STM32MP1_MULPIPE_SHIFT … #define STM32MP1_MULPIPE_MASK … #define STM32MP1_OPBITS_SHIFT … #define STM32MP1_OPBITS_MASK … #define STM32MP1_IDLEVALUE_SHIFT … #define STM32MP1_IDLEVALUE_MASK … /* STM32MP1_ADC_VERR - bit fields */ #define STM32MP1_MINREV_SHIFT … #define STM32MP1_MINREV_MASK … #define STM32MP1_MAJREV_SHIFT … #define STM32MP1_MAJREV_MASK … /* STM32MP1_ADC_IPDR - bit fields */ #define STM32MP1_IPIDR_MASK … /* STM32MP1_ADC_SIDR - bit fields */ #define STM32MP1_SIDR_MASK … /* STM32MP13_ADC_CFGR specific bit fields */ #define STM32MP13_DMAEN … #define STM32MP13_DMACFG … #define STM32MP13_DFSDMCFG … #define STM32MP13_RES_SHIFT … #define STM32MP13_RES_MASK … /* STM32MP13_ADC_DIFSEL - bit fields */ #define STM32MP13_DIFSEL_MASK … /* STM32MP13_ADC_CALFACT - bit fields */ #define STM32MP13_CALFACT_D_SHIFT … #define STM32MP13_CALFACT_D_MASK … #define STM32MP13_CALFACT_S_SHIFT … #define STM32MP13_CALFACT_S_MASK … /* STM32MP13_ADC2_OR - bit fields */ #define STM32MP13_OP2 … #define STM32MP13_OP1 … #define STM32MP13_OP0 … #define STM32MP15_IPIDR_NUMBER … #define STM32MP13_IPIDR_NUMBER … /** * struct stm32_adc_common - stm32 ADC driver common data (for all instances) * @base: control registers base cpu addr * @phys_base: control registers base physical addr * @rate: clock rate used for analog circuitry * @vref_mv: vref voltage (mv) * @lock: spinlock */ struct stm32_adc_common { … }; #endif
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