// SPDX-License-Identifier: GPL-2.0 /* * This file is part of STM32 ADC driver * * Copyright (C) 2016, STMicroelectronics - All Rights Reserved * Author: Fabrice Gasnier <[email protected]>. */ #include <linux/clk.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/iio/iio.h> #include <linux/iio/buffer.h> #include <linux/iio/timer/stm32-lptim-trigger.h> #include <linux/iio/timer/stm32-timer-trigger.h> #include <linux/iio/trigger.h> #include <linux/iio/trigger_consumer.h> #include <linux/iio/triggered_buffer.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/nvmem-consumer.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/property.h> #include "stm32-adc-core.h" /* Number of linear calibration shadow registers / LINCALRDYW control bits */ #define STM32H7_LINCALFACT_NUM … /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ #define STM32H7_BOOST_CLKRATE … #define STM32_ADC_CH_MAX … #define STM32_ADC_CH_SZ … #define STM32_ADC_MAX_SQ … #define STM32_ADC_MAX_SMP … #define STM32_ADC_TIMEOUT_US … #define STM32_ADC_TIMEOUT … #define STM32_ADC_HW_STOP_DELAY_MS … #define STM32_ADC_VREFINT_VOLTAGE … #define STM32_DMA_BUFFER_SIZE … /* External trigger enable */ enum stm32_adc_exten { … }; /* extsel - trigger mux selection value */ enum stm32_adc_extsel { … }; enum stm32_adc_int_ch { … }; /** * struct stm32_adc_ic - ADC internal channels * @name: name of the internal channel * @idx: internal channel enum index */ struct stm32_adc_ic { … }; static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = …; /** * struct stm32_adc_trig_info - ADC trigger info * @name: name of the trigger, corresponding to its source * @extsel: trigger selection */ struct stm32_adc_trig_info { … }; /** * struct stm32_adc_calib - optional adc calibration data * @lincalfact: Linearity calibration factor * @lincal_saved: Indicates that linear calibration factors are saved */ struct stm32_adc_calib { … }; /** * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc * @reg: register offset * @mask: bitfield mask * @shift: left shift */ struct stm32_adc_regs { … }; /** * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data * @vrefint_cal: vrefint calibration value from nvmem * @vrefint_data: vrefint actual value */ struct stm32_adc_vrefint { … }; /** * struct stm32_adc_regspec - stm32 registers definition * @dr: data register offset * @ier_eoc: interrupt enable register & eocie bitfield * @ier_ovr: interrupt enable register & overrun bitfield * @isr_eoc: interrupt status register & eoc bitfield * @isr_ovr: interrupt status register & overrun bitfield * @sqr: reference to sequence registers array * @exten: trigger control register & bitfield * @extsel: trigger selection register & bitfield * @res: resolution selection register & bitfield * @difsel: differential mode selection register & bitfield * @smpr: smpr1 & smpr2 registers offset array * @smp_bits: smpr1 & smpr2 index and bitfields * @or_vddcore: option register & vddcore bitfield * @or_vddcpu: option register & vddcpu bitfield * @or_vddq_ddr: option register & vddq_ddr bitfield * @ccr_vbat: common register & vbat bitfield * @ccr_vref: common register & vrefint bitfield */ struct stm32_adc_regspec { … }; struct stm32_adc; /** * struct stm32_adc_cfg - stm32 compatible configuration data * @regs: registers descriptions * @adc_info: per instance input channels definitions * @trigs: external trigger sources * @clk_required: clock is required * @has_vregready: vregready status flag presence * @has_boostmode: boost mode support flag * @has_linearcal: linear calibration support flag * @has_presel: channel preselection support flag * @prepare: optional prepare routine (power-up, enable) * @start_conv: routine to start conversions * @stop_conv: routine to stop conversions * @unprepare: optional unprepare routine (disable, power-down) * @irq_clear: routine to clear irqs * @smp_cycles: programmable sampling time (ADC clock cycles) * @ts_int_ch: pointer to array of internal channels minimum sampling time in ns */ struct stm32_adc_cfg { … }; /** * struct stm32_adc - private data of each ADC IIO instance * @common: reference to ADC block common data * @offset: ADC instance register offset in ADC block * @cfg: compatible configuration data * @completion: end of single conversion completion * @buffer: data buffer + 8 bytes for timestamp if enabled * @clk: clock for this adc instance * @irq: interrupt for this adc instance * @lock: spinlock * @bufi: data buffer index * @num_conv: expected number of scan conversions * @res: data resolution (e.g. RES bitfield value) * @trigger_polarity: external trigger polarity (e.g. exten) * @dma_chan: dma channel * @rx_buf: dma rx buffer cpu address * @rx_dma_buf: dma rx buffer bus address * @rx_buf_sz: dma rx buffer size * @difsel: bitmask to set single-ended/differential channel * @pcsel: bitmask to preselect channels on some devices * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) * @cal: optional calibration data on some devices * @vrefint: internal reference voltage data * @chan_name: channel name array * @num_diff: number of differential channels * @int_ch: internal channel indexes array * @nsmps: number of channels with optional sample time */ struct stm32_adc { … }; struct stm32_adc_diff_channel { … }; /** * struct stm32_adc_info - stm32 ADC, per instance config data * @max_channels: Number of channels * @resolutions: available resolutions * @num_res: number of available resolutions */ struct stm32_adc_info { … }; static const unsigned int stm32f4_adc_resolutions[] = …; /* stm32f4 can have up to 16 channels */ static const struct stm32_adc_info stm32f4_adc_info = …; static const unsigned int stm32h7_adc_resolutions[] = …; /* stm32h7 can have up to 20 channels */ static const struct stm32_adc_info stm32h7_adc_info = …; /* stm32mp13 can have up to 19 channels */ static const struct stm32_adc_info stm32mp13_adc_info = …; /* * stm32f4_sq - describe regular sequence registers * - L: sequence len (register & bit field) * - SQ1..SQ16: sequence entries (register & bit field) */ static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = …; /* STM32F4 external trigger sources for all instances */ static struct stm32_adc_trig_info stm32f4_adc_trigs[] = …; /* * stm32f4_smp_bits[] - describe sampling time register index & bit fields * Sorted so it can be indexed by channel number. */ static const struct stm32_adc_regs stm32f4_smp_bits[] = …; /* STM32F4 programmable sampling time (ADC clock cycles) */ static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = …; static const struct stm32_adc_regspec stm32f4_adc_regspec = …; static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = …; /* STM32H7 external trigger sources for all instances */ static struct stm32_adc_trig_info stm32h7_adc_trigs[] = …; /* * stm32h7_smp_bits - describe sampling time register index & bit fields * Sorted so it can be indexed by channel number. */ static const struct stm32_adc_regs stm32h7_smp_bits[] = …; /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = …; static const struct stm32_adc_regspec stm32h7_adc_regspec = …; /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */ static const unsigned int stm32mp13_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = …; static const struct stm32_adc_regspec stm32mp13_adc_regspec = …; static const struct stm32_adc_regspec stm32mp1_adc_regspec = …; /* * STM32 ADC registers access routines * @adc: stm32 adc instance * @reg: reg offset in adc instance * * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. * for adc1, adc2 and adc3. */ static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) { … } #define stm32_adc_readl_addr(addr) … #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) … static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) { … } static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) { … } static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) { … } static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) { … } static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) { … } static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) { … } /** * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt * @adc: stm32 adc instance */ static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) { stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, adc->cfg->regs->ier_eoc.mask); }; /** * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt * @adc: stm32 adc instance */ static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) { … } static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) { … } static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) { … } static void stm32_adc_set_res(struct stm32_adc *adc) { … } static int stm32_adc_hw_stop(struct device *dev) { … } static int stm32_adc_hw_start(struct device *dev) { … } static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) { … } static void stm32_adc_int_ch_disable(struct stm32_adc *adc) { … } /** * stm32f4_adc_start_conv() - Start conversions for regular channels. * @indio_dev: IIO device instance * @dma: use dma to transfer conversion result * * Start conversions for regular channels. * Also take care of normal or DMA mode. Circular DMA may be used for regular * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). */ static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) { … } static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) { … } static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) { … } static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) { … } static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) { … } static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) { … } static void stm32mp13_adc_start_conv(struct iio_dev *indio_dev, bool dma) { … } static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) { … } static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) { … } static int stm32h7_adc_enable(struct iio_dev *indio_dev) { … } static void stm32h7_adc_disable(struct iio_dev *indio_dev) { … } /** * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result * @indio_dev: IIO device instance * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable */ static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) { … } /** * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result * @indio_dev: IIO device instance * Note: ADC must be enabled, with no on-going conversions. */ static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) { … } /* * Fixed timeout value for ADC calibration. * worst cases: * - low clock frequency * - maximum prescalers * Calibration requires: * - 131,072 ADC clock cycle for the linear calibration * - 20 ADC clock cycle for the offset calibration * * Set to 100ms for now */ #define STM32H7_ADC_CALIB_TIMEOUT_US … /** * stm32h7_adc_selfcalib() - Procedure to calibrate ADC * @indio_dev: IIO device instance * @do_lincal: linear calibration request flag * Note: Must be called once ADC is out of power down. * * Run offset calibration unconditionally. * Run linear calibration if requested & supported. */ static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev, int do_lincal) { … } /** * stm32h7_adc_check_selfcalib() - Check linear calibration status * @indio_dev: IIO device instance * * Used to check if linear calibration has been done. * Return true if linear calibration factors are already saved in private data * or if a linear calibration has been done at boot stage. */ static int stm32h7_adc_check_selfcalib(struct iio_dev *indio_dev) { … } /** * stm32h7_adc_prepare() - Leave power down mode to enable ADC. * @indio_dev: IIO device instance * Leave power down mode. * Configure channels as single ended or differential before enabling ADC. * Enable ADC. * Restore calibration data. * Pre-select channels that may be used in PCSEL (required by input MUX / IO): * - Only one input is selected for single ended (e.g. 'vinp') * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') */ static int stm32h7_adc_prepare(struct iio_dev *indio_dev) { … } static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) { … } /** * stm32_adc_conf_scan_seq() - Build regular channels scan sequence * @indio_dev: IIO device * @scan_mask: channels to be converted * * Conversion sequence : * Apply sampling time settings for all channels. * Configure ADC scan sequence based on selected channels in scan_mask. * Add channels to SQR registers, from scan_mask LSB to MSB, then * program sequence len. */ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, const unsigned long *scan_mask) { … } /** * stm32_adc_get_trig_extsel() - Get external trigger selection * @indio_dev: IIO device structure * @trig: trigger * * Returns trigger extsel value, if trig matches, -EINVAL otherwise. */ static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, struct iio_trigger *trig) { … } /** * stm32_adc_set_trig() - Set a regular trigger * @indio_dev: IIO device * @trig: IIO trigger * * Set trigger source/polarity (e.g. SW, or HW with polarity) : * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) * - if HW trigger enabled, set source & polarity */ static int stm32_adc_set_trig(struct iio_dev *indio_dev, struct iio_trigger *trig) { … } static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, unsigned int type) { … } static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { … } static const char * const stm32_trig_pol_items[] = …; static const struct iio_enum stm32_adc_trig_pol = …; /** * stm32_adc_single_conv() - Performs a single conversion * @indio_dev: IIO device * @chan: IIO channel * @res: conversion result * * The function performs a single conversion on a given channel: * - Apply sampling time settings * - Program sequencer with one channel (e.g. in SQ1 with len = 1) * - Use SW trigger * - Start conversion, then wait for interrupt completion. */ static int stm32_adc_single_conv(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *res) { … } static int stm32_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { … } static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) { … } static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) { … } static irqreturn_t stm32_adc_isr(int irq, void *data) { … } /** * stm32_adc_validate_trigger() - validate trigger for stm32 adc * @indio_dev: IIO device * @trig: new trigger * * Returns: 0 if trig matches one of the triggers registered by stm32 adc * driver, -EINVAL otherwise. */ static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig) { … } static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) { … } static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { … } static int stm32_adc_fwnode_xlate(struct iio_dev *indio_dev, const struct fwnode_reference_args *iiospec) { … } /** * stm32_adc_debugfs_reg_access - read or write register value * @indio_dev: IIO device structure * @reg: register offset * @writeval: value to write * @readval: value to read * * To read a value from an ADC register: * echo [ADC reg offset] > direct_reg_access * cat direct_reg_access * * To write a value in a ADC register: * echo [ADC_reg_offset] [value] > direct_reg_access */ static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, unsigned reg, unsigned writeval, unsigned *readval) { … } static const struct iio_info stm32_adc_iio_info = …; static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) { … } static void stm32_adc_dma_buffer_done(void *data) { … } static int stm32_adc_dma_start(struct iio_dev *indio_dev) { … } static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) { … } static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) { … } static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = …; static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) { … } static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = …; static void stm32_adc_debugfs_init(struct iio_dev *indio_dev) { … } static int stm32_adc_fw_get_resolution(struct iio_dev *indio_dev) { … } static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) { … } static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, struct iio_chan_spec *chan, u32 vinp, u32 vinn, int scan_index, bool differential) { … } static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) { … } static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, struct stm32_adc *adc, struct iio_chan_spec *channels, int nchans) { … } static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, int chan) { … } static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, struct stm32_adc *adc, struct iio_chan_spec *channels) { … } static int stm32_adc_chan_fw_init(struct iio_dev *indio_dev, bool timestamping) { … } static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) { … } static int stm32_adc_probe(struct platform_device *pdev) { … } static void stm32_adc_remove(struct platform_device *pdev) { … } static int stm32_adc_suspend(struct device *dev) { … } static int stm32_adc_resume(struct device *dev) { … } static int stm32_adc_runtime_suspend(struct device *dev) { … } static int stm32_adc_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops stm32_adc_pm_ops = …; static const struct stm32_adc_cfg stm32f4_adc_cfg = …; static const unsigned int stm32_adc_min_ts_h7[] = …; static_assert(…); static const struct stm32_adc_cfg stm32h7_adc_cfg = …; static const unsigned int stm32_adc_min_ts_mp1[] = …; static_assert(…); static const struct stm32_adc_cfg stm32mp1_adc_cfg = …; static const unsigned int stm32_adc_min_ts_mp13[] = …; static_assert(…); static const struct stm32_adc_cfg stm32mp13_adc_cfg = …; static const struct of_device_id stm32_adc_of_match[] = …; MODULE_DEVICE_TABLE(of, stm32_adc_of_match); static struct platform_driver stm32_adc_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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