// SPDX-License-Identifier: GPL-2.0 /* * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs * * Copyright (c) 2020 AVL DiTEST GmbH * Tomislav Denis <[email protected]> * * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/iio/buffer.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> #include <linux/iio/trigger.h> #include <linux/iio/trigger_consumer.h> #include <linux/iio/triggered_buffer.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> #include <linux/unaligned.h> /* Commands */ #define ADS131E08_CMD_RESET … #define ADS131E08_CMD_START … #define ADS131E08_CMD_STOP … #define ADS131E08_CMD_OFFSETCAL … #define ADS131E08_CMD_SDATAC … #define ADS131E08_CMD_RDATA … #define ADS131E08_CMD_RREG(r) … #define ADS131E08_CMD_WREG(r) … /* Registers */ #define ADS131E08_ADR_CFG1R … #define ADS131E08_ADR_CFG3R … #define ADS131E08_ADR_CH0R … /* Configuration register 1 */ #define ADS131E08_CFG1R_DR_MASK … /* Configuration register 3 */ #define ADS131E08_CFG3R_PDB_REFBUF_MASK … #define ADS131E08_CFG3R_VREF_4V_MASK … /* Channel settings register */ #define ADS131E08_CHR_GAIN_MASK … #define ADS131E08_CHR_MUX_MASK … #define ADS131E08_CHR_PWD_MASK … /* ADC misc */ #define ADS131E08_DEFAULT_DATA_RATE … #define ADS131E08_DEFAULT_PGA_GAIN … #define ADS131E08_DEFAULT_MUX … #define ADS131E08_VREF_2V4_mV … #define ADS131E08_VREF_4V_mV … #define ADS131E08_WAIT_RESET_CYCLES … #define ADS131E08_WAIT_SDECODE_CYCLES … #define ADS131E08_WAIT_OFFSETCAL_MS … #define ADS131E08_MAX_SETTLING_TIME_MS … #define ADS131E08_NUM_STATUS_BYTES … #define ADS131E08_NUM_DATA_BYTES_MAX … #define ADS131E08_NUM_DATA_BYTES(dr) … #define ADS131E08_NUM_DATA_BITS(dr) … #define ADS131E08_NUM_STORAGE_BYTES … enum ads131e08_ids { … }; struct ads131e08_info { … }; struct ads131e08_channel_config { … }; struct ads131e08_state { … }; static const struct ads131e08_info ads131e08_info_tbl[] = …; struct ads131e08_data_rate_desc { … }; static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = …; struct ads131e08_pga_gain_desc { … }; static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = …; static const u8 ads131e08_valid_channel_mux_values[] = …; static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd) { … } static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg) { … } static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value) { … } static int ads131e08_read_data(struct ads131e08_state *st, int rx_len) { … } static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate) { … } static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st, unsigned int pga_gain) { … } static int ads131e08_set_pga_gain(struct ads131e08_state *st, unsigned int channel, unsigned int pga_gain) { … } static int ads131e08_validate_channel_mux(struct ads131e08_state *st, unsigned int mux) { … } static int ads131e08_set_channel_mux(struct ads131e08_state *st, unsigned int channel, unsigned int mux) { … } static int ads131e08_power_down_channel(struct ads131e08_state *st, unsigned int channel, bool value) { … } static int ads131e08_config_reference_voltage(struct ads131e08_state *st) { … } static int ads131e08_initial_config(struct iio_dev *indio_dev) { … } static int ads131e08_pool_data(struct ads131e08_state *st) { … } static int ads131e08_read_direct(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int *value) { … } static int ads131e08_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int *value, int *value2, long mask) { … } static int ads131e08_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int value, int value2, long mask) { … } static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64"); static struct attribute *ads131e08_attributes[] = …; static const struct attribute_group ads131e08_attribute_group = …; static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { … } static const struct iio_info ads131e08_iio_info = …; static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state) { … } static const struct iio_trigger_ops ads131e08_trigger_ops = …; static irqreturn_t ads131e08_trigger_handler(int irq, void *private) { … } static irqreturn_t ads131e08_interrupt(int irq, void *private) { … } static int ads131e08_alloc_channels(struct iio_dev *indio_dev) { … } static void ads131e08_regulator_disable(void *data) { … } static int ads131e08_probe(struct spi_device *spi) { … } static const struct of_device_id ads131e08_of_match[] = …; MODULE_DEVICE_TABLE(of, ads131e08_of_match); static const struct spi_device_id ads131e08_ids[] = …; MODULE_DEVICE_TABLE(spi, ads131e08_ids); static struct spi_driver ads131e08_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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