/* SPDX-License-Identifier: GPL-2.0-only */ /* * ADF4350/ADF4351 SPI PLL driver * * Copyright 2012-2013 Analog Devices Inc. */ #ifndef IIO_PLL_ADF4350_H_ #define IIO_PLL_ADF4350_H_ /* Registers */ #define ADF4350_REG0 … #define ADF4350_REG1 … #define ADF4350_REG2 … #define ADF4350_REG3 … #define ADF4350_REG4 … #define ADF4350_REG5 … /* REG0 Bit Definitions */ #define ADF4350_REG0_FRACT(x) … #define ADF4350_REG0_INT(x) … /* REG1 Bit Definitions */ #define ADF4350_REG1_MOD(x) … #define ADF4350_REG1_PHASE(x) … #define ADF4350_REG1_PRESCALER … /* REG2 Bit Definitions */ #define ADF4350_REG2_COUNTER_RESET_EN … #define ADF4350_REG2_CP_THREESTATE_EN … #define ADF4350_REG2_POWER_DOWN_EN … #define ADF4350_REG2_PD_POLARITY_POS … #define ADF4350_REG2_LDP_6ns … #define ADF4350_REG2_LDP_10ns … #define ADF4350_REG2_LDF_FRACT_N … #define ADF4350_REG2_LDF_INT_N … #define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x) … #define ADF4350_REG2_DOUBLE_BUFF_EN … #define ADF4350_REG2_10BIT_R_CNT(x) … #define ADF4350_REG2_RDIV2_EN … #define ADF4350_REG2_RMULT2_EN … #define ADF4350_REG2_MUXOUT(x) … #define ADF4350_REG2_NOISE_MODE(x) … #define ADF4350_MUXOUT_THREESTATE … #define ADF4350_MUXOUT_DVDD … #define ADF4350_MUXOUT_GND … #define ADF4350_MUXOUT_R_DIV_OUT … #define ADF4350_MUXOUT_N_DIV_OUT … #define ADF4350_MUXOUT_ANALOG_LOCK_DETECT … #define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT … /* REG3 Bit Definitions */ #define ADF4350_REG3_12BIT_CLKDIV(x) … #define ADF4350_REG3_12BIT_CLKDIV_MODE(x) … #define ADF4350_REG3_12BIT_CSR_EN … #define ADF4351_REG3_CHARGE_CANCELLATION_EN … #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN … #define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH … /* REG4 Bit Definitions */ #define ADF4350_REG4_OUTPUT_PWR(x) … #define ADF4350_REG4_RF_OUT_EN … #define ADF4350_REG4_AUX_OUTPUT_PWR(x) … #define ADF4350_REG4_AUX_OUTPUT_EN … #define ADF4350_REG4_AUX_OUTPUT_FUND … #define ADF4350_REG4_AUX_OUTPUT_DIV … #define ADF4350_REG4_MUTE_TILL_LOCK_EN … #define ADF4350_REG4_VCO_PWRDOWN_EN … #define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x) … #define ADF4350_REG4_RF_DIV_SEL(x) … #define ADF4350_REG4_FEEDBACK_DIVIDED … #define ADF4350_REG4_FEEDBACK_FUND … /* REG5 Bit Definitions */ #define ADF4350_REG5_LD_PIN_MODE_LOW … #define ADF4350_REG5_LD_PIN_MODE_DIGITAL … #define ADF4350_REG5_LD_PIN_MODE_HIGH … /* Specifications */ #define ADF4350_MAX_OUT_FREQ … #define ADF4350_MIN_OUT_FREQ … #define ADF4351_MIN_OUT_FREQ … #define ADF4350_MIN_VCO_FREQ … #define ADF4350_MAX_FREQ_45_PRESC … #define ADF4350_MAX_FREQ_PFD … #define ADF4350_MAX_BANDSEL_CLK … #define ADF4350_MAX_FREQ_REFIN … #define ADF4350_MAX_MODULUS … #define ADF4350_MAX_R_CNT … /** * struct adf4350_platform_data - platform specific information * @name: Optional device name. * @clkin: REFin frequency in Hz. * @channel_spacing: Channel spacing in Hz (influences MODULUS). * @power_up_frequency: Optional, If set in Hz the PLL tunes to the desired * frequency on probe. * @ref_div_factor: Optional, if set the driver skips dynamic calculation * and uses this default value instead. * @ref_doubler_en: Enables reference doubler. * @ref_div2_en: Enables reference divider. * @r2_user_settings: User defined settings for ADF4350/1 REGISTER_2. * @r3_user_settings: User defined settings for ADF4350/1 REGISTER_3. * @r4_user_settings: User defined settings for ADF4350/1 REGISTER_4. */ struct adf4350_platform_data { … }; #endif /* IIO_PLL_ADF4350_H_ */
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