/* * This file is provided under a GPLv2 license. When using or * redistributing this file, you may do so under that license. * * GPL LICENSE SUMMARY * * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General * Public License for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, one can be found http://www.gnu.org/licenses/. * * The full GNU General Public License is included in this distribution in * the file called "COPYING". * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * IDT PCIe-switch NTB Linux driver * * Contact Information: * Serge Semin <[email protected]>, <[email protected]> */ #ifndef NTB_HW_IDT_H #define NTB_HW_IDT_H #include <linux/types.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/mutex.h> #include <linux/ntb.h> /* * Macro is used to create the struct pci_device_id that matches * the supported IDT PCIe-switches * @devname: Capitalized name of the particular device * @data: Variable passed to the driver of the particular device */ #define IDT_PCI_DEVICE_IDS(devname, data) … /* * IDT PCIe-switches device IDs */ #define PCI_DEVICE_ID_IDT_89HPES24NT6AG2 … #define PCI_DEVICE_ID_IDT_89HPES32NT8AG2 … #define PCI_DEVICE_ID_IDT_89HPES32NT8BG2 … #define PCI_DEVICE_ID_IDT_89HPES12NT12G2 … #define PCI_DEVICE_ID_IDT_89HPES16NT16G2 … #define PCI_DEVICE_ID_IDT_89HPES24NT24G2 … #define PCI_DEVICE_ID_IDT_89HPES32NT24AG2 … #define PCI_DEVICE_ID_IDT_89HPES32NT24BG2 … /* * NT-function Configuration Space registers * NOTE 1) The IDT PCIe-switch internal data is little-endian * so it must be taken into account in the driver * internals. * 2) Additionally the registers should be accessed either * with byte-enables corresponding to their native size or * the size of one DWORD * * So to simplify the driver code, there is only DWORD-sized read/write * operations utilized. */ /* PCI Express Configuration Space */ /* PCI Express command/status register (DWORD) */ #define IDT_NT_PCICMDSTS … /* PCI Express Device Capabilities (DWORD) */ #define IDT_NT_PCIEDCAP … /* PCI Express Device Control/Status (WORD+WORD) */ #define IDT_NT_PCIEDCTLSTS … /* PCI Express Link Capabilities (DWORD) */ #define IDT_NT_PCIELCAP … /* PCI Express Link Control/Status (WORD+WORD) */ #define IDT_NT_PCIELCTLSTS … /* PCI Express Device Capabilities 2 (DWORD) */ #define IDT_NT_PCIEDCAP2 … /* PCI Express Device Control 2 (WORD+WORD) */ #define IDT_NT_PCIEDCTL2 … /* PCI Power Management Control and Status (DWORD) */ #define IDT_NT_PMCSR … /*==========================================*/ /* IDT Proprietary NT-port-specific registers */ /* NT-function main control registers */ /* NT Endpoint Control (DWORD) */ #define IDT_NT_NTCTL … /* NT Endpoint Interrupt Status/Mask (DWORD) */ #define IDT_NT_NTINTSTS … #define IDT_NT_NTINTMSK … /* NT Endpoint Signal Data (DWORD) */ #define IDT_NT_NTSDATA … /* NT Endpoint Global Signal (DWORD) */ #define IDT_NT_NTGSIGNAL … /* Internal Error Reporting Mask 0/1 (DWORD) */ #define IDT_NT_NTIERRORMSK0 … #define IDT_NT_NTIERRORMSK1 … /* Doorbel registers */ /* NT Outbound Doorbell Set (DWORD) */ #define IDT_NT_OUTDBELLSET … /* NT Inbound Doorbell Status/Mask (DWORD) */ #define IDT_NT_INDBELLSTS … #define IDT_NT_INDBELLMSK … /* Message registers */ /* Outbound Message N (DWORD) */ #define IDT_NT_OUTMSG0 … #define IDT_NT_OUTMSG1 … #define IDT_NT_OUTMSG2 … #define IDT_NT_OUTMSG3 … /* Inbound Message N (DWORD) */ #define IDT_NT_INMSG0 … #define IDT_NT_INMSG1 … #define IDT_NT_INMSG2 … #define IDT_NT_INMSG3 … /* Inbound Message Source N (DWORD) */ #define IDT_NT_INMSGSRC0 … #define IDT_NT_INMSGSRC1 … #define IDT_NT_INMSGSRC2 … #define IDT_NT_INMSGSRC3 … /* Message Status (DWORD) */ #define IDT_NT_MSGSTS … /* Message Status Mask (DWORD) */ #define IDT_NT_MSGSTSMSK … /* BAR-setup registers */ /* BAR N Setup/Limit Address/Lower and Upper Translated Base Address (DWORD) */ #define IDT_NT_BARSETUP0 … #define IDT_NT_BARLIMIT0 … #define IDT_NT_BARLTBASE0 … #define IDT_NT_BARUTBASE0 … #define IDT_NT_BARSETUP1 … #define IDT_NT_BARLIMIT1 … #define IDT_NT_BARLTBASE1 … #define IDT_NT_BARUTBASE1 … #define IDT_NT_BARSETUP2 … #define IDT_NT_BARLIMIT2 … #define IDT_NT_BARLTBASE2 … #define IDT_NT_BARUTBASE2 … #define IDT_NT_BARSETUP3 … #define IDT_NT_BARLIMIT3 … #define IDT_NT_BARLTBASE3 … #define IDT_NT_BARUTBASE3 … #define IDT_NT_BARSETUP4 … #define IDT_NT_BARLIMIT4 … #define IDT_NT_BARLTBASE4 … #define IDT_NT_BARUTBASE4 … #define IDT_NT_BARSETUP5 … #define IDT_NT_BARLIMIT5 … #define IDT_NT_BARLTBASE5 … #define IDT_NT_BARUTBASE5 … /* NT mapping table registers */ /* NT Mapping Table Address/Status/Data (DWORD) */ #define IDT_NT_NTMTBLADDR … #define IDT_NT_NTMTBLSTS … #define IDT_NT_NTMTBLDATA … /* Requester ID (Bus:Device:Function) Capture (DWORD) */ #define IDT_NT_REQIDCAP … /* Memory Windows Lookup table registers */ /* Lookup Table Offset/Lower, Middle and Upper data (DWORD) */ #define IDT_NT_LUTOFFSET … #define IDT_NT_LUTLDATA … #define IDT_NT_LUTMDATA … #define IDT_NT_LUTUDATA … /* NT Endpoint Uncorrectable/Correctable Errors Emulation registers (DWORD) */ #define IDT_NT_NTUEEM … #define IDT_NT_NTCEEM … /* Global Address Space Access/Data registers (DWARD) */ #define IDT_NT_GASAADDR … #define IDT_NT_GASADATA … /* * IDT PCIe-switch Global Configuration and Status registers */ /* Port N Configuration register in global space */ /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP0_PCIECMDSTS … #define IDT_SW_NTP0_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP0_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP0_BARSETUP0 … #define IDT_SW_NTP0_BARLIMIT0 … #define IDT_SW_NTP0_BARLTBASE0 … #define IDT_SW_NTP0_BARUTBASE0 … #define IDT_SW_NTP0_BARSETUP1 … #define IDT_SW_NTP0_BARLIMIT1 … #define IDT_SW_NTP0_BARLTBASE1 … #define IDT_SW_NTP0_BARUTBASE1 … #define IDT_SW_NTP0_BARSETUP2 … #define IDT_SW_NTP0_BARLIMIT2 … #define IDT_SW_NTP0_BARLTBASE2 … #define IDT_SW_NTP0_BARUTBASE2 … #define IDT_SW_NTP0_BARSETUP3 … #define IDT_SW_NTP0_BARLIMIT3 … #define IDT_SW_NTP0_BARLTBASE3 … #define IDT_SW_NTP0_BARUTBASE3 … #define IDT_SW_NTP0_BARSETUP4 … #define IDT_SW_NTP0_BARLIMIT4 … #define IDT_SW_NTP0_BARLTBASE4 … #define IDT_SW_NTP0_BARUTBASE4 … #define IDT_SW_NTP0_BARSETUP5 … #define IDT_SW_NTP0_BARLIMIT5 … #define IDT_SW_NTP0_BARLTBASE5 … #define IDT_SW_NTP0_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP2_PCIECMDSTS … #define IDT_SW_NTP2_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP2_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP2_BARSETUP0 … #define IDT_SW_NTP2_BARLIMIT0 … #define IDT_SW_NTP2_BARLTBASE0 … #define IDT_SW_NTP2_BARUTBASE0 … #define IDT_SW_NTP2_BARSETUP1 … #define IDT_SW_NTP2_BARLIMIT1 … #define IDT_SW_NTP2_BARLTBASE1 … #define IDT_SW_NTP2_BARUTBASE1 … #define IDT_SW_NTP2_BARSETUP2 … #define IDT_SW_NTP2_BARLIMIT2 … #define IDT_SW_NTP2_BARLTBASE2 … #define IDT_SW_NTP2_BARUTBASE2 … #define IDT_SW_NTP2_BARSETUP3 … #define IDT_SW_NTP2_BARLIMIT3 … #define IDT_SW_NTP2_BARLTBASE3 … #define IDT_SW_NTP2_BARUTBASE3 … #define IDT_SW_NTP2_BARSETUP4 … #define IDT_SW_NTP2_BARLIMIT4 … #define IDT_SW_NTP2_BARLTBASE4 … #define IDT_SW_NTP2_BARUTBASE4 … #define IDT_SW_NTP2_BARSETUP5 … #define IDT_SW_NTP2_BARLIMIT5 … #define IDT_SW_NTP2_BARLTBASE5 … #define IDT_SW_NTP2_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP4_PCIECMDSTS … #define IDT_SW_NTP4_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP4_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP4_BARSETUP0 … #define IDT_SW_NTP4_BARLIMIT0 … #define IDT_SW_NTP4_BARLTBASE0 … #define IDT_SW_NTP4_BARUTBASE0 … #define IDT_SW_NTP4_BARSETUP1 … #define IDT_SW_NTP4_BARLIMIT1 … #define IDT_SW_NTP4_BARLTBASE1 … #define IDT_SW_NTP4_BARUTBASE1 … #define IDT_SW_NTP4_BARSETUP2 … #define IDT_SW_NTP4_BARLIMIT2 … #define IDT_SW_NTP4_BARLTBASE2 … #define IDT_SW_NTP4_BARUTBASE2 … #define IDT_SW_NTP4_BARSETUP3 … #define IDT_SW_NTP4_BARLIMIT3 … #define IDT_SW_NTP4_BARLTBASE3 … #define IDT_SW_NTP4_BARUTBASE3 … #define IDT_SW_NTP4_BARSETUP4 … #define IDT_SW_NTP4_BARLIMIT4 … #define IDT_SW_NTP4_BARLTBASE4 … #define IDT_SW_NTP4_BARUTBASE4 … #define IDT_SW_NTP4_BARSETUP5 … #define IDT_SW_NTP4_BARLIMIT5 … #define IDT_SW_NTP4_BARLTBASE5 … #define IDT_SW_NTP4_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP6_PCIECMDSTS … #define IDT_SW_NTP6_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP6_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP6_BARSETUP0 … #define IDT_SW_NTP6_BARLIMIT0 … #define IDT_SW_NTP6_BARLTBASE0 … #define IDT_SW_NTP6_BARUTBASE0 … #define IDT_SW_NTP6_BARSETUP1 … #define IDT_SW_NTP6_BARLIMIT1 … #define IDT_SW_NTP6_BARLTBASE1 … #define IDT_SW_NTP6_BARUTBASE1 … #define IDT_SW_NTP6_BARSETUP2 … #define IDT_SW_NTP6_BARLIMIT2 … #define IDT_SW_NTP6_BARLTBASE2 … #define IDT_SW_NTP6_BARUTBASE2 … #define IDT_SW_NTP6_BARSETUP3 … #define IDT_SW_NTP6_BARLIMIT3 … #define IDT_SW_NTP6_BARLTBASE3 … #define IDT_SW_NTP6_BARUTBASE3 … #define IDT_SW_NTP6_BARSETUP4 … #define IDT_SW_NTP6_BARLIMIT4 … #define IDT_SW_NTP6_BARLTBASE4 … #define IDT_SW_NTP6_BARUTBASE4 … #define IDT_SW_NTP6_BARSETUP5 … #define IDT_SW_NTP6_BARLIMIT5 … #define IDT_SW_NTP6_BARLTBASE5 … #define IDT_SW_NTP6_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP8_PCIECMDSTS … #define IDT_SW_NTP8_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP8_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP8_BARSETUP0 … #define IDT_SW_NTP8_BARLIMIT0 … #define IDT_SW_NTP8_BARLTBASE0 … #define IDT_SW_NTP8_BARUTBASE0 … #define IDT_SW_NTP8_BARSETUP1 … #define IDT_SW_NTP8_BARLIMIT1 … #define IDT_SW_NTP8_BARLTBASE1 … #define IDT_SW_NTP8_BARUTBASE1 … #define IDT_SW_NTP8_BARSETUP2 … #define IDT_SW_NTP8_BARLIMIT2 … #define IDT_SW_NTP8_BARLTBASE2 … #define IDT_SW_NTP8_BARUTBASE2 … #define IDT_SW_NTP8_BARSETUP3 … #define IDT_SW_NTP8_BARLIMIT3 … #define IDT_SW_NTP8_BARLTBASE3 … #define IDT_SW_NTP8_BARUTBASE3 … #define IDT_SW_NTP8_BARSETUP4 … #define IDT_SW_NTP8_BARLIMIT4 … #define IDT_SW_NTP8_BARLTBASE4 … #define IDT_SW_NTP8_BARUTBASE4 … #define IDT_SW_NTP8_BARSETUP5 … #define IDT_SW_NTP8_BARLIMIT5 … #define IDT_SW_NTP8_BARLTBASE5 … #define IDT_SW_NTP8_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP12_PCIECMDSTS … #define IDT_SW_NTP12_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP12_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP12_BARSETUP0 … #define IDT_SW_NTP12_BARLIMIT0 … #define IDT_SW_NTP12_BARLTBASE0 … #define IDT_SW_NTP12_BARUTBASE0 … #define IDT_SW_NTP12_BARSETUP1 … #define IDT_SW_NTP12_BARLIMIT1 … #define IDT_SW_NTP12_BARLTBASE1 … #define IDT_SW_NTP12_BARUTBASE1 … #define IDT_SW_NTP12_BARSETUP2 … #define IDT_SW_NTP12_BARLIMIT2 … #define IDT_SW_NTP12_BARLTBASE2 … #define IDT_SW_NTP12_BARUTBASE2 … #define IDT_SW_NTP12_BARSETUP3 … #define IDT_SW_NTP12_BARLIMIT3 … #define IDT_SW_NTP12_BARLTBASE3 … #define IDT_SW_NTP12_BARUTBASE3 … #define IDT_SW_NTP12_BARSETUP4 … #define IDT_SW_NTP12_BARLIMIT4 … #define IDT_SW_NTP12_BARLTBASE4 … #define IDT_SW_NTP12_BARUTBASE4 … #define IDT_SW_NTP12_BARSETUP5 … #define IDT_SW_NTP12_BARLIMIT5 … #define IDT_SW_NTP12_BARLTBASE5 … #define IDT_SW_NTP12_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP16_PCIECMDSTS … #define IDT_SW_NTP16_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP16_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP16_BARSETUP0 … #define IDT_SW_NTP16_BARLIMIT0 … #define IDT_SW_NTP16_BARLTBASE0 … #define IDT_SW_NTP16_BARUTBASE0 … #define IDT_SW_NTP16_BARSETUP1 … #define IDT_SW_NTP16_BARLIMIT1 … #define IDT_SW_NTP16_BARLTBASE1 … #define IDT_SW_NTP16_BARUTBASE1 … #define IDT_SW_NTP16_BARSETUP2 … #define IDT_SW_NTP16_BARLIMIT2 … #define IDT_SW_NTP16_BARLTBASE2 … #define IDT_SW_NTP16_BARUTBASE2 … #define IDT_SW_NTP16_BARSETUP3 … #define IDT_SW_NTP16_BARLIMIT3 … #define IDT_SW_NTP16_BARLTBASE3 … #define IDT_SW_NTP16_BARUTBASE3 … #define IDT_SW_NTP16_BARSETUP4 … #define IDT_SW_NTP16_BARLIMIT4 … #define IDT_SW_NTP16_BARLTBASE4 … #define IDT_SW_NTP16_BARUTBASE4 … #define IDT_SW_NTP16_BARSETUP5 … #define IDT_SW_NTP16_BARLIMIT5 … #define IDT_SW_NTP16_BARLTBASE5 … #define IDT_SW_NTP16_BARUTBASE5 … /* PCI Express command/status and link control/status registers (WORD+WORD) */ #define IDT_SW_NTP20_PCIECMDSTS … #define IDT_SW_NTP20_PCIELCTLSTS … /* NT-function control register (DWORD) */ #define IDT_SW_NTP20_NTCTL … /* BAR setup/limit/base address registers (DWORD) */ #define IDT_SW_NTP20_BARSETUP0 … #define IDT_SW_NTP20_BARLIMIT0 … #define IDT_SW_NTP20_BARLTBASE0 … #define IDT_SW_NTP20_BARUTBASE0 … #define IDT_SW_NTP20_BARSETUP1 … #define IDT_SW_NTP20_BARLIMIT1 … #define IDT_SW_NTP20_BARLTBASE1 … #define IDT_SW_NTP20_BARUTBASE1 … #define IDT_SW_NTP20_BARSETUP2 … #define IDT_SW_NTP20_BARLIMIT2 … #define IDT_SW_NTP20_BARLTBASE2 … #define IDT_SW_NTP20_BARUTBASE2 … #define IDT_SW_NTP20_BARSETUP3 … #define IDT_SW_NTP20_BARLIMIT3 … #define IDT_SW_NTP20_BARLTBASE3 … #define IDT_SW_NTP20_BARUTBASE3 … #define IDT_SW_NTP20_BARSETUP4 … #define IDT_SW_NTP20_BARLIMIT4 … #define IDT_SW_NTP20_BARLTBASE4 … #define IDT_SW_NTP20_BARUTBASE4 … #define IDT_SW_NTP20_BARSETUP5 … #define IDT_SW_NTP20_BARLIMIT5 … #define IDT_SW_NTP20_BARLTBASE5 … #define IDT_SW_NTP20_BARUTBASE5 … /* IDT PCIe-switch control register (DWORD) */ #define IDT_SW_CTL … /* Boot Configuration Vector Status (DWORD) */ #define IDT_SW_BCVSTS … /* Port Clocking Mode (DWORD) */ #define IDT_SW_PCLKMODE … /* Reset Drain Delay (DWORD) */ #define IDT_SW_RDRAINDELAY … /* Port Operating Mode Change Drain Delay (DWORD) */ #define IDT_SW_POMCDELAY … /* Side Effect Delay (DWORD) */ #define IDT_SW_SEDELAY … /* Upstream Secondary Bus Reset Delay (DWORD) */ #define IDT_SW_SSBRDELAY … /* Switch partition N Control/Status/Failover registers */ #define IDT_SW_SWPART0CTL … #define IDT_SW_SWPART0STS … #define IDT_SW_SWPART0FCTL … #define IDT_SW_SWPART1CTL … #define IDT_SW_SWPART1STS … #define IDT_SW_SWPART1FCTL … #define IDT_SW_SWPART2CTL … #define IDT_SW_SWPART2STS … #define IDT_SW_SWPART2FCTL … #define IDT_SW_SWPART3CTL … #define IDT_SW_SWPART3STS … #define IDT_SW_SWPART3FCTL … #define IDT_SW_SWPART4CTL … #define IDT_SW_SWPART4STS … #define IDT_SW_SWPART4FCTL … #define IDT_SW_SWPART5CTL … #define IDT_SW_SWPART5STS … #define IDT_SW_SWPART5FCTL … #define IDT_SW_SWPART6CTL … #define IDT_SW_SWPART6STS … #define IDT_SW_SWPART6FCTL … #define IDT_SW_SWPART7CTL … #define IDT_SW_SWPART7STS … #define IDT_SW_SWPART7FCTL … /* Switch port N control and status registers */ #define IDT_SW_SWPORT0CTL … #define IDT_SW_SWPORT0STS … #define IDT_SW_SWPORT0FCTL … #define IDT_SW_SWPORT2CTL … #define IDT_SW_SWPORT2STS … #define IDT_SW_SWPORT2FCTL … #define IDT_SW_SWPORT4CTL … #define IDT_SW_SWPORT4STS … #define IDT_SW_SWPORT4FCTL … #define IDT_SW_SWPORT6CTL … #define IDT_SW_SWPORT6STS … #define IDT_SW_SWPORT6FCTL … #define IDT_SW_SWPORT8CTL … #define IDT_SW_SWPORT8STS … #define IDT_SW_SWPORT8FCTL … #define IDT_SW_SWPORT12CTL … #define IDT_SW_SWPORT12STS … #define IDT_SW_SWPORT12FCTL … #define IDT_SW_SWPORT16CTL … #define IDT_SW_SWPORT16STS … #define IDT_SW_SWPORT16FCTL … #define IDT_SW_SWPORT20CTL … #define IDT_SW_SWPORT20STS … #define IDT_SW_SWPORT20FCTL … /* Switch Event registers */ /* Switch Event Status/Mask/Partition mask (DWORD) */ #define IDT_SW_SESTS … #define IDT_SW_SEMSK … #define IDT_SW_SEPMSK … /* Switch Event Link Up/Down Status/Mask (DWORD) */ #define IDT_SW_SELINKUPSTS … #define IDT_SW_SELINKUPMSK … #define IDT_SW_SELINKDNSTS … #define IDT_SW_SELINKDNMSK … /* Switch Event Fundamental Reset Status/Mask (DWORD) */ #define IDT_SW_SEFRSTSTS … #define IDT_SW_SEFRSTMSK … /* Switch Event Hot Reset Status/Mask (DWORD) */ #define IDT_SW_SEHRSTSTS … #define IDT_SW_SEHRSTMSK … /* Switch Event Failover Mask (DWORD) */ #define IDT_SW_SEFOVRMSK … /* Switch Event Global Signal Status/Mask (DWORD) */ #define IDT_SW_SEGSIGSTS … #define IDT_SW_SEGSIGMSK … /* NT Global Doorbell Status (DWORD) */ #define IDT_SW_GDBELLSTS … /* Switch partition N message M control (msgs routing table) (DWORD) */ #define IDT_SW_SWP0MSGCTL0 … #define IDT_SW_SWP1MSGCTL0 … #define IDT_SW_SWP2MSGCTL0 … #define IDT_SW_SWP3MSGCTL0 … #define IDT_SW_SWP4MSGCTL0 … #define IDT_SW_SWP5MSGCTL0 … #define IDT_SW_SWP6MSGCTL0 … #define IDT_SW_SWP7MSGCTL0 … #define IDT_SW_SWP0MSGCTL1 … #define IDT_SW_SWP1MSGCTL1 … #define IDT_SW_SWP2MSGCTL1 … #define IDT_SW_SWP3MSGCTL1 … #define IDT_SW_SWP4MSGCTL1 … #define IDT_SW_SWP5MSGCTL1 … #define IDT_SW_SWP6MSGCTL1 … #define IDT_SW_SWP7MSGCTL1 … #define IDT_SW_SWP0MSGCTL2 … #define IDT_SW_SWP1MSGCTL2 … #define IDT_SW_SWP2MSGCTL2 … #define IDT_SW_SWP3MSGCTL2 … #define IDT_SW_SWP4MSGCTL2 … #define IDT_SW_SWP5MSGCTL2 … #define IDT_SW_SWP6MSGCTL2 … #define IDT_SW_SWP7MSGCTL2 … #define IDT_SW_SWP0MSGCTL3 … #define IDT_SW_SWP1MSGCTL3 … #define IDT_SW_SWP2MSGCTL3 … #define IDT_SW_SWP3MSGCTL3 … #define IDT_SW_SWP4MSGCTL3 … #define IDT_SW_SWP5MSGCTL3 … #define IDT_SW_SWP6MSGCTL3 … #define IDT_SW_SWP7MSGCTL3 … /* SMBus Status and Control registers (DWORD) */ #define IDT_SW_SMBUSSTS … #define IDT_SW_SMBUSCTL … /* Serial EEPROM Interface (DWORD) */ #define IDT_SW_EEPROMINTF … /* MBus I/O Expander Address N (DWORD) */ #define IDT_SW_IOEXPADDR0 … #define IDT_SW_IOEXPADDR1 … #define IDT_SW_IOEXPADDR2 … #define IDT_SW_IOEXPADDR3 … #define IDT_SW_IOEXPADDR4 … #define IDT_SW_IOEXPADDR5 … /* General Purpose Events Control and Status registers (DWORD) */ #define IDT_SW_GPECTL … #define IDT_SW_GPESTS … /* Temperature sensor Control/Status/Alarm/Adjustment/Slope registers */ #define IDT_SW_TMPCTL … #define IDT_SW_TMPSTS … #define IDT_SW_TMPALARM … #define IDT_SW_TMPADJ … #define IDT_SW_TSSLOPE … /* SMBus Configuration Block header log (DWORD) */ #define IDT_SW_SMBUSCBHL … /* * Common registers related constants * @IDT_REG_ALIGN: Registers alignment used in the driver * @IDT_REG_PCI_MAX: Maximum PCI configuration space register value * @IDT_REG_SW_MAX: Maximum global register value */ #define IDT_REG_ALIGN … #define IDT_REG_PCI_MAX … #define IDT_REG_SW_MAX … /* * PCICMDSTS register fields related constants * @IDT_PCICMDSTS_IOAE: I/O access enable * @IDT_PCICMDSTS_MAE: Memory access enable * @IDT_PCICMDSTS_BME: Bus master enable */ #define IDT_PCICMDSTS_IOAE … #define IDT_PCICMDSTS_MAE … #define IDT_PCICMDSTS_BME … /* * PCIEDCAP register fields related constants * @IDT_PCIEDCAP_MPAYLOAD_MASK: Maximum payload size mask * @IDT_PCIEDCAP_MPAYLOAD_FLD: Maximum payload size field offset * @IDT_PCIEDCAP_MPAYLOAD_S128: Max supported payload size of 128 bytes * @IDT_PCIEDCAP_MPAYLOAD_S256: Max supported payload size of 256 bytes * @IDT_PCIEDCAP_MPAYLOAD_S512: Max supported payload size of 512 bytes * @IDT_PCIEDCAP_MPAYLOAD_S1024: Max supported payload size of 1024 bytes * @IDT_PCIEDCAP_MPAYLOAD_S2048: Max supported payload size of 2048 bytes */ #define IDT_PCIEDCAP_MPAYLOAD_MASK … #define IDT_PCIEDCAP_MPAYLOAD_FLD … #define IDT_PCIEDCAP_MPAYLOAD_S128 … #define IDT_PCIEDCAP_MPAYLOAD_S256 … #define IDT_PCIEDCAP_MPAYLOAD_S512 … #define IDT_PCIEDCAP_MPAYLOAD_S1024 … #define IDT_PCIEDCAP_MPAYLOAD_S2048 … /* * PCIEDCTLSTS registers fields related constants * @IDT_PCIEDCTL_MPS_MASK: Maximum payload size mask * @IDT_PCIEDCTL_MPS_FLD: MPS field offset * @IDT_PCIEDCTL_MPS_S128: Max payload size of 128 bytes * @IDT_PCIEDCTL_MPS_S256: Max payload size of 256 bytes * @IDT_PCIEDCTL_MPS_S512: Max payload size of 512 bytes * @IDT_PCIEDCTL_MPS_S1024: Max payload size of 1024 bytes * @IDT_PCIEDCTL_MPS_S2048: Max payload size of 2048 bytes * @IDT_PCIEDCTL_MPS_S4096: Max payload size of 4096 bytes */ #define IDT_PCIEDCTLSTS_MPS_MASK … #define IDT_PCIEDCTLSTS_MPS_FLD … #define IDT_PCIEDCTLSTS_MPS_S128 … #define IDT_PCIEDCTLSTS_MPS_S256 … #define IDT_PCIEDCTLSTS_MPS_S512 … #define IDT_PCIEDCTLSTS_MPS_S1024 … #define IDT_PCIEDCTLSTS_MPS_S2048 … #define IDT_PCIEDCTLSTS_MPS_S4096 … /* * PCIELCAP register fields related constants * @IDT_PCIELCAP_PORTNUM_MASK: Port number field mask * @IDT_PCIELCAP_PORTNUM_FLD: Port number field offset */ #define IDT_PCIELCAP_PORTNUM_MASK … #define IDT_PCIELCAP_PORTNUM_FLD … /* * PCIELCTLSTS registers fields related constants * @IDT_PCIELSTS_CLS_MASK: Current link speed mask * @IDT_PCIELSTS_CLS_FLD: Current link speed field offset * @IDT_PCIELSTS_NLW_MASK: Negotiated link width mask * @IDT_PCIELSTS_NLW_FLD: Negotiated link width field offset * @IDT_PCIELSTS_SCLK_COM: Common slot clock configuration */ #define IDT_PCIELCTLSTS_CLS_MASK … #define IDT_PCIELCTLSTS_CLS_FLD … #define IDT_PCIELCTLSTS_NLW_MASK … #define IDT_PCIELCTLSTS_NLW_FLD … #define IDT_PCIELCTLSTS_SCLK_COM … /* * NTCTL register fields related constants * @IDT_NTCTL_IDPROTDIS: ID Protection check disable (disable MTBL) * @IDT_NTCTL_CPEN: Completion enable * @IDT_NTCTL_RNS: Request no snoop processing (if MTBL disabled) * @IDT_NTCTL_ATP: Address type processing (if MTBL disabled) */ #define IDT_NTCTL_IDPROTDIS … #define IDT_NTCTL_CPEN … #define IDT_NTCTL_RNS … #define IDT_NTCTL_ATP … /* * NTINTSTS register fields related constants * @IDT_NTINTSTS_MSG: Message interrupt bit * @IDT_NTINTSTS_DBELL: Doorbell interrupt bit * @IDT_NTINTSTS_SEVENT: Switch Event interrupt bit * @IDT_NTINTSTS_TMPSENSOR: Temperature sensor interrupt bit */ #define IDT_NTINTSTS_MSG … #define IDT_NTINTSTS_DBELL … #define IDT_NTINTSTS_SEVENT … #define IDT_NTINTSTS_TMPSENSOR … /* * NTINTMSK register fields related constants * @IDT_NTINTMSK_MSG: Message interrupt mask bit * @IDT_NTINTMSK_DBELL: Doorbell interrupt mask bit * @IDT_NTINTMSK_SEVENT: Switch Event interrupt mask bit * @IDT_NTINTMSK_TMPSENSOR: Temperature sensor interrupt mask bit * @IDT_NTINTMSK_ALL: NTB-related interrupts mask */ #define IDT_NTINTMSK_MSG … #define IDT_NTINTMSK_DBELL … #define IDT_NTINTMSK_SEVENT … #define IDT_NTINTMSK_TMPSENSOR … #define IDT_NTINTMSK_ALL … /* * NTGSIGNAL register fields related constants * @IDT_NTGSIGNAL_SET: Set global signal of the local partition */ #define IDT_NTGSIGNAL_SET … /* * BARSETUP register fields related constants * @IDT_BARSETUP_TYPE_MASK: Mask of the TYPE field * @IDT_BARSETUP_TYPE_32: 32-bit addressing BAR * @IDT_BARSETUP_TYPE_64: 64-bit addressing BAR * @IDT_BARSETUP_PREF: Value of the BAR prefetchable field * @IDT_BARSETUP_SIZE_MASK: Mask of the SIZE field * @IDT_BARSETUP_SIZE_FLD: SIZE field offset * @IDT_BARSETUP_SIZE_CFG: SIZE field value in case of config space MODE * @IDT_BARSETUP_MODE_CFG: Configuration space BAR mode * @IDT_BARSETUP_ATRAN_MASK: ATRAN field mask * @IDT_BARSETUP_ATRAN_FLD: ATRAN field offset * @IDT_BARSETUP_ATRAN_DIR: Direct address translation memory window * @IDT_BARSETUP_ATRAN_LUT12: 12-entry lookup table * @IDT_BARSETUP_ATRAN_LUT24: 24-entry lookup table * @IDT_BARSETUP_TPART_MASK: TPART field mask * @IDT_BARSETUP_TPART_FLD: TPART field offset * @IDT_BARSETUP_EN: BAR enable bit */ #define IDT_BARSETUP_TYPE_MASK … #define IDT_BARSETUP_TYPE_FLD … #define IDT_BARSETUP_TYPE_32 … #define IDT_BARSETUP_TYPE_64 … #define IDT_BARSETUP_PREF … #define IDT_BARSETUP_SIZE_MASK … #define IDT_BARSETUP_SIZE_FLD … #define IDT_BARSETUP_SIZE_CFG … #define IDT_BARSETUP_MODE_CFG … #define IDT_BARSETUP_ATRAN_MASK … #define IDT_BARSETUP_ATRAN_FLD … #define IDT_BARSETUP_ATRAN_DIR … #define IDT_BARSETUP_ATRAN_LUT12 … #define IDT_BARSETUP_ATRAN_LUT24 … #define IDT_BARSETUP_TPART_MASK … #define IDT_BARSETUP_TPART_FLD … #define IDT_BARSETUP_EN … /* * NTMTBLDATA register fields related constants * @IDT_NTMTBLDATA_VALID: Set the MTBL entry being valid * @IDT_NTMTBLDATA_REQID_MASK: Bus:Device:Function field mask * @IDT_NTMTBLDATA_REQID_FLD: Bus:Device:Function field offset * @IDT_NTMTBLDATA_PART_MASK: Partition field mask * @IDT_NTMTBLDATA_PART_FLD: Partition field offset * @IDT_NTMTBLDATA_ATP_TRANS: Enable AT field translation on request TLPs * @IDT_NTMTBLDATA_CNS_INV: Enable No Snoop attribute inversion of * Completion TLPs * @IDT_NTMTBLDATA_RNS_INV: Enable No Snoop attribute inversion of * Request TLPs */ #define IDT_NTMTBLDATA_VALID … #define IDT_NTMTBLDATA_REQID_MASK … #define IDT_NTMTBLDATA_REQID_FLD … #define IDT_NTMTBLDATA_PART_MASK … #define IDT_NTMTBLDATA_PART_FLD … #define IDT_NTMTBLDATA_ATP_TRANS … #define IDT_NTMTBLDATA_CNS_INV … #define IDT_NTMTBLDATA_RNS_INV … /* * REQIDCAP register fields related constants * @IDT_REQIDCAP_REQID_MASK: Request ID field mask * @IDT_REQIDCAP_REQID_FLD: Request ID field offset */ #define IDT_REQIDCAP_REQID_MASK … #define IDT_REQIDCAP_REQID_FLD … /* * LUTOFFSET register fields related constants * @IDT_LUTOFFSET_INDEX_MASK: Lookup table index field mask * @IDT_LUTOFFSET_INDEX_FLD: Lookup table index field offset * @IDT_LUTOFFSET_BAR_MASK: Lookup table BAR select field mask * @IDT_LUTOFFSET_BAR_FLD: Lookup table BAR select field offset */ #define IDT_LUTOFFSET_INDEX_MASK … #define IDT_LUTOFFSET_INDEX_FLD … #define IDT_LUTOFFSET_BAR_MASK … #define IDT_LUTOFFSET_BAR_FLD … /* * LUTUDATA register fields related constants * @IDT_LUTUDATA_PART_MASK: Partition field mask * @IDT_LUTUDATA_PART_FLD: Partition field offset * @IDT_LUTUDATA_VALID: Lookup table entry valid bit */ #define IDT_LUTUDATA_PART_MASK … #define IDT_LUTUDATA_PART_FLD … #define IDT_LUTUDATA_VALID … /* * SWPARTxSTS register fields related constants * @IDT_SWPARTxSTS_SCI: Switch partition state change initiated * @IDT_SWPARTxSTS_SCC: Switch partition state change completed * @IDT_SWPARTxSTS_STATE_MASK: Switch partition state mask * @IDT_SWPARTxSTS_STATE_FLD: Switch partition state field offset * @IDT_SWPARTxSTS_STATE_DIS: Switch partition disabled * @IDT_SWPARTxSTS_STATE_ACT: Switch partition enabled * @IDT_SWPARTxSTS_STATE_RES: Switch partition in reset * @IDT_SWPARTxSTS_US: Switch partition has upstream port * @IDT_SWPARTxSTS_USID_MASK: Switch partition upstream port ID mask * @IDT_SWPARTxSTS_USID_FLD: Switch partition upstream port ID field offset * @IDT_SWPARTxSTS_NT: Upstream port has NT function * @IDT_SWPARTxSTS_DMA: Upstream port has DMA function */ #define IDT_SWPARTxSTS_SCI … #define IDT_SWPARTxSTS_SCC … #define IDT_SWPARTxSTS_STATE_MASK … #define IDT_SWPARTxSTS_STATE_FLD … #define IDT_SWPARTxSTS_STATE_DIS … #define IDT_SWPARTxSTS_STATE_ACT … #define IDT_SWPARTxSTS_STATE_RES … #define IDT_SWPARTxSTS_US … #define IDT_SWPARTxSTS_USID_MASK … #define IDT_SWPARTxSTS_USID_FLD … #define IDT_SWPARTxSTS_NT … #define IDT_SWPARTxSTS_DMA … /* * SWPORTxSTS register fields related constants * @IDT_SWPORTxSTS_OMCI: Operation mode change initiated * @IDT_SWPORTxSTS_OMCC: Operation mode change completed * @IDT_SWPORTxSTS_LINKUP: Link up status * @IDT_SWPORTxSTS_DS: Port lanes behave as downstream lanes * @IDT_SWPORTxSTS_MODE_MASK: Port mode field mask * @IDT_SWPORTxSTS_MODE_FLD: Port mode field offset * @IDT_SWPORTxSTS_MODE_DIS: Port mode - disabled * @IDT_SWPORTxSTS_MODE_DS: Port mode - downstream switch port * @IDT_SWPORTxSTS_MODE_US: Port mode - upstream switch port * @IDT_SWPORTxSTS_MODE_NT: Port mode - NT function * @IDT_SWPORTxSTS_MODE_USNT: Port mode - upstream switch port with NTB * @IDT_SWPORTxSTS_MODE_UNAT: Port mode - unattached * @IDT_SWPORTxSTS_MODE_USDMA: Port mode - upstream switch port with DMA * @IDT_SWPORTxSTS_MODE_USNTDMA:Port mode - upstream port with NTB and DMA * @IDT_SWPORTxSTS_MODE_NTDMA: Port mode - NT function with DMA * @IDT_SWPORTxSTS_SWPART_MASK: Port partition field mask * @IDT_SWPORTxSTS_SWPART_FLD: Port partition field offset * @IDT_SWPORTxSTS_DEVNUM_MASK: Port device number field mask * @IDT_SWPORTxSTS_DEVNUM_FLD: Port device number field offset */ #define IDT_SWPORTxSTS_OMCI … #define IDT_SWPORTxSTS_OMCC … #define IDT_SWPORTxSTS_LINKUP … #define IDT_SWPORTxSTS_DS … #define IDT_SWPORTxSTS_MODE_MASK … #define IDT_SWPORTxSTS_MODE_FLD … #define IDT_SWPORTxSTS_MODE_DIS … #define IDT_SWPORTxSTS_MODE_DS … #define IDT_SWPORTxSTS_MODE_US … #define IDT_SWPORTxSTS_MODE_NT … #define IDT_SWPORTxSTS_MODE_USNT … #define IDT_SWPORTxSTS_MODE_UNAT … #define IDT_SWPORTxSTS_MODE_USDMA … #define IDT_SWPORTxSTS_MODE_USNTDMA … #define IDT_SWPORTxSTS_MODE_NTDMA … #define IDT_SWPORTxSTS_SWPART_MASK … #define IDT_SWPORTxSTS_SWPART_FLD … #define IDT_SWPORTxSTS_DEVNUM_MASK … #define IDT_SWPORTxSTS_DEVNUM_FLD … /* * SEMSK register fields related constants * @IDT_SEMSK_LINKUP: Link Up event mask bit * @IDT_SEMSK_LINKDN: Link Down event mask bit * @IDT_SEMSK_GSIGNAL: Global Signal event mask bit */ #define IDT_SEMSK_LINKUP … #define IDT_SEMSK_LINKDN … #define IDT_SEMSK_GSIGNAL … /* * SWPxMSGCTL register fields related constants * @IDT_SWPxMSGCTL_REG_MASK: Register select field mask * @IDT_SWPxMSGCTL_REG_FLD: Register select field offset * @IDT_SWPxMSGCTL_PART_MASK: Partition select field mask * @IDT_SWPxMSGCTL_PART_FLD: Partition select field offset */ #define IDT_SWPxMSGCTL_REG_MASK … #define IDT_SWPxMSGCTL_REG_FLD … #define IDT_SWPxMSGCTL_PART_MASK … #define IDT_SWPxMSGCTL_PART_FLD … /* * TMPCTL register fields related constants * @IDT_TMPCTL_LTH_MASK: Low temperature threshold field mask * @IDT_TMPCTL_LTH_FLD: Low temperature threshold field offset * @IDT_TMPCTL_MTH_MASK: Middle temperature threshold field mask * @IDT_TMPCTL_MTH_FLD: Middle temperature threshold field offset * @IDT_TMPCTL_HTH_MASK: High temperature threshold field mask * @IDT_TMPCTL_HTH_FLD: High temperature threshold field offset * @IDT_TMPCTL_PDOWN: Temperature sensor power down */ #define IDT_TMPCTL_LTH_MASK … #define IDT_TMPCTL_LTH_FLD … #define IDT_TMPCTL_MTH_MASK … #define IDT_TMPCTL_MTH_FLD … #define IDT_TMPCTL_HTH_MASK … #define IDT_TMPCTL_HTH_FLD … #define IDT_TMPCTL_PDOWN … /* * TMPSTS register fields related constants * @IDT_TMPSTS_TEMP_MASK: Current temperature field mask * @IDT_TMPSTS_TEMP_FLD: Current temperature field offset * @IDT_TMPSTS_LTEMP_MASK: Lowest temperature field mask * @IDT_TMPSTS_LTEMP_FLD: Lowest temperature field offset * @IDT_TMPSTS_HTEMP_MASK: Highest temperature field mask * @IDT_TMPSTS_HTEMP_FLD: Highest temperature field offset */ #define IDT_TMPSTS_TEMP_MASK … #define IDT_TMPSTS_TEMP_FLD … #define IDT_TMPSTS_LTEMP_MASK … #define IDT_TMPSTS_LTEMP_FLD … #define IDT_TMPSTS_HTEMP_MASK … #define IDT_TMPSTS_HTEMP_FLD … /* * TMPALARM register fields related constants * @IDT_TMPALARM_LTEMP_MASK: Lowest temperature field mask * @IDT_TMPALARM_LTEMP_FLD: Lowest temperature field offset * @IDT_TMPALARM_HTEMP_MASK: Highest temperature field mask * @IDT_TMPALARM_HTEMP_FLD: Highest temperature field offset * @IDT_TMPALARM_IRQ_MASK: Alarm IRQ status mask */ #define IDT_TMPALARM_LTEMP_MASK … #define IDT_TMPALARM_LTEMP_FLD … #define IDT_TMPALARM_HTEMP_MASK … #define IDT_TMPALARM_HTEMP_FLD … #define IDT_TMPALARM_IRQ_MASK … /* * TMPADJ register fields related constants * @IDT_TMPADJ_OFFSET_MASK: Temperature value offset field mask * @IDT_TMPADJ_OFFSET_FLD: Temperature value offset field offset */ #define IDT_TMPADJ_OFFSET_MASK … #define IDT_TMPADJ_OFFSET_FLD … /* * Helper macro to get/set the corresponding field value * @GET_FIELD: Retrieve the value of the corresponding field * @SET_FIELD: Set the specified field up * @IS_FLD_SET: Check whether a field is set with value */ #define GET_FIELD(field, data) … #define SET_FIELD(field, data, value) … #define IS_FLD_SET(field, data, value) … /* * Useful registers masks: * @IDT_DBELL_MASK: Doorbell bits mask * @IDT_OUTMSG_MASK: Out messages status bits mask * @IDT_INMSG_MASK: In messages status bits mask * @IDT_MSG_MASK: Any message status bits mask */ #define IDT_DBELL_MASK … #define IDT_OUTMSG_MASK … #define IDT_INMSG_MASK … #define IDT_MSG_MASK … /* * Number of IDT NTB resources: * @IDT_MSG_CNT: Number of Message registers * @IDT_BAR_CNT: Number of BARs of each port * @IDT_MTBL_ENTRY_CNT: Number mapping table entries */ #define IDT_MSG_CNT … #define IDT_BAR_CNT … #define IDT_MTBL_ENTRY_CNT … /* * General IDT PCIe-switch constant * @IDT_MAX_NR_PORTS: Maximum number of ports per IDT PCIe-switch * @IDT_MAX_NR_PARTS: Maximum number of partitions per IDT PCIe-switch * @IDT_MAX_NR_PEERS: Maximum number of NT-peers per IDT PCIe-switch * @IDT_MAX_NR_MWS: Maximum number of Memory Widows * @IDT_PCIE_REGSIZE: Size of the registers in bytes * @IDT_TRANS_ALIGN: Alignment of translated base address * @IDT_DIR_SIZE_ALIGN: Alignment of size setting for direct translated MWs. * Even though the lower 10 bits are reserved, they are * treated by IDT as one's so basically there is no any * alignment of size limit for DIR address translation. */ #define IDT_MAX_NR_PORTS … #define IDT_MAX_NR_PARTS … #define IDT_MAX_NR_PEERS … #define IDT_MAX_NR_MWS … #define IDT_PCIE_REGSIZE … #define IDT_TRANS_ALIGN … #define IDT_DIR_SIZE_ALIGN … /* * IDT PCIe-switch temperature sensor value limits * @IDT_TEMP_MIN_MDEG: Minimal integer value of temperature * @IDT_TEMP_MAX_MDEG: Maximal integer value of temperature * @IDT_TEMP_MIN_OFFSET:Minimal integer value of temperature offset * @IDT_TEMP_MAX_OFFSET:Maximal integer value of temperature offset */ #define IDT_TEMP_MIN_MDEG … #define IDT_TEMP_MAX_MDEG … #define IDT_TEMP_MIN_OFFSET … #define IDT_TEMP_MAX_OFFSET … /* * Temperature sensor values enumeration * @IDT_TEMP_CUR: Current temperature * @IDT_TEMP_LOW: Lowest historical temperature * @IDT_TEMP_HIGH: Highest historical temperature * @IDT_TEMP_OFFSET: Current temperature offset */ enum idt_temp_val { … }; /* * IDT Memory Windows type. Depending on the device settings, IDT supports * Direct Address Translation MW registers and Lookup Table registers * @IDT_MW_DIR: Direct address translation * @IDT_MW_LUT12: 12-entry lookup table entry * @IDT_MW_LUT24: 24-entry lookup table entry * * NOTE These values are exactly the same as one of the BARSETUP ATRAN field */ enum idt_mw_type { … }; /* * IDT PCIe-switch model private data * @name: Device name * @port_cnt: Total number of NT endpoint ports * @ports: Port ids */ struct idt_89hpes_cfg { … }; /* * Memory window configuration structure * @type: Type of the memory window (direct address translation or lookup * table) * * @bar: PCIe BAR the memory window referenced to * @idx: Index of the memory window within the BAR * * @addr_align: Alignment of translated address * @size_align: Alignment of memory window size * @size_max: Maximum size of memory window */ struct idt_mw_cfg { … }; /* * Description structure of peer IDT NT-functions: * @port: NT-function port * @part: NT-function partition * * @mw_cnt: Number of memory windows supported by NT-function * @mws: Array of memory windows descriptors */ struct idt_ntb_peer { … }; /* * Description structure of local IDT NT-function: * @ntb: Linux NTB-device description structure * @swcfg: Pointer to the structure of local IDT PCIe-switch * specific cofnfigurations * * @port: Local NT-function port * @part: Local NT-function partition * * @peer_cnt: Number of peers with activated NTB-function * @peers: Array of peers descripting structures * @port_idx_map: Map of port number -> peer index * @part_idx_map: Map of partition number -> peer index * * @mtbl_lock: Mapping table access lock * * @mw_cnt: Number of memory windows supported by NT-function * @mws: Array of memory windows descriptors * @lut_lock: Lookup table access lock * * @msg_locks: Message registers mapping table lockers * * @cfgspc: Virtual address of the memory mapped configuration * space of the NT-function * @db_mask_lock: Doorbell mask register lock * @msg_mask_lock: Message mask register lock * @gasa_lock: GASA registers access lock * * @hwmon_mtx: Temperature sensor interface update mutex * * @dbgfs_info: DebugFS info node */ struct idt_ntb_dev { … }; #define to_ndev_ntb(__ntb) … /* * Descriptor of the IDT PCIe-switch BAR resources * @setup: BAR setup register * @limit: BAR limit register * @ltbase: Lower translated base address * @utbase: Upper translated base address */ struct idt_ntb_bar { … }; /* * Descriptor of the IDT PCIe-switch message resources * @in: Inbound message register * @out: Outbound message register * @src: Source of inbound message register */ struct idt_ntb_msg { … }; /* * Descriptor of the IDT PCIe-switch NT-function specific parameters in the * PCI Configuration Space * @bars: BARs related registers * @msgs: Messaging related registers */ struct idt_ntb_regs { … }; /* * Descriptor of the IDT PCIe-switch port specific parameters in the * Global Configuration Space * @pcicmdsts: PCI command/status register * @pcielctlsts: PCIe link control/status * * @ctl: Port control register * @sts: Port status register * * @bars: BARs related registers */ struct idt_ntb_port { … }; /* * Descriptor of the IDT PCIe-switch partition specific parameters. * @ctl: Partition control register in the Global Address Space * @sts: Partition status register in the Global Address Space * @msgctl: Messages control registers */ struct idt_ntb_part { … }; #endif /* NTB_HW_IDT_H */
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