/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2020-2023 HabanaLabs, Ltd. * All Rights Reserved. * */ #ifndef CPUCP_IF_H #define CPUCP_IF_H #include <linux/types.h> #include <linux/if_ether.h> #include "hl_boot_if.h" #define NUM_HBM_PSEUDO_CH … #define NUM_HBM_CH_PER_DEV … #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK … #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK … #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK … #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK … #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK … #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK … #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT … #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK … #define PLL_MAP_MAX_BITS … #define PLL_MAP_LEN … enum eq_event_id { … }; /* * info of the pkt queue pointers in the first async occurrence */ struct cpucp_pkt_sync_err { … }; struct hl_eq_hbm_ecc_data { … }; /* * EVENT QUEUE */ struct hl_eq_header { … }; struct hl_eq_ecc_data { … }; enum hl_sm_sei_cause { … }; struct hl_eq_sm_sei_data { … }; enum hl_fw_alive_severity { … }; struct hl_eq_fw_alive { … }; struct hl_eq_intr_cause { … }; struct hl_eq_pcie_drain_ind_data { … }; struct hl_eq_razwi_lbw_info_regs { … }; struct hl_eq_razwi_hbw_info_regs { … }; /* razwi_happened masks */ #define RAZWI_HAPPENED_HBW … #define RAZWI_HAPPENED_LBW … #define RAZWI_HAPPENED_AW … #define RAZWI_HAPPENED_AR … struct hl_eq_razwi_info { … }; struct hl_eq_razwi_with_intr_cause { … }; #define HBM_CA_ERR_CMD_LIFO_LEN … #define HBM_RD_ERR_DATA_LIFO_LEN … #define HBM_WR_PAR_CMD_LIFO_LEN … enum hl_hbm_sei_cause { … }; /* Masks for parsing hl_hbm_sei_headr fields */ #define HBM_ECC_SERR_CNTR_MASK … #define HBM_ECC_DERR_CNTR_MASK … #define HBM_RD_PARITY_CNTR_MASK … /* HBM index and MC index are known by the event_id */ struct hl_hbm_sei_header { … }; #define HBM_RD_ADDR_SID_SHIFT … #define HBM_RD_ADDR_SID_MASK … #define HBM_RD_ADDR_BG_SHIFT … #define HBM_RD_ADDR_BG_MASK … #define HBM_RD_ADDR_BA_SHIFT … #define HBM_RD_ADDR_BA_MASK … #define HBM_RD_ADDR_COL_SHIFT … #define HBM_RD_ADDR_COL_MASK … #define HBM_RD_ADDR_ROW_SHIFT … #define HBM_RD_ADDR_ROW_MASK … struct hbm_rd_addr { … }; #define HBM_RD_ERR_BEAT_SHIFT … /* dbg_rd_err_misc fields: */ /* Read parity is calculated per DW on every beat */ #define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT … #define HBM_RD_ERR_PAR_ERR_BEAT0_MASK … #define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT … #define HBM_RD_ERR_PAR_DATA_BEAT0_MASK … /* ECC is calculated per PC on every beat */ #define HBM_RD_ERR_SERR_BEAT0_SHIFT … #define HBM_RD_ERR_SERR_BEAT0_MASK … #define HBM_RD_ERR_DERR_BEAT0_SHIFT … #define HBM_RD_ERR_DERR_BEAT0_MASK … struct hl_eq_hbm_sei_read_err_intr_info { … }; struct hl_eq_hbm_sei_ca_par_intr_info { … }; #define WR_PAR_LAST_CMD_COL_SHIFT … #define WR_PAR_LAST_CMD_COL_MASK … #define WR_PAR_LAST_CMD_BG_SHIFT … #define WR_PAR_LAST_CMD_BG_MASK … #define WR_PAR_LAST_CMD_BA_SHIFT … #define WR_PAR_LAST_CMD_BA_MASK … #define WR_PAR_LAST_CMD_SID_SHIFT … #define WR_PAR_LAST_CMD_SID_MASK … /* Row address isn't latched */ struct hbm_sei_wr_cmd_address { … }; struct hl_eq_hbm_sei_wr_par_intr_info { … }; /* * this struct represents the following sei causes: * command parity, ECC double error, ECC single error, dfi error, cattrip, * temperature read-out, read parity error and write parity error. * some only use the header while some have extra data. */ struct hl_eq_hbm_sei_data { … }; /* Engine/farm arc interrupt type */ enum hl_engine_arc_interrupt_type { … }; /* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ struct hl_engine_arc_dccm_queue_full_irq { … }; /* Data structure specifies details of QM/FARM ARC interrupt */ struct hl_eq_engine_arc_intr_data { … }; #define ADDR_DEC_ADDRESS_COUNT_MAX … /* Data structure specifies details of ADDR_DEC interrupt */ struct hl_eq_addr_dec_intr_data { … }; struct hl_eq_entry { … }; #define HL_EQ_ENTRY_SIZE … #define EQ_CTL_READY_SHIFT … #define EQ_CTL_READY_MASK … #define EQ_CTL_EVENT_MODE_SHIFT … #define EQ_CTL_EVENT_MODE_MASK … #define EQ_CTL_EVENT_TYPE_SHIFT … #define EQ_CTL_EVENT_TYPE_MASK … #define EQ_CTL_INDEX_SHIFT … #define EQ_CTL_INDEX_MASK … enum pq_init_status { … }; /* * CpuCP Primary Queue Packets * * During normal operation, the host's kernel driver needs to send various * messages to CpuCP, usually either to SET some value into a H/W periphery or * to GET the current value of some H/W periphery. For example, SET the * frequency of MME/TPC and GET the value of the thermal sensor. * * These messages can be initiated either by the User application or by the * host's driver itself, e.g. power management code. In either case, the * communication from the host's driver to CpuCP will *always* be in * synchronous mode, meaning that the host will send a single message and poll * until the message was acknowledged and the results are ready (if results are * needed). * * This means that only a single message can be sent at a time and the host's * driver must wait for its result before sending the next message. Having said * that, because these are control messages which are sent in a relatively low * frequency, this limitation seems acceptable. It's important to note that * in case of multiple devices, messages to different devices *can* be sent * at the same time. * * The message, inputs/outputs (if relevant) and fence object will be located * on the device DDR at an address that will be determined by the host's driver. * During device initialization phase, the host will pass to CpuCP that address. * Most of the message types will contain inputs/outputs inside the message * itself. The common part of each message will contain the opcode of the * message (its type) and a field representing a fence object. * * When the host's driver wishes to send a message to CPU CP, it will write the * message contents to the device DDR, clear the fence object and then write to * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. * * Upon receiving the interrupt (#121), CpuCP will read the message from the * DDR. In case the message is a SET operation, CpuCP will first perform the * operation and then write to the fence object on the device DDR. In case the * message is a GET operation, CpuCP will first fill the results section on the * device DDR and then write to the fence object. If an error occurred, CpuCP * will fill the rc field with the right error code. * * In the meantime, the host's driver will poll on the fence object. Once the * host sees that the fence object is signaled, it will read the results from * the device DDR (if relevant) and resume the code execution in the host's * driver. * * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 * so the value being put by the host's driver matches the value read by CpuCP * * Non-QMAN packets should be limited to values 1 through (2^8 - 1) * * Detailed description: * * CPUCP_PACKET_DISABLE_PCI_ACCESS - * After receiving this packet the embedded CPU must NOT issue PCI * transactions (read/write) towards the Host CPU. This also include * sending MSI-X interrupts. * This packet is usually sent before the device is moved to D3Hot state. * * CPUCP_PACKET_ENABLE_PCI_ACCESS - * After receiving this packet the embedded CPU is allowed to issue PCI * transactions towards the Host CPU, including sending MSI-X interrupts. * This packet is usually send after the device is moved to D0 state. * * CPUCP_PACKET_TEMPERATURE_GET - * Fetch the current temperature / Max / Max Hyst / Critical / * Critical Hyst of a specified thermal sensor. The packet's * arguments specify the desired sensor and the field to get. * * CPUCP_PACKET_VOLTAGE_GET - * Fetch the voltage / Max / Min of a specified sensor. The packet's * arguments specify the sensor and type. * * CPUCP_PACKET_CURRENT_GET - * Fetch the current / Max / Min of a specified sensor. The packet's * arguments specify the sensor and type. * * CPUCP_PACKET_FAN_SPEED_GET - * Fetch the speed / Max / Min of a specified fan. The packet's * arguments specify the sensor and type. * * CPUCP_PACKET_PWM_GET - * Fetch the pwm value / mode of a specified pwm. The packet's * arguments specify the sensor and type. * * CPUCP_PACKET_PWM_SET - * Set the pwm value / mode of a specified pwm. The packet's * arguments specify the sensor, type and value. * * CPUCP_PACKET_FREQUENCY_SET - * Set the frequency of a specified PLL. The packet's arguments specify * the PLL and the desired frequency. The actual frequency in the device * might differ from the requested frequency. * * CPUCP_PACKET_FREQUENCY_GET - * Fetch the frequency of a specified PLL. The packet's arguments specify * the PLL. * * CPUCP_PACKET_LED_SET - * Set the state of a specified led. The packet's arguments * specify the led and the desired state. * * CPUCP_PACKET_I2C_WR - * Write 32-bit value to I2C device. The packet's arguments specify the * I2C bus, address and value. * * CPUCP_PACKET_I2C_RD - * Read 32-bit value from I2C device. The packet's arguments specify the * I2C bus and address. * * CPUCP_PACKET_INFO_GET - * Fetch information from the device as specified in the packet's * structure. The host's driver passes the max size it allows the CpuCP to * write to the structure, to prevent data corruption in case of * mismatched driver/FW versions. * * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed * * CPUCP_PACKET_UNMASK_RAZWI_IRQ - * Unmask the given IRQ. The IRQ number is specified in the value field. * The packet is sent after receiving an interrupt and printing its * relevant information. * * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - * Unmask the given IRQs. The IRQs numbers are specified in an array right * after the cpucp_packet structure, where its first element is the array * length. The packet is sent after a soft reset was done in order to * handle any interrupts that were sent during the reset process. * * CPUCP_PACKET_TEST - * Test packet for CpuCP connectivity. The CPU will put the fence value * in the result field. * * CPUCP_PACKET_FREQUENCY_CURR_GET - * Fetch the current frequency of a specified PLL. The packet's arguments * specify the PLL. * * CPUCP_PACKET_MAX_POWER_GET - * Fetch the maximal power of the device. * * CPUCP_PACKET_MAX_POWER_SET - * Set the maximal power of the device. The packet's arguments specify * the power. * * CPUCP_PACKET_EEPROM_DATA_GET - * Get EEPROM data from the CpuCP kernel. The buffer is specified in the * addr field. The CPU will put the returned data size in the result * field. In addition, the host's driver passes the max size it allows the * CpuCP to write to the structure, to prevent data corruption in case of * mismatched driver/FW versions. * * CPUCP_PACKET_NIC_INFO_GET - * Fetch information from the device regarding the NIC. the host's driver * passes the max size it allows the CpuCP to write to the structure, to * prevent data corruption in case of mismatched driver/FW versions. * * CPUCP_PACKET_TEMPERATURE_SET - * Set the value of the offset property of a specified thermal sensor. * The packet's arguments specify the desired sensor and the field to * set. * * CPUCP_PACKET_VOLTAGE_SET - * Trigger the reset_history property of a specified voltage sensor. * The packet's arguments specify the desired sensor and the field to * set. * * CPUCP_PACKET_CURRENT_SET - * Trigger the reset_history property of a specified current sensor. * The packet's arguments specify the desired sensor and the field to * set. * * CPUCP_PACKET_PCIE_THROUGHPUT_GET - * Get throughput of PCIe. * The packet's arguments specify the transaction direction (TX/RX). * The window measurement is 10[msec], and the return value is in KB/sec. * * CPUCP_PACKET_PCIE_REPLAY_CNT_GET * Replay count measures number of "replay" events, which is basicly * number of retries done by PCIe. * * CPUCP_PACKET_TOTAL_ENERGY_GET - * Total Energy is measurement of energy from the time FW Linux * is loaded. It is calculated by multiplying the average power * by time (passed from armcp start). The units are in MilliJouls. * * CPUCP_PACKET_PLL_INFO_GET - * Fetch frequencies of PLL from the required PLL IP. * The packet's arguments specify the device PLL type * Pll type is the PLL from device pll_index enum. * The result is composed of 4 outputs, each is 16-bit * frequency in MHz. * * CPUCP_PACKET_POWER_GET - * Fetch the present power consumption of the device (Current * Voltage). * * CPUCP_PACKET_NIC_PFC_SET - * Enable/Disable the NIC PFC feature. The packet's arguments specify the * NIC port, relevant lanes to configure and one bit indication for * enable/disable. * * CPUCP_PACKET_NIC_FAULT_GET - * Fetch the current indication for local/remote faults from the NIC MAC. * The result is 32-bit value of the relevant register. * * CPUCP_PACKET_NIC_LPBK_SET - * Enable/Disable the MAC loopback feature. The packet's arguments specify * the NIC port, relevant lanes to configure and one bit indication for * enable/disable. * * CPUCP_PACKET_NIC_MAC_INIT - * Configure the NIC MAC channels. The packet's arguments specify the * NIC port and the speed. * * CPUCP_PACKET_MSI_INFO_SET - * set the index number for each supported msi type going from * host to device * * CPUCP_PACKET_NIC_XPCS91_REGS_GET - * Fetch the un/correctable counters values from the NIC MAC. * * CPUCP_PACKET_NIC_STAT_REGS_GET - * Fetch various NIC MAC counters from the NIC STAT. * * CPUCP_PACKET_NIC_STAT_REGS_CLR - * Clear the various NIC MAC counters in the NIC STAT. * * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - * Fetch all NIC MAC counters from the NIC STAT. * * CPUCP_PACKET_IS_IDLE_CHECK - * Check if the device is IDLE in regard to the DMA/compute engines * and QMANs. The f/w will return a bitmask where each bit represents * a different engine or QMAN according to enum cpucp_idle_mask. * The bit will be 1 if the engine is NOT idle. * * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - * Fetch all HBM replaced-rows and prending to be replaced rows data. * * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - * Fetch status of HBM rows pending replacement and need a reboot to * be replaced. * * CPUCP_PACKET_POWER_SET - * Resets power history of device to 0 * * CPUCP_PACKET_ENGINE_CORE_ASID_SET - * Packet to perform engine core ASID configuration * * CPUCP_PACKET_SEC_ATTEST_GET - * Get the attestaion data that is collected during various stages of the * boot sequence. the attestation data is also hashed with some unique * number (nonce) provided by the host to prevent replay attacks. * public key and certificate also provided as part of the FW response. * * CPUCP_PACKET_INFO_SIGNED_GET - * Get the device information signed by the Trusted Platform device. * device info data is also hashed with some unique number (nonce) provided * by the host to prevent replay attacks. public key and certificate also * provided as part of the FW response. * * CPUCP_PACKET_MONITOR_DUMP_GET - * Get monitors registers dump from the CpuCP kernel. * The CPU will put the registers dump in the a buffer allocated by the driver * which address is passed via the CpuCp packet. In addition, the host's driver * passes the max size it allows the CpuCP to write to the structure, to prevent * data corruption in case of mismatched driver/FW versions. * Obsolete. * * CPUCP_PACKET_GENERIC_PASSTHROUGH - * Generic opcode for all firmware info that is only passed to host * through the LKD, without getting parsed there. * * CPUCP_PACKET_ACTIVE_STATUS_SET - * LKD sends FW indication whether device is free or in use, this indication is reported * also to the BMC. * * CPUCP_PACKET_SOFT_RESET - * Packet to perform soft-reset. * * CPUCP_PACKET_INTS_REGISTER - * Packet to inform FW that queues have been established and LKD is ready to receive * EQ events. */ enum cpucp_packet_id { … }; #define CPUCP_PACKET_FENCE_VAL … #define CPUCP_PKT_CTL_RC_SHIFT … #define CPUCP_PKT_CTL_RC_MASK … #define CPUCP_PKT_CTL_OPCODE_SHIFT … #define CPUCP_PKT_CTL_OPCODE_MASK … #define CPUCP_PKT_RES_PLL_OUT0_SHIFT … #define CPUCP_PKT_RES_PLL_OUT0_MASK … #define CPUCP_PKT_RES_PLL_OUT1_SHIFT … #define CPUCP_PKT_RES_PLL_OUT1_MASK … #define CPUCP_PKT_RES_PLL_OUT2_SHIFT … #define CPUCP_PKT_RES_PLL_OUT2_MASK … #define CPUCP_PKT_RES_PLL_OUT3_SHIFT … #define CPUCP_PKT_RES_PLL_OUT3_MASK … #define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT … #define CPUCP_PKT_RES_EEPROM_OUT0_MASK … #define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT … #define CPUCP_PKT_RES_EEPROM_OUT1_MASK … #define CPUCP_PKT_VAL_PFC_IN1_SHIFT … #define CPUCP_PKT_VAL_PFC_IN1_MASK … #define CPUCP_PKT_VAL_PFC_IN2_SHIFT … #define CPUCP_PKT_VAL_PFC_IN2_MASK … #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT … #define CPUCP_PKT_VAL_LPBK_IN1_MASK … #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT … #define CPUCP_PKT_VAL_LPBK_IN2_MASK … #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT … #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK … #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT … #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK … /* heartbeat status bits */ #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT … #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK … struct cpucp_packet { … }; struct cpucp_unmask_irq_arr_packet { … }; struct cpucp_nic_status_packet { … }; struct cpucp_array_data_packet { … }; enum cpucp_led_index { … }; /* * enum cpucp_packet_rc - Error return code * @cpucp_packet_success -> in case of success. * @cpucp_packet_invalid -> this is to support first generation platforms. * @cpucp_packet_fault -> in case of processing error like failing to * get device binding or semaphore etc. * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. * @cpucp_packet_invalid_params -> when checking parameter like length of buffer * or attribute value etc. * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. */ enum cpucp_packet_rc { … }; /* * cpucp_temp_type should adhere to hwmon_temp_attributes * defined in Linux kernel hwmon.h file */ enum cpucp_temp_type { … }; enum cpucp_in_attributes { … }; enum cpucp_curr_attributes { … }; enum cpucp_fan_attributes { … }; enum cpucp_pwm_attributes { … }; enum cpucp_pcie_throughput_attributes { … }; /* TODO temporary kept before removal */ enum cpucp_pll_reg_attributes { … }; /* TODO temporary kept before removal */ enum cpucp_pll_type_attributes { … }; /* * cpucp_power_type aligns with hwmon_power_attributes * defined in Linux kernel hwmon.h file */ enum cpucp_power_type { … }; /* * MSI type enumeration table for all ASICs and future SW versions. * For future ASIC-LKD compatibility, we can only add new enumerations. * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). * Changing the order of entries or removing entries is not allowed. */ enum cpucp_msi_type { … }; /* * PLL enumeration table used for all ASICs and future SW versions. * For future ASIC-LKD compatibility, we can only add new enumerations. * at the end of the table. * Changing the order of entries or removing entries is not allowed. */ enum pll_index { … }; enum rl_index { … }; enum pvt_index { … }; /* Event Queue Packets */ struct eq_generic_event { … }; /* * CpuCP info */ #define CARD_NAME_MAX_LEN … #define CPUCP_MAX_SENSORS … #define CPUCP_MAX_NICS … #define CPUCP_LANES_PER_NIC … #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN … #define CPUCP_MAX_NIC_LANES … #define CPUCP_NIC_MASK_ARR_LEN … #define CPUCP_NIC_POLARITY_ARR_LEN … #define CPUCP_HBM_ROW_REPLACE_MAX … struct cpucp_sensor { … }; /** * struct cpucp_card_types - ASIC card type. * @cpucp_card_type_pci: PCI card. * @cpucp_card_type_pmc: PCI Mezzanine Card. */ enum cpucp_card_types { … }; #define CPUCP_SEC_CONF_ENABLED_SHIFT … #define CPUCP_SEC_CONF_ENABLED_MASK … #define CPUCP_SEC_CONF_FLASH_WP_SHIFT … #define CPUCP_SEC_CONF_FLASH_WP_MASK … #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT … #define CPUCP_SEC_CONF_EEPROM_WP_MASK … /** * struct cpucp_security_info - Security information. * @config: configuration bit field * @keys_num: number of stored keys * @revoked_keys: revoked keys bit field * @min_svn: minimal security version */ struct cpucp_security_info { … }; /** * struct cpucp_info - Info from CpuCP that is necessary to the host's driver * @sensors: available sensors description. * @kernel_version: CpuCP linux kernel version. * @reserved: reserved field. * @card_type: card configuration type. * @card_location: in a server, each card has different connections topology * depending on its location (relevant for PMC card type) * @cpld_version: CPLD programmed F/W version. * @infineon_version: Infineon main DC-DC version. * @fuse_version: silicon production FUSE information. * @thermal_version: thermald S/W version. * @cpucp_version: CpuCP S/W version. * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. * @dram_size: available DRAM size. * @card_name: card name that will be displayed in HWMON subsystem on the host * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance * (0 = functional, 1 = binned) * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance * (0 = functional, 1 = binned), maximum 1 per dcore * @sram_binning: Categorize SRAM functionality * (0 = fully functional, 1 = lower-half is not functional, * 2 = upper-half is not functional) * @sec_info: security information * @cpld_timestamp: CPLD programmed F/W timestamp. * @pll_map: Bit map of supported PLLs for current ASIC version. * @mme_binning_mask: MME binning mask, * bits [0:6] <==> dcore0 mme fma * bits [7:13] <==> dcore1 mme fma * bits [14:20] <==> dcore0 mme ima * bits [21:27] <==> dcore1 mme ima * For each group, if the 6th bit is set then first 5 bits * represent the col's idx [0-31], otherwise these bits are * ignored, and col idx 32 is binned. 7th bit is don't care. * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance * (0 = functional 1 = binned) * @memory_repair_flag: eFuse flag indicating memory repair * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance * (0 = functional 1 = binned) * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance * (0 = functional 1 = binned) * @interposer_version: Interposer version programmed in eFuse * @substrate_version: Substrate version programmed in eFuse * @eq_health_check_supported: eq health check feature supported in FW. * @fw_hbm_region_size: Size in bytes of FW reserved region in HBM. * @fw_os_version: Firmware OS Version */ struct cpucp_info { … }; struct cpucp_mac_addr { … }; enum cpucp_serdes_type { … }; struct cpucp_nic_info { … }; #define PAGE_DISCARD_MAX … struct page_discard_info { … }; /* * struct frac_val - fracture value represented by "integer.frac". * @integer: the integer part of the fracture value; * @frac: the fracture part of the fracture value. */ struct frac_val { … }; /* * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". * @integer: the integer part of the SER value; * @exp: the exponent part of the SER value. */ struct ser_val { … }; /* * struct cpucp_nic_status - describes the status of a NIC port. * @port: NIC port index. * @bad_format_cnt: e.g. CRC. * @responder_out_of_sequence_psn_cnt: e.g NAK. * @high_ber_reinit_cnt: link reinit due to high BER. * @correctable_err_cnt: e.g. bit-flip. * @uncorrectable_err_cnt: e.g. MAC errors. * @retraining_cnt: re-training counter. * @up: is port up. * @pcs_link: has PCS link. * @phy_ready: is PHY ready. * @auto_neg: is Autoneg enabled. * @timeout_retransmission_cnt: timeout retransmission events. * @high_ber_cnt: high ber events. * @pre_fec_ser: pre FEC SER value. * @post_fec_ser: post FEC SER value. * @throughput: measured throughput. * @latency: measured latency. */ struct cpucp_nic_status { … }; enum cpucp_hbm_row_replace_cause { … }; struct cpucp_hbm_row_info { … }; struct cpucp_hbm_row_replaced_rows_info { … }; enum cpu_reset_status { … }; #define SEC_PCR_DATA_BUF_SZ … #define SEC_PCR_QUOTE_BUF_SZ … #define SEC_SIGNATURE_BUF_SZ … #define SEC_PUB_DATA_BUF_SZ … #define SEC_CERTIFICATE_BUF_SZ … /* * struct cpucp_sec_attest_info - attestation report of the boot * @pcr_data: raw values of the PCR registers * @pcr_num_reg: number of PCR registers in the pcr_data array * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) * @nonce: number only used once. random number provided by host. this also * passed to the quote command as a qualifying data. * @pcr_quote_len: length of the attestation quote data (bytes) * @pcr_quote: attestation report data structure * @quote_sig_len: length of the attestation report signature (bytes) * @quote_sig: signature structure of the attestation report * @pub_data_len: length of the public data (bytes) * @public_data: public key for the signed attestation * (outPublic + name + qualifiedName) * @certificate_len: length of the certificate (bytes) * @certificate: certificate for the attestation signing key */ struct cpucp_sec_attest_info { … }; /* * struct cpucp_dev_info_signed - device information signed by a secured device * @info: device information structure as defined above * @nonce: number only used once. random number provided by host. this number is * hashed and signed along with the device information. * @info_sig_len: length of the attestation signature (bytes) * @info_sig: signature of the info + nonce data. * @pub_data_len: length of the public data (bytes) * @public_data: public key info signed info data * (outPublic + name + qualifiedName) * @certificate_len: length of the certificate (bytes) * @certificate: certificate for the signing key */ struct cpucp_dev_info_signed { … }; #define DCORE_MON_REGS_SZ … /* * struct dcore_monitor_regs_data - DCORE monitor regs data. * the structure follows sync manager block layout. Obsolete. * @mon_pay_addrl: array of payload address low bits. * @mon_pay_addrh: array of payload address high bits. * @mon_pay_data: array of payload data. * @mon_arm: array of monitor arm. * @mon_status: array of monitor status. */ struct dcore_monitor_regs_data { … }; /* contains SM data for each SYNC_MNGR (Obsolete) */ struct cpucp_monitor_dump { … }; /* * The Type of the generic request (and other input arguments) will be fetched from user by reading * from "pkt_subidx" field in struct cpucp_packet. * * HL_PASSTHROUGHT_VERSIONS - Fetch all firmware versions. */ enum hl_passthrough_type { … }; #endif /* CPUCP_IF_H */
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