/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2020-2023 Intel Corporation */ #ifndef __IVPU_HW_40XX_REG_H__ #define __IVPU_HW_40XX_REG_H__ #include <linux/bits.h> #define VPU_40XX_HOST_SS_CPR_CLK_EN … #define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK … #define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_CLK_SET … #define VPU_40XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK … #define VPU_40XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_EN … #define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK … #define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_SET … #define VPU_40XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK … #define VPU_40XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_CLR … #define VPU_40XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK … #define VPU_40XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK … #define VPU_40XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK … #define VPU_40XX_HOST_SS_HW_VERSION … #define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK … #define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK … #define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK … #define VPU_40XX_HOST_SS_SW_VERSION … #define VPU_40XX_HOST_SS_GEN_CTRL … #define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK … #define VPU_40XX_HOST_SS_NOC_QREQN … #define VPU_40XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK … #define VPU_40XX_HOST_SS_NOC_QACCEPTN … #define VPU_40XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK … #define VPU_40XX_HOST_SS_NOC_QDENY … #define VPU_40XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK … #define VPU_40XX_TOP_NOC_QREQN … #define VPU_40XX_TOP_NOC_QREQN_CPU_CTRL_MASK … #define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK … #define VPU_40XX_TOP_NOC_QACCEPTN … #define VPU_40XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK … #define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK … #define VPU_40XX_TOP_NOC_QDENY … #define VPU_40XX_TOP_NOC_QDENY_CPU_CTRL_MASK … #define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK … #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0 … #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_1 … #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK … #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK … #define VPU_40XX_HOST_SS_ICB_CLEAR_0 … #define VPU_40XX_HOST_SS_ICB_CLEAR_1 … #define VPU_40XX_HOST_SS_ICB_ENABLE_0 … #define VPU_40XX_HOST_SS_ICB_ENABLE_1 … #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM … #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT … #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK … #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0 … #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0_CSS_CPU_MASK … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0_CSS_CPU_MASK … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0 … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_CSS_CPU_MASK … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 … #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK … #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY … #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK … #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY … #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK … #define VPU_40XX_HOST_SS_AON_IDLE_GEN … #define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK … #define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK … #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE … #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK … #define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE … #define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK … #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO … #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK … #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK … #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK … #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR … #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK … #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK … #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK … #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK … #define VPU_40XX_CPU_SS_DSU_LEON_RT_BASE … #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_CTRL … #define VPU_40XX_CPU_SS_DSU_LEON_RT_PC_REG … #define VPU_40XX_CPU_SS_DSU_LEON_RT_NPC_REG … #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG … #define VPU_40XX_CPU_SS_TIM_WATCHDOG … #define VPU_40XX_CPU_SS_TIM_WDOG_EN … #define VPU_40XX_CPU_SS_TIM_SAFE … #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG … #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK … #define VPU_40XX_CPU_SS_CPR_NOC_QREQN … #define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK … #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN … #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK … #define VPU_40XX_CPU_SS_CPR_NOC_QDENY … #define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK … #define VPU_40XX_CPU_SS_TIM_IPC_FIFO … #define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT … #define VPU_40XX_CPU_SS_DOORBELL_0 … #define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK … #define VPU_40XX_CPU_SS_DOORBELL_1 … #endif /* __IVPU_HW_40XX_REG_H__ */
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