/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * cs42l51.h * * ASoC Driver for Cirrus Logic CS42L51 codecs * * Copyright (c) 2010 Arnaud Patard <[email protected]> */ #ifndef _CS42L51_H #define _CS42L51_H struct device; extern const struct regmap_config cs42l51_regmap; int cs42l51_probe(struct device *dev, struct regmap *regmap); void cs42l51_remove(struct device *dev); int __maybe_unused cs42l51_suspend(struct device *dev); int __maybe_unused cs42l51_resume(struct device *dev); #define CS42L51_CHIP_ID … #define CS42L51_CHIP_REV_A … #define CS42L51_CHIP_REV_B … #define CS42L51_CHIP_REV_MASK … #define CS42L51_CHIP_REV_ID … #define CS42L51_MK_CHIP_REV(a, b) … #define CS42L51_POWER_CTL1 … #define CS42L51_POWER_CTL1_PDN_DACB … #define CS42L51_POWER_CTL1_PDN_DACA … #define CS42L51_POWER_CTL1_PDN_PGAB … #define CS42L51_POWER_CTL1_PDN_PGAA … #define CS42L51_POWER_CTL1_PDN_ADCB … #define CS42L51_POWER_CTL1_PDN_ADCA … #define CS42L51_POWER_CTL1_PDN … #define CS42L51_MIC_POWER_CTL … #define CS42L51_MIC_POWER_CTL_AUTO … #define CS42L51_MIC_POWER_CTL_SPEED(x) … #define CS42L51_QSM_MODE … #define CS42L51_HSM_MODE … #define CS42L51_SSM_MODE … #define CS42L51_DSM_MODE … #define CS42L51_MIC_POWER_CTL_3ST_SP … #define CS42L51_MIC_POWER_CTL_PDN_MICB … #define CS42L51_MIC_POWER_CTL_PDN_MICA … #define CS42L51_MIC_POWER_CTL_PDN_BIAS … #define CS42L51_MIC_POWER_CTL_MCLK_DIV2 … #define CS42L51_INTF_CTL … #define CS42L51_INTF_CTL_LOOPBACK … #define CS42L51_INTF_CTL_MASTER … #define CS42L51_INTF_CTL_DAC_FORMAT(x) … #define CS42L51_DAC_DIF_LJ24 … #define CS42L51_DAC_DIF_I2S … #define CS42L51_DAC_DIF_RJ24 … #define CS42L51_DAC_DIF_RJ20 … #define CS42L51_DAC_DIF_RJ18 … #define CS42L51_DAC_DIF_RJ16 … #define CS42L51_INTF_CTL_ADC_I2S … #define CS42L51_INTF_CTL_DIGMIX … #define CS42L51_INTF_CTL_MICMIX … #define CS42L51_MIC_CTL … #define CS42L51_MIC_CTL_ADC_SNGVOL … #define CS42L51_MIC_CTL_ADCD_DBOOST … #define CS42L51_MIC_CTL_ADCA_DBOOST … #define CS42L51_MIC_CTL_MICBIAS_SEL … #define CS42L51_MIC_CTL_MICBIAS_LVL(x) … #define CS42L51_MIC_CTL_MICB_BOOST … #define CS42L51_MIC_CTL_MICA_BOOST … #define CS42L51_ADC_CTL … #define CS42L51_ADC_CTL_ADCB_HPFEN … #define CS42L51_ADC_CTL_ADCB_HPFRZ … #define CS42L51_ADC_CTL_ADCA_HPFEN … #define CS42L51_ADC_CTL_ADCA_HPFRZ … #define CS42L51_ADC_CTL_SOFTB … #define CS42L51_ADC_CTL_ZCROSSB … #define CS42L51_ADC_CTL_SOFTA … #define CS42L51_ADC_CTL_ZCROSSA … #define CS42L51_ADC_INPUT … #define CS42L51_ADC_INPUT_AINB_MUX(x) … #define CS42L51_ADC_INPUT_AINA_MUX(x) … #define CS42L51_ADC_INPUT_INV_ADCB … #define CS42L51_ADC_INPUT_INV_ADCA … #define CS42L51_ADC_INPUT_ADCB_MUTE … #define CS42L51_ADC_INPUT_ADCA_MUTE … #define CS42L51_DAC_OUT_CTL … #define CS42L51_DAC_OUT_CTL_HP_GAIN(x) … #define CS42L51_DAC_OUT_CTL_DAC_SNGVOL … #define CS42L51_DAC_OUT_CTL_INV_PCMB … #define CS42L51_DAC_OUT_CTL_INV_PCMA … #define CS42L51_DAC_OUT_CTL_DACB_MUTE … #define CS42L51_DAC_OUT_CTL_DACA_MUTE … #define CS42L51_DAC_CTL … #define CS42L51_DAC_CTL_DATA_SEL(x) … #define CS42L51_DAC_CTL_FREEZE … #define CS42L51_DAC_CTL_DEEMPH … #define CS42L51_DAC_CTL_AMUTE … #define CS42L51_DAC_CTL_DACSZ(x) … #define CS42L51_ALC_PGA_CTL … #define CS42L51_ALC_PGB_CTL … #define CS42L51_ALC_PGX_ALCX_SRDIS … #define CS42L51_ALC_PGX_ALCX_ZCDIS … #define CS42L51_ALC_PGX_PGX_VOL(x) … #define CS42L51_ADCA_ATT … #define CS42L51_ADCB_ATT … #define CS42L51_ADCA_VOL … #define CS42L51_ADCB_VOL … #define CS42L51_PCMA_VOL … #define CS42L51_PCMB_VOL … #define CS42L51_MIX_MUTE_ADCMIX … #define CS42L51_MIX_VOLUME(x) … #define CS42L51_BEEP_FREQ … #define CS42L51_BEEP_VOL … #define CS42L51_BEEP_CONF … #define CS42L51_TONE_CTL … #define CS42L51_TONE_CTL_TREB(x) … #define CS42L51_TONE_CTL_BASS(x) … #define CS42L51_AOUTA_VOL … #define CS42L51_AOUTB_VOL … #define CS42L51_PCM_MIXER … #define CS42L51_LIMIT_THRES_DIS … #define CS42L51_LIMIT_REL … #define CS42L51_LIMIT_ATT … #define CS42L51_ALC_EN … #define CS42L51_ALC_REL … #define CS42L51_ALC_THRES … #define CS42L51_NOISE_CONF … #define CS42L51_STATUS … #define CS42L51_STATUS_SP_CLKERR … #define CS42L51_STATUS_SPEA_OVFL … #define CS42L51_STATUS_SPEB_OVFL … #define CS42L51_STATUS_PCMA_OVFL … #define CS42L51_STATUS_PCMB_OVFL … #define CS42L51_STATUS_ADCA_OVFL … #define CS42L51_STATUS_ADCB_OVFL … #define CS42L51_CHARGE_FREQ … #define CS42L51_FIRSTREG … /* * Hack: with register 0x21, it makes 33 registers. Looks like someone in the * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using * 32 regs */ #define CS42L51_LASTREG … #define CS42L51_NUMREGS … #endif
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