linux/include/dt-bindings/clock/r8a779f0-cpg-mssr.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Copyright (C) 2021 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a779f0 CPG Core Clocks */

#define R8A779F0_CLK_ZX …
#define R8A779F0_CLK_ZS …
#define R8A779F0_CLK_ZT …
#define R8A779F0_CLK_ZTR …
#define R8A779F0_CLK_S0D2 …
#define R8A779F0_CLK_S0D3 …
#define R8A779F0_CLK_S0D4 …
#define R8A779F0_CLK_S0D2_MM …
#define R8A779F0_CLK_S0D3_MM …
#define R8A779F0_CLK_S0D4_MM …
#define R8A779F0_CLK_S0D2_RT …
#define R8A779F0_CLK_S0D3_RT …
#define R8A779F0_CLK_S0D4_RT …
#define R8A779F0_CLK_S0D6_RT …
#define R8A779F0_CLK_S0D3_PER …
#define R8A779F0_CLK_S0D6_PER …
#define R8A779F0_CLK_S0D12_PER …
#define R8A779F0_CLK_S0D24_PER …
#define R8A779F0_CLK_S0D2_HSC …
#define R8A779F0_CLK_S0D3_HSC …
#define R8A779F0_CLK_S0D4_HSC …
#define R8A779F0_CLK_S0D6_HSC …
#define R8A779F0_CLK_S0D12_HSC …
#define R8A779F0_CLK_S0D2_CC …
#define R8A779F0_CLK_CL …
#define R8A779F0_CLK_CL16M …
#define R8A779F0_CLK_CL16M_MM …
#define R8A779F0_CLK_CL16M_RT …
#define R8A779F0_CLK_CL16M_PER …
#define R8A779F0_CLK_CL16M_HSC …
#define R8A779F0_CLK_Z0 …
#define R8A779F0_CLK_Z1 …
#define R8A779F0_CLK_ZB3 …
#define R8A779F0_CLK_ZB3D2 …
#define R8A779F0_CLK_ZB3D4 …
#define R8A779F0_CLK_SD0H …
#define R8A779F0_CLK_SD0 …
#define R8A779F0_CLK_RPC …
#define R8A779F0_CLK_RPCD2 …
#define R8A779F0_CLK_MSO …
#define R8A779F0_CLK_SASYNCRT …
#define R8A779F0_CLK_SASYNCPERD1 …
#define R8A779F0_CLK_SASYNCPERD2 …
#define R8A779F0_CLK_SASYNCPERD4 …
#define R8A779F0_CLK_DBGSOC_HSC …
#define R8A779F0_CLK_RSW2 …
#define R8A779F0_CLK_OSC …
#define R8A779F0_CLK_ZR …
#define R8A779F0_CLK_CPEX …
#define R8A779F0_CLK_CBFUSA …
#define R8A779F0_CLK_R …

#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */