/* * ACP_2_2 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef ACP_2_2_D_H #define ACP_2_2_D_H #define mmACP_DMA_CNTL_0 … #define mmACP_DMA_CNTL_1 … #define mmACP_DMA_CNTL_2 … #define mmACP_DMA_CNTL_3 … #define mmACP_DMA_CNTL_4 … #define mmACP_DMA_CNTL_5 … #define mmACP_DMA_CNTL_6 … #define mmACP_DMA_CNTL_7 … #define mmACP_DMA_CNTL_8 … #define mmACP_DMA_CNTL_9 … #define mmACP_DMA_CNTL_10 … #define mmACP_DMA_CNTL_11 … #define mmACP_DMA_CNTL_12 … #define mmACP_DMA_CNTL_13 … #define mmACP_DMA_CNTL_14 … #define mmACP_DMA_CNTL_15 … #define mmACP_DMA_DSCR_STRT_IDX_0 … #define mmACP_DMA_DSCR_STRT_IDX_1 … #define mmACP_DMA_DSCR_STRT_IDX_2 … #define mmACP_DMA_DSCR_STRT_IDX_3 … #define mmACP_DMA_DSCR_STRT_IDX_4 … #define mmACP_DMA_DSCR_STRT_IDX_5 … #define mmACP_DMA_DSCR_STRT_IDX_6 … #define mmACP_DMA_DSCR_STRT_IDX_7 … #define mmACP_DMA_DSCR_STRT_IDX_8 … #define mmACP_DMA_DSCR_STRT_IDX_9 … #define mmACP_DMA_DSCR_STRT_IDX_10 … #define mmACP_DMA_DSCR_STRT_IDX_11 … #define mmACP_DMA_DSCR_STRT_IDX_12 … #define mmACP_DMA_DSCR_STRT_IDX_13 … #define mmACP_DMA_DSCR_STRT_IDX_14 … #define mmACP_DMA_DSCR_STRT_IDX_15 … #define mmACP_DMA_DSCR_CNT_0 … #define mmACP_DMA_DSCR_CNT_1 … #define mmACP_DMA_DSCR_CNT_2 … #define mmACP_DMA_DSCR_CNT_3 … #define mmACP_DMA_DSCR_CNT_4 … #define mmACP_DMA_DSCR_CNT_5 … #define mmACP_DMA_DSCR_CNT_6 … #define mmACP_DMA_DSCR_CNT_7 … #define mmACP_DMA_DSCR_CNT_8 … #define mmACP_DMA_DSCR_CNT_9 … #define mmACP_DMA_DSCR_CNT_10 … #define mmACP_DMA_DSCR_CNT_11 … #define mmACP_DMA_DSCR_CNT_12 … #define mmACP_DMA_DSCR_CNT_13 … #define mmACP_DMA_DSCR_CNT_14 … #define mmACP_DMA_DSCR_CNT_15 … #define mmACP_DMA_PRIO_0 … #define mmACP_DMA_PRIO_1 … #define mmACP_DMA_PRIO_2 … #define mmACP_DMA_PRIO_3 … #define mmACP_DMA_PRIO_4 … #define mmACP_DMA_PRIO_5 … #define mmACP_DMA_PRIO_6 … #define mmACP_DMA_PRIO_7 … #define mmACP_DMA_PRIO_8 … #define mmACP_DMA_PRIO_9 … #define mmACP_DMA_PRIO_10 … #define mmACP_DMA_PRIO_11 … #define mmACP_DMA_PRIO_12 … #define mmACP_DMA_PRIO_13 … #define mmACP_DMA_PRIO_14 … #define mmACP_DMA_PRIO_15 … #define mmACP_DMA_CUR_DSCR_0 … #define mmACP_DMA_CUR_DSCR_1 … #define mmACP_DMA_CUR_DSCR_2 … #define mmACP_DMA_CUR_DSCR_3 … #define mmACP_DMA_CUR_DSCR_4 … #define mmACP_DMA_CUR_DSCR_5 … #define mmACP_DMA_CUR_DSCR_6 … #define mmACP_DMA_CUR_DSCR_7 … #define mmACP_DMA_CUR_DSCR_8 … #define mmACP_DMA_CUR_DSCR_9 … #define mmACP_DMA_CUR_DSCR_10 … #define mmACP_DMA_CUR_DSCR_11 … #define mmACP_DMA_CUR_DSCR_12 … #define mmACP_DMA_CUR_DSCR_13 … #define mmACP_DMA_CUR_DSCR_14 … #define mmACP_DMA_CUR_DSCR_15 … #define mmACP_DMA_CUR_TRANS_CNT_0 … #define mmACP_DMA_CUR_TRANS_CNT_1 … #define mmACP_DMA_CUR_TRANS_CNT_2 … #define mmACP_DMA_CUR_TRANS_CNT_3 … #define mmACP_DMA_CUR_TRANS_CNT_4 … #define mmACP_DMA_CUR_TRANS_CNT_5 … #define mmACP_DMA_CUR_TRANS_CNT_6 … #define mmACP_DMA_CUR_TRANS_CNT_7 … #define mmACP_DMA_CUR_TRANS_CNT_8 … #define mmACP_DMA_CUR_TRANS_CNT_9 … #define mmACP_DMA_CUR_TRANS_CNT_10 … #define mmACP_DMA_CUR_TRANS_CNT_11 … #define mmACP_DMA_CUR_TRANS_CNT_12 … #define mmACP_DMA_CUR_TRANS_CNT_13 … #define mmACP_DMA_CUR_TRANS_CNT_14 … #define mmACP_DMA_CUR_TRANS_CNT_15 … #define mmACP_DMA_ERR_STS_0 … #define mmACP_DMA_ERR_STS_1 … #define mmACP_DMA_ERR_STS_2 … #define mmACP_DMA_ERR_STS_3 … #define mmACP_DMA_ERR_STS_4 … #define mmACP_DMA_ERR_STS_5 … #define mmACP_DMA_ERR_STS_6 … #define mmACP_DMA_ERR_STS_7 … #define mmACP_DMA_ERR_STS_8 … #define mmACP_DMA_ERR_STS_9 … #define mmACP_DMA_ERR_STS_10 … #define mmACP_DMA_ERR_STS_11 … #define mmACP_DMA_ERR_STS_12 … #define mmACP_DMA_ERR_STS_13 … #define mmACP_DMA_ERR_STS_14 … #define mmACP_DMA_ERR_STS_15 … #define mmACP_DMA_DESC_BASE_ADDR … #define mmACP_DMA_DESC_MAX_NUM_DSCR … #define mmACP_DMA_CH_STS … #define mmACP_DMA_CH_GROUP … #define mmACP_DSP0_CACHE_OFFSET0 … #define mmACP_DSP0_CACHE_SIZE0 … #define mmACP_DSP0_CACHE_OFFSET1 … #define mmACP_DSP0_CACHE_SIZE1 … #define mmACP_DSP0_CACHE_OFFSET2 … #define mmACP_DSP0_CACHE_SIZE2 … #define mmACP_DSP0_CACHE_OFFSET3 … #define mmACP_DSP0_CACHE_SIZE3 … #define mmACP_DSP0_CACHE_OFFSET4 … #define mmACP_DSP0_CACHE_SIZE4 … #define mmACP_DSP0_CACHE_OFFSET5 … #define mmACP_DSP0_CACHE_SIZE5 … #define mmACP_DSP0_CACHE_OFFSET6 … #define mmACP_DSP0_CACHE_SIZE6 … #define mmACP_DSP0_CACHE_OFFSET7 … #define mmACP_DSP0_CACHE_SIZE7 … #define mmACP_DSP0_CACHE_OFFSET8 … #define mmACP_DSP0_CACHE_SIZE8 … #define mmACP_DSP0_NONCACHE_OFFSET0 … #define mmACP_DSP0_NONCACHE_SIZE0 … #define mmACP_DSP0_NONCACHE_OFFSET1 … #define mmACP_DSP0_NONCACHE_SIZE1 … #define mmACP_DSP0_DEBUG_PC … #define mmACP_DSP0_NMI_SEL … #define mmACP_DSP0_CLKRST_CNTL … #define mmACP_DSP0_RUNSTALL … #define mmACP_DSP0_OCD_HALT_ON_RST … #define mmACP_DSP0_WAIT_MODE … #define mmACP_DSP0_VECT_SEL … #define mmACP_DSP0_DEBUG_REG1 … #define mmACP_DSP0_DEBUG_REG2 … #define mmACP_DSP0_DEBUG_REG3 … #define mmACP_DSP1_CACHE_OFFSET0 … #define mmACP_DSP1_CACHE_SIZE0 … #define mmACP_DSP1_CACHE_OFFSET1 … #define mmACP_DSP1_CACHE_SIZE1 … #define mmACP_DSP1_CACHE_OFFSET2 … #define mmACP_DSP1_CACHE_SIZE2 … #define mmACP_DSP1_CACHE_OFFSET3 … #define mmACP_DSP1_CACHE_SIZE3 … #define mmACP_DSP1_CACHE_OFFSET4 … #define mmACP_DSP1_CACHE_SIZE4 … #define mmACP_DSP1_CACHE_OFFSET5 … #define mmACP_DSP1_CACHE_SIZE5 … #define mmACP_DSP1_CACHE_OFFSET6 … #define mmACP_DSP1_CACHE_SIZE6 … #define mmACP_DSP1_CACHE_OFFSET7 … #define mmACP_DSP1_CACHE_SIZE7 … #define mmACP_DSP1_CACHE_OFFSET8 … #define mmACP_DSP1_CACHE_SIZE8 … #define mmACP_DSP1_NONCACHE_OFFSET0 … #define mmACP_DSP1_NONCACHE_SIZE0 … #define mmACP_DSP1_NONCACHE_OFFSET1 … #define mmACP_DSP1_NONCACHE_SIZE1 … #define mmACP_DSP1_DEBUG_PC … #define mmACP_DSP1_NMI_SEL … #define mmACP_DSP1_CLKRST_CNTL … #define mmACP_DSP1_RUNSTALL … #define mmACP_DSP1_OCD_HALT_ON_RST … #define mmACP_DSP1_WAIT_MODE … #define mmACP_DSP1_VECT_SEL … #define mmACP_DSP1_DEBUG_REG1 … #define mmACP_DSP1_DEBUG_REG2 … #define mmACP_DSP1_DEBUG_REG3 … #define mmACP_DSP2_CACHE_OFFSET0 … #define mmACP_DSP2_CACHE_SIZE0 … #define mmACP_DSP2_CACHE_OFFSET1 … #define mmACP_DSP2_CACHE_SIZE1 … #define mmACP_DSP2_CACHE_OFFSET2 … #define mmACP_DSP2_CACHE_SIZE2 … #define mmACP_DSP2_CACHE_OFFSET3 … #define mmACP_DSP2_CACHE_SIZE3 … #define mmACP_DSP2_CACHE_OFFSET4 … #define mmACP_DSP2_CACHE_SIZE4 … #define mmACP_DSP2_CACHE_OFFSET5 … #define mmACP_DSP2_CACHE_SIZE5 … #define mmACP_DSP2_CACHE_OFFSET6 … #define mmACP_DSP2_CACHE_SIZE6 … #define mmACP_DSP2_CACHE_OFFSET7 … #define mmACP_DSP2_CACHE_SIZE7 … #define mmACP_DSP2_CACHE_OFFSET8 … #define mmACP_DSP2_CACHE_SIZE8 … #define mmACP_DSP2_NONCACHE_OFFSET0 … #define mmACP_DSP2_NONCACHE_SIZE0 … #define mmACP_DSP2_NONCACHE_OFFSET1 … #define mmACP_DSP2_NONCACHE_SIZE1 … #define mmACP_DSP2_DEBUG_PC … #define mmACP_DSP2_NMI_SEL … #define mmACP_DSP2_CLKRST_CNTL … #define mmACP_DSP2_RUNSTALL … #define mmACP_DSP2_OCD_HALT_ON_RST … #define mmACP_DSP2_WAIT_MODE … #define mmACP_DSP2_VECT_SEL … #define mmACP_DSP2_DEBUG_REG1 … #define mmACP_DSP2_DEBUG_REG2 … #define mmACP_DSP2_DEBUG_REG3 … #define mmACP_AXI2DAGB_ONION_CNTL … #define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR … #define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD … #define mmACP_DAGB_Onion_TransPerf_Counter_Control … #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current … #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak … #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current … #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak … #define mmACP_AXI2DAGB_GARLIC_CNTL … #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR … #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD … #define mmACP_DAGB_Garlic_TransPerf_Counter_Control … #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current … #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak … #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current … #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak … #define mmACP_DAGB_PAGE_SIZE_GRP_1 … #define mmACP_DAGB_BASE_ADDR_GRP_1 … #define mmACP_DAGB_PAGE_SIZE_GRP_2 … #define mmACP_DAGB_BASE_ADDR_GRP_2 … #define mmACP_DAGB_PAGE_SIZE_GRP_3 … #define mmACP_DAGB_BASE_ADDR_GRP_3 … #define mmACP_DAGB_PAGE_SIZE_GRP_4 … #define mmACP_DAGB_BASE_ADDR_GRP_4 … #define mmACP_DAGB_PAGE_SIZE_GRP_5 … #define mmACP_DAGB_BASE_ADDR_GRP_5 … #define mmACP_DAGB_PAGE_SIZE_GRP_6 … #define mmACP_DAGB_BASE_ADDR_GRP_6 … #define mmACP_DAGB_PAGE_SIZE_GRP_7 … #define mmACP_DAGB_BASE_ADDR_GRP_7 … #define mmACP_DAGB_PAGE_SIZE_GRP_8 … #define mmACP_DAGB_BASE_ADDR_GRP_8 … #define mmACP_DAGB_ATU_CTRL … #define mmACP_CONTROL … #define mmACP_STATUS … #define mmACP_SOFT_RESET … #define mmACP_PwrMgmt_CNTL … #define mmACP_CAC_INDICATOR_CONTROL … #define mmACP_SMU_MAILBOX … #define mmACP_FUTURE_REG_SCLK_0 … #define mmACP_FUTURE_REG_SCLK_1 … #define mmACP_FUTURE_REG_SCLK_2 … #define mmACP_FUTURE_REG_SCLK_3 … #define mmACP_FUTURE_REG_SCLK_4 … #define mmACP_DAGB_DEBUG_CNT_ENABLE … #define mmACP_DAGBG_WR_ASK_CNT … #define mmACP_DAGBG_WR_GO_CNT … #define mmACP_DAGBG_WR_EXP_RESP_CNT … #define mmACP_DAGBG_WR_ACTUAL_RESP_CNT … #define mmACP_DAGBG_RD_ASK_CNT … #define mmACP_DAGBG_RD_GO_CNT … #define mmACP_DAGBG_RD_EXP_RESP_CNT … #define mmACP_DAGBG_RD_ACTUAL_RESP_CNT … #define mmACP_DAGBO_WR_ASK_CNT … #define mmACP_DAGBO_WR_GO_CNT … #define mmACP_DAGBO_WR_EXP_RESP_CNT … #define mmACP_DAGBO_WR_ACTUAL_RESP_CNT … #define mmACP_DAGBO_RD_ASK_CNT … #define mmACP_DAGBO_RD_GO_CNT … #define mmACP_DAGBO_RD_EXP_RESP_CNT … #define mmACP_DAGBO_RD_ACTUAL_RESP_CNT … #define mmACP_BRB_CONTROL … #define mmACP_EXTERNAL_INTR_ENB … #define mmACP_EXTERNAL_INTR_CNTL … #define mmACP_ERROR_SOURCE_STS … #define mmACP_DSP_SW_INTR_TRIG … #define mmACP_DSP_SW_INTR_CNTL … #define mmACP_DAGBG_TIMEOUT_CNTL … #define mmACP_DAGBO_TIMEOUT_CNTL … #define mmACP_EXTERNAL_INTR_STAT … #define mmACP_DSP_SW_INTR_STAT … #define mmACP_DSP0_INTR_CNTL … #define mmACP_DSP0_INTR_STAT … #define mmACP_DSP0_TIMEOUT_CNTL … #define mmACP_DSP1_INTR_CNTL … #define mmACP_DSP1_INTR_STAT … #define mmACP_DSP1_TIMEOUT_CNTL … #define mmACP_DSP2_INTR_CNTL … #define mmACP_DSP2_INTR_STAT … #define mmACP_DSP2_TIMEOUT_CNTL … #define mmACP_DSP0_EXT_TIMER_CNTL … #define mmACP_DSP1_EXT_TIMER_CNTL … #define mmACP_DSP2_EXT_TIMER_CNTL … #define mmACP_AXI2DAGB_SEM_0 … #define mmACP_AXI2DAGB_SEM_1 … #define mmACP_AXI2DAGB_SEM_2 … #define mmACP_AXI2DAGB_SEM_3 … #define mmACP_AXI2DAGB_SEM_4 … #define mmACP_AXI2DAGB_SEM_5 … #define mmACP_AXI2DAGB_SEM_6 … #define mmACP_AXI2DAGB_SEM_7 … #define mmACP_AXI2DAGB_SEM_8 … #define mmACP_AXI2DAGB_SEM_9 … #define mmACP_AXI2DAGB_SEM_10 … #define mmACP_AXI2DAGB_SEM_11 … #define mmACP_AXI2DAGB_SEM_12 … #define mmACP_AXI2DAGB_SEM_13 … #define mmACP_AXI2DAGB_SEM_14 … #define mmACP_AXI2DAGB_SEM_15 … #define mmACP_AXI2DAGB_SEM_16 … #define mmACP_AXI2DAGB_SEM_17 … #define mmACP_AXI2DAGB_SEM_18 … #define mmACP_AXI2DAGB_SEM_19 … #define mmACP_AXI2DAGB_SEM_20 … #define mmACP_AXI2DAGB_SEM_21 … #define mmACP_AXI2DAGB_SEM_22 … #define mmACP_AXI2DAGB_SEM_23 … #define mmACP_AXI2DAGB_SEM_24 … #define mmACP_AXI2DAGB_SEM_25 … #define mmACP_AXI2DAGB_SEM_26 … #define mmACP_AXI2DAGB_SEM_27 … #define mmACP_AXI2DAGB_SEM_28 … #define mmACP_AXI2DAGB_SEM_29 … #define mmACP_AXI2DAGB_SEM_30 … #define mmACP_AXI2DAGB_SEM_31 … #define mmACP_AXI2DAGB_SEM_32 … #define mmACP_AXI2DAGB_SEM_33 … #define mmACP_AXI2DAGB_SEM_34 … #define mmACP_AXI2DAGB_SEM_35 … #define mmACP_AXI2DAGB_SEM_36 … #define mmACP_AXI2DAGB_SEM_37 … #define mmACP_AXI2DAGB_SEM_38 … #define mmACP_AXI2DAGB_SEM_39 … #define mmACP_AXI2DAGB_SEM_40 … #define mmACP_AXI2DAGB_SEM_41 … #define mmACP_AXI2DAGB_SEM_42 … #define mmACP_AXI2DAGB_SEM_43 … #define mmACP_AXI2DAGB_SEM_44 … #define mmACP_AXI2DAGB_SEM_45 … #define mmACP_AXI2DAGB_SEM_46 … #define mmACP_AXI2DAGB_SEM_47 … #define mmACP_SRBM_Client_Base_Addr … #define mmACP_SRBM_Client_RDDATA … #define mmACP_SRBM_Cycle_Sts … #define mmACP_SRBM_Targ_Idx_Addr … #define mmACP_SRBM_Targ_Idx_Data … #define mmACP_SEMA_ADDR_LOW … #define mmACP_SEMA_ADDR_HIGH … #define mmACP_SEMA_CMD … #define mmACP_SEMA_STS … #define mmACP_SEMA_REQ … #define mmACP_FW_STATUS … #define mmACP_FUTURE_REG_ACLK_0 … #define mmACP_FUTURE_REG_ACLK_1 … #define mmACP_FUTURE_REG_ACLK_2 … #define mmACP_FUTURE_REG_ACLK_3 … #define mmACP_FUTURE_REG_ACLK_4 … #define mmACP_TIMER … #define mmACP_TIMER_CNTL … #define mmACP_DSP0_TIMER … #define mmACP_DSP1_TIMER … #define mmACP_DSP2_TIMER … #define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH … #define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW … #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH … #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW … #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH … #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW … #define mmACP_DSP0_CS_STATE … #define mmACP_DSP1_CS_STATE … #define mmACP_DSP2_CS_STATE … #define mmACP_SCRATCH_REG_BASE_ADDR … #define mmCC_ACP_EFUSE … #define mmACP_PGFSM_RETAIN_REG … #define mmACP_PGFSM_CONFIG_REG … #define mmACP_PGFSM_WRITE_REG … #define mmACP_PGFSM_READ_REG_0 … #define mmACP_PGFSM_READ_REG_1 … #define mmACP_PGFSM_READ_REG_2 … #define mmACP_PGFSM_READ_REG_3 … #define mmACP_PGFSM_READ_REG_4 … #define mmACP_PGFSM_READ_REG_5 … #define mmACP_IP_PGFSM_ENABLE … #define mmACP_I2S_PIN_CONFIG … #define mmACP_AZALIA_I2S_SELECT … #define mmACP_CHIP_PKG_FOR_PAD_ISOLATION … #define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL … #define mmACP_BT_UART_PAD_SEL … #define mmACP_SCRATCH_REG_0 … #define mmACP_SCRATCH_REG_1 … #define mmACP_SCRATCH_REG_2 … #define mmACP_SCRATCH_REG_3 … #define mmACP_SCRATCH_REG_4 … #define mmACP_SCRATCH_REG_5 … #define mmACP_SCRATCH_REG_6 … #define mmACP_SCRATCH_REG_7 … #define mmACP_SCRATCH_REG_8 … #define mmACP_SCRATCH_REG_9 … #define mmACP_SCRATCH_REG_10 … #define mmACP_SCRATCH_REG_11 … #define mmACP_SCRATCH_REG_12 … #define mmACP_SCRATCH_REG_13 … #define mmACP_SCRATCH_REG_14 … #define mmACP_SCRATCH_REG_15 … #define mmACP_SCRATCH_REG_16 … #define mmACP_SCRATCH_REG_17 … #define mmACP_SCRATCH_REG_18 … #define mmACP_SCRATCH_REG_19 … #define mmACP_SCRATCH_REG_20 … #define mmACP_SCRATCH_REG_21 … #define mmACP_SCRATCH_REG_22 … #define mmACP_SCRATCH_REG_23 … #define mmACP_SCRATCH_REG_24 … #define mmACP_SCRATCH_REG_25 … #define mmACP_SCRATCH_REG_26 … #define mmACP_SCRATCH_REG_27 … #define mmACP_SCRATCH_REG_28 … #define mmACP_SCRATCH_REG_29 … #define mmACP_SCRATCH_REG_30 … #define mmACP_SCRATCH_REG_31 … #define mmACP_SCRATCH_REG_32 … #define mmACP_SCRATCH_REG_33 … #define mmACP_SCRATCH_REG_34 … #define mmACP_SCRATCH_REG_35 … #define mmACP_SCRATCH_REG_36 … #define mmACP_SCRATCH_REG_37 … #define mmACP_SCRATCH_REG_38 … #define mmACP_SCRATCH_REG_39 … #define mmACP_SCRATCH_REG_40 … #define mmACP_SCRATCH_REG_41 … #define mmACP_SCRATCH_REG_42 … #define mmACP_SCRATCH_REG_43 … #define mmACP_SCRATCH_REG_44 … #define mmACP_SCRATCH_REG_45 … #define mmACP_SCRATCH_REG_46 … #define mmACP_SCRATCH_REG_47 … #define mmACP_VOICE_WAKEUP_ENABLE … #define mmACP_VOICE_WAKEUP_STATUS … #define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD … #define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD … #define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES … #define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS … #define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS … #define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION … #define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH … #define mmI2S_VOICE_WAKEUP_DATA_POINTER … #define mmI2S_VOICE_WAKEUP_AUTH_MATCH … #define mmI2S_VOICE_WAKEUP_8KB_WRAP … #define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH … #define mmACP_I2S_RECEIVED_BYTE_CNT_LOW … #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH … #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW … #define mmACP_MEM_SHUT_DOWN_REQ_LO … #define mmACP_MEM_SHUT_DOWN_REQ_HI … #define mmACP_MEM_SHUT_DOWN_STS_LO … #define mmACP_MEM_SHUT_DOWN_STS_HI … #define mmACP_MEM_DEEP_SLEEP_REQ_LO … #define mmACP_MEM_DEEP_SLEEP_REQ_HI … #define mmACP_MEM_DEEP_SLEEP_STS_LO … #define mmACP_MEM_DEEP_SLEEP_STS_HI … #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO … #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI … #define mmACP_MEM_WAKEUP_FROM_SLEEP_LO … #define mmACP_MEM_WAKEUP_FROM_SLEEP_HI … #define mmACP_I2SSP_IER … #define mmACP_I2SSP_IRER … #define mmACP_I2SSP_ITER … #define mmACP_I2SSP_CER … #define mmACP_I2SSP_CCR … #define mmACP_I2SSP_RXFFR … #define mmACP_I2SSP_TXFFR … #define mmACP_I2SSP_LRBR0 … #define mmACP_I2SSP_RRBR0 … #define mmACP_I2SSP_RER0 … #define mmACP_I2SSP_TER0 … #define mmACP_I2SSP_RCR0 … #define mmACP_I2SSP_TCR0 … #define mmACP_I2SSP_ISR0 … #define mmACP_I2SSP_IMR0 … #define mmACP_I2SSP_ROR0 … #define mmACP_I2SSP_TOR0 … #define mmACP_I2SSP_RFCR0 … #define mmACP_I2SSP_TFCR0 … #define mmACP_I2SSP_RFF0 … #define mmACP_I2SSP_TFF0 … #define mmACP_I2SSP_RXDMA … #define mmACP_I2SSP_RRXDMA … #define mmACP_I2SSP_TXDMA … #define mmACP_I2SSP_RTXDMA … #define mmACP_I2SSP_COMP_PARAM_2 … #define mmACP_I2SSP_COMP_PARAM_1 … #define mmACP_I2SSP_COMP_VERSION … #define mmACP_I2SSP_COMP_TYPE … #define mmACP_I2SMICSP_IER … #define mmACP_I2SMICSP_IRER … #define mmACP_I2SMICSP_ITER … #define mmACP_I2SMICSP_CER … #define mmACP_I2SMICSP_CCR … #define mmACP_I2SMICSP_RXFFR … #define mmACP_I2SMICSP_TXFFR … #define mmACP_I2SMICSP_LRBR0 … #define mmACP_I2SMICSP_RRBR0 … #define mmACP_I2SMICSP_RER0 … #define mmACP_I2SMICSP_TER0 … #define mmACP_I2SMICSP_RCR0 … #define mmACP_I2SMICSP_TCR0 … #define mmACP_I2SMICSP_ISR0 … #define mmACP_I2SMICSP_IMR0 … #define mmACP_I2SMICSP_ROR0 … #define mmACP_I2SMICSP_TOR0 … #define mmACP_I2SMICSP_RFCR0 … #define mmACP_I2SMICSP_TFCR0 … #define mmACP_I2SMICSP_RFF0 … #define mmACP_I2SMICSP_TFF0 … #define mmACP_I2SMICSP_LRBR1 … #define mmACP_I2SMICSP_RRBR1 … #define mmACP_I2SMICSP_RER1 … #define mmACP_I2SMICSP_TER1 … #define mmACP_I2SMICSP_RCR1 … #define mmACP_I2SMICSP_TCR1 … #define mmACP_I2SMICSP_ISR1 … #define mmACP_I2SMICSP_IMR1 … #define mmACP_I2SMICSP_ROR1 … #define mmACP_I2SMICSP_TOR1 … #define mmACP_I2SMICSP_RFCR1 … #define mmACP_I2SMICSP_TFCR1 … #define mmACP_I2SMICSP_RFF1 … #define mmACP_I2SMICSP_TFF1 … #define mmACP_I2SMICSP_RXDMA … #define mmACP_I2SMICSP_RRXDMA … #define mmACP_I2SMICSP_TXDMA … #define mmACP_I2SMICSP_RTXDMA … #define mmACP_I2SMICSP_COMP_PARAM_2 … #define mmACP_I2SMICSP_COMP_PARAM_1 … #define mmACP_I2SMICSP_COMP_VERSION … #define mmACP_I2SMICSP_COMP_TYPE … #define mmACP_I2SBT_IER … #define mmACP_I2SBT_IRER … #define mmACP_I2SBT_ITER … #define mmACP_I2SBT_CER … #define mmACP_I2SBT_CCR … #define mmACP_I2SBT_RXFFR … #define mmACP_I2SBT_TXFFR … #define mmACP_I2SBT_LRBR0 … #define mmACP_I2SBT_RRBR0 … #define mmACP_I2SBT_RER0 … #define mmACP_I2SBT_TER0 … #define mmACP_I2SBT_RCR0 … #define mmACP_I2SBT_TCR0 … #define mmACP_I2SBT_ISR0 … #define mmACP_I2SBT_IMR0 … #define mmACP_I2SBT_ROR0 … #define mmACP_I2SBT_TOR0 … #define mmACP_I2SBT_RFCR0 … #define mmACP_I2SBT_TFCR0 … #define mmACP_I2SBT_RFF0 … #define mmACP_I2SBT_TFF0 … #define mmACP_I2SBT_LRBR1 … #define mmACP_I2SBT_RRBR1 … #define mmACP_I2SBT_RER1 … #define mmACP_I2SBT_TER1 … #define mmACP_I2SBT_RCR1 … #define mmACP_I2SBT_TCR1 … #define mmACP_I2SBT_ISR1 … #define mmACP_I2SBT_IMR1 … #define mmACP_I2SBT_ROR1 … #define mmACP_I2SBT_TOR1 … #define mmACP_I2SBT_RFCR1 … #define mmACP_I2SBT_TFCR1 … #define mmACP_I2SBT_RFF1 … #define mmACP_I2SBT_TFF1 … #define mmACP_I2SBT_RXDMA … #define mmACP_I2SBT_RRXDMA … #define mmACP_I2SBT_TXDMA … #define mmACP_I2SBT_RTXDMA … #define mmACP_I2SBT_COMP_PARAM_2 … #define mmACP_I2SBT_COMP_PARAM_1 … #define mmACP_I2SBT_COMP_VERSION … #define mmACP_I2SBT_COMP_TYPE … #endif /* ACP_2_2_D_H */
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