// SPDX-License-Identifier: GPL-2.0 // // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver // // Author: Timur Tabi <[email protected]> // // Copyright 2007-2010 Freescale Semiconductor, Inc. // // Some notes why imx-pcm-fiq is used instead of DMA on some boards: // // The i.MX SSI core has some nasty limitations in AC97 mode. While most // sane processor vendors have a FIFO per AC97 slot, the i.MX has only // one FIFO which combines all valid receive slots. We cannot even select // which slots we want to receive. The WM9712 with which this driver // was developed with always sends GPIO status data in slot 12 which // we receive in our (PCM-) data stream. The only chance we have is to // manually skip this data in the FIQ handler. With sampling rates different // from 48000Hz not every frame has valid receive data, so the ratio // between pcm data and GPIO status data changes. Our FIQ handler is not // able to handle this, hence this driver only works with 48000Hz sampling // rate. // Reading and writing AC97 registers is another challenge. The core // provides us status bits when the read register is updated with *another* // value. When we read the same register two times (and the register still // contains the same value) these status bits are not set. We work // around this by not polling these bits but only wait a fixed delay. #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/clk.h> #include <linux/ctype.h> #include <linux/device.h> #include <linux/delay.h> #include <linux/mutex.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/dma/imx-dma.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/initval.h> #include <sound/soc.h> #include <sound/dmaengine_pcm.h> #include "fsl_ssi.h" #include "imx-pcm.h" /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ #define RX … #define TX … /** * FSLSSI_I2S_FORMATS: audio formats supported by the SSI * * The SSI has a limitation in that the samples must be in the same byte * order as the host CPU. This is because when multiple bytes are written * to the STX register, the bytes and bits must be written in the same * order. The STX is a shift register, so all the bits need to be aligned * (bit-endianness must match byte-endianness). Processors typically write * the bits within a byte in the same order that the bytes of a word are * written in. So if the host CPU is big-endian, then only big-endian * samples will be written to STX properly. */ #ifdef __BIG_ENDIAN #define FSLSSI_I2S_FORMATS … #else #define FSLSSI_I2S_FORMATS … #endif /* * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS * - Also have NB_NF to mark these two clocks will not be inverted */ #define FSLSSI_AC97_DAIFMT … #define FSLSSI_SIER_DBG_RX_FLAGS … #define FSLSSI_SIER_DBG_TX_FLAGS … enum fsl_ssi_type { … }; struct fsl_ssi_regvals { … }; static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) { … } static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) { … } static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) { … } static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config fsl_ssi_regconfig = …; struct fsl_ssi_soc_data { … }; /** * struct fsl_ssi - per-SSI private data * @regs: Pointer to the regmap registers * @irq: IRQ of this SSI * @cpu_dai_drv: CPU DAI driver for this device * @dai_fmt: DAI configuration this device is currently used with * @streams: Mask of current active streams: BIT(TX) and BIT(RX) * @i2s_net: I2S and Network mode configurations of SCR register * (this is the initial settings based on the DAI format) * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK * @use_dma: DMA is used or FIQ with stream filter * @use_dual_fifo: DMA with support for dual FIFO mode * @use_dyna_fifo: DMA with support for multi FIFO script * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree * @fifo_depth: Depth of the SSI FIFOs * @slot_width: Width of each DAI slot * @slots: Number of slots * @regvals: Specific RX/TX register settings * @clk: Clock source to access register * @baudclk: Clock source to generate bit and frame-sync clocks * @baudclk_streams: Active streams that are using baudclk * @regcache_sfcsr: Cache sfcsr register value during suspend and resume * @regcache_sacnt: Cache sacnt register value during suspend and resume * @dma_params_tx: DMA transmit parameters * @dma_params_rx: DMA receive parameters * @ssi_phys: physical address of the SSI registers * @fiq_params: FIQ stream filtering parameters * @card_pdev: Platform_device pointer to register a sound card for PowerPC or * to register a CODEC platform device for AC97 * @card_name: Platform_device name to register a sound card for PowerPC or * to register a CODEC platform device for AC97 * @card_idx: The index of SSI to register a sound card for PowerPC or * to register a CODEC platform device for AC97 * @dbg_stats: Debugging statistics * @soc: SoC specific data * @dev: Pointer to &pdev->dev * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are * @fifo_watermark or fewer words in TX fifo or * @fifo_watermark or more empty words in RX fifo. * @dma_maxburst: Max number of words to transfer in one go. So far, * this is always the same as fifo_watermark. * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations * @audio_config: configure for dma multi fifo script */ struct fsl_ssi { … }; /* * SoC specific data * * Notes: * 1) SSI in earlier SoCS has critical bits in control registers that * cannot be changed after SSI starts running -- a software reset * (set SSIEN to 0) is required to change their values. So adding * an offline_config flag for these SoCs. * 2) SDMA is available since imx35. However, imx35 does not support * DMA bits changing when SSI is running, so set offline_config. * 3) imx51 and later versions support register configurations when * SSI is running (SSIEN); For these versions, DMA needs to be * configured before SSI sends DMA request to avoid an undefined * DMA request on the SDMA side. */ static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = …; static struct fsl_ssi_soc_data fsl_ssi_imx21 = …; static struct fsl_ssi_soc_data fsl_ssi_imx35 = …; static struct fsl_ssi_soc_data fsl_ssi_imx51 = …; static const struct of_device_id fsl_ssi_ids[] = …; MODULE_DEVICE_TABLE(of, fsl_ssi_ids); static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) { … } static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi) { … } static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi) { … } /** * fsl_ssi_isr - Interrupt handler to gather states * @irq: irq number * @dev_id: context */ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) { … } /** * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with * cached values in regvals * @ssi: SSI context * @tx: direction * * Notes: * 1) For offline_config SoCs, enable all necessary bits of both streams * when 1st stream starts, even if the opposite stream will not start * 2) It also clears FIFO before setting regvals; SOR is safe to set online */ static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) { … } /* * Exclude bits that are used by the opposite stream * * When both streams are active, disabling some bits for the current stream * might break the other stream if these bits are used by it. * * @vals : regvals of the current stream * @avals: regvals of the opposite stream * @aactive: active state of the opposite stream * * 1) XOR vals and avals to get the differences if the other stream is active; * Otherwise, return current vals if the other stream is not active * 2) AND the result of 1) with the current vals */ #define _ssi_xor_shared_bits(vals, avals, aactive) … #define ssi_excl_shared_bits(vals, avals, aactive) … /** * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers * with cached values in regvals * @ssi: SSI context * @tx: direction * * Notes: * 1) For offline_config SoCs, to avoid online reconfigurations, disable all * bits of both streams at once when the last stream is abort to end * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online */ static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) { … } static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) { … } /** * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and * SCR to later set them safely * @ssi: SSI context */ static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) { … } static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) { … } static int fsl_ssi_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } /** * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock * @substream: ASoC substream * @dai: pointer to DAI * @hw_params: pointers to hw_params * * Notes: This function can be only called when using SSI as DAI master * * Quick instruction for parameters: * freq: Output BCLK frequency = samplerate * slots * slot_width * (In 2-channel I2S Master mode, slot_width is fixed 32) */ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, struct snd_soc_dai *dai, struct snd_pcm_hw_params *hw_params) { … } /** * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters * @substream: ASoC substream * @hw_params: pointers to hw_params * @dai: pointer to DAI * * Notes: * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily * disabled on offline_config SoCs. Even for online configurable SoCs * running in synchronous mode (both TX and RX use STCCR), it is not * safe to re-configure them when both two streams start running. * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the * fsl_ssi_set_bclk() if SSI is the DAI clock master. */ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *dai) { … } static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) { … } /** * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format * @dai: pointer to DAI * @fmt: format mask */ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) { … } /** * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width * @dai: pointer to DAI * @tx_mask: mask for TX * @rx_mask: mask for RX * @slots: number of slots * @slot_width: number of bits per slot */ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, u32 rx_mask, int slots, int slot_width) { … } /** * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction. * @substream: ASoC substream * @cmd: trigger command * @dai: pointer to DAI * * The DMA channel is in external master start and pause mode, which * means the SSI completely controls the flow of data. */ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops fsl_ssi_dai_ops = …; static struct snd_soc_dai_driver fsl_ssi_dai_template = …; static const struct snd_soc_component_driver fsl_ssi_component = …; static struct snd_soc_dai_driver fsl_ssi_ac97_dai = …; static struct fsl_ssi *fsl_ac97_data; static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { … } static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { … } static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = …; /** * fsl_ssi_hw_init - Initialize SSI registers * @ssi: SSI context */ static int fsl_ssi_hw_init(struct fsl_ssi *ssi) { … } /** * fsl_ssi_hw_clean - Clear SSI registers * @ssi: SSI context */ static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) { … } /* * Make every character in a string lower-case */ static void make_lowercase(char *s) { … } static int fsl_ssi_imx_probe(struct platform_device *pdev, struct fsl_ssi *ssi, void __iomem *iomem) { … } static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) { … } static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) { … } static int fsl_ssi_probe(struct platform_device *pdev) { … } static void fsl_ssi_remove(struct platform_device *pdev) { … } static int fsl_ssi_suspend(struct device *dev) { … } static int fsl_ssi_resume(struct device *dev) { … } static const struct dev_pm_ops fsl_ssi_pm = …; static struct platform_driver fsl_ssi_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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